1964 lines · cpp
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This tablegen backend is responsible for emitting a description of a target10// register file for a code generator. It uses instances of the Register,11// RegisterAliases, and RegisterClass classes to gather this information.12//13//===----------------------------------------------------------------------===//14 15#include "Basic/SequenceToOffsetTable.h"16#include "Common/CodeGenHwModes.h"17#include "Common/CodeGenRegisters.h"18#include "Common/CodeGenTarget.h"19#include "Common/InfoByHwMode.h"20#include "Common/Types.h"21#include "llvm/ADT/ArrayRef.h"22#include "llvm/ADT/BitVector.h"23#include "llvm/ADT/STLExtras.h"24#include "llvm/ADT/SetVector.h"25#include "llvm/ADT/SmallVector.h"26#include "llvm/ADT/SparseBitVector.h"27#include "llvm/ADT/Twine.h"28#include "llvm/CodeGenTypes/MachineValueType.h"29#include "llvm/Support/Casting.h"30#include "llvm/Support/CommandLine.h"31#include "llvm/Support/Format.h"32#include "llvm/Support/raw_ostream.h"33#include "llvm/TableGen/Error.h"34#include "llvm/TableGen/Record.h"35#include "llvm/TableGen/SetTheory.h"36#include "llvm/TableGen/TGTimer.h"37#include "llvm/TableGen/TableGenBackend.h"38#include <algorithm>39#include <cassert>40#include <cstddef>41#include <cstdint>42#include <deque>43#include <iterator>44#include <set>45#include <string>46#include <vector>47 48using namespace llvm;49 50static cl::OptionCategory RegisterInfoCat("Options for -gen-register-info");51 52static cl::opt<bool>53 RegisterInfoDebug("register-info-debug", cl::init(false),54 cl::desc("Dump register information to help debugging"),55 cl::cat(RegisterInfoCat));56 57namespace {58 59class RegisterInfoEmitter {60 const RecordKeeper &Records;61 const CodeGenTarget Target;62 CodeGenRegBank &RegBank;63 64public:65 RegisterInfoEmitter(const RecordKeeper &R)66 : Records(R), Target(R), RegBank(Target.getRegBank()) {67 RegBank.computeDerivedInfo();68 }69 70 // runEnums - Print out enum values for all of the registers.71 void runEnums(raw_ostream &OS, raw_ostream &MainOS, StringRef FilenamePrefix);72 73 // runMCDesc - Print out MC register descriptions.74 void runMCDesc(raw_ostream &OS, raw_ostream &MainOS,75 StringRef FilenamePrefix);76 77 // runTargetHeader - Emit a header fragment for the register info emitter.78 void runTargetHeader(raw_ostream &OS, raw_ostream &MainOS,79 StringRef FilenamePrefix);80 81 // runTargetDesc - Output the target register and register file descriptions.82 void runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,83 StringRef FilenamePrefix);84 85 // run - Output the register file description.86 TableGenOutputFiles run(StringRef FilenamePrefix);87 88 void debugDump(raw_ostream &OS);89 90private:91 void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs,92 bool isCtor);93 void EmitRegMappingTables(raw_ostream &OS,94 const std::deque<CodeGenRegister> &Regs,95 bool isCtor);96 void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName);97 void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName);98 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName);99};100 101} // end anonymous namespace102 103static void emitInclude(StringRef FilenamePrefix, StringRef IncludeFile,104 StringRef GuardMacro, raw_ostream &OS) {105 OS << "#ifdef " << GuardMacro << '\n';106 OS << "#undef " << GuardMacro << '\n';107 OS << "#include \"" << FilenamePrefix << IncludeFile << "\"\n";108 OS << "#endif\n\n";109}110 111// runEnums - Print out enum values for all of the registers.112void RegisterInfoEmitter::runEnums(raw_ostream &OS, raw_ostream &MainOS,113 StringRef FilenamePrefix) {114 emitInclude(FilenamePrefix, "Enums.inc", "GET_REGINFO_ENUM", MainOS);115 116 const auto &Registers = RegBank.getRegisters();117 118 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.119 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");120 121 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");122 123 emitSourceFileHeader("Target Register Enum Values", OS);124 125 OS << "namespace llvm {\n\n";126 127 OS << "class MCRegisterClass;\n"128 << "extern const MCRegisterClass " << Target.getName()129 << "MCRegisterClasses[];\n\n";130 131 if (!Namespace.empty())132 OS << "namespace " << Namespace << " {\n";133 OS << "enum : unsigned {\n NoRegister,\n";134 135 for (const auto &Reg : Registers)136 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";137 assert(Registers.size() == Registers.back().EnumValue &&138 "Register enum value mismatch!");139 OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n";140 OS << "};\n";141 if (!Namespace.empty())142 OS << "} // end namespace " << Namespace << "\n";143 144 const auto &RegisterClasses = RegBank.getRegClasses();145 if (!RegisterClasses.empty()) {146 147 // RegisterClass enums are stored as uint16_t in the tables.148 assert(RegisterClasses.size() <= 0xffff &&149 "Too many register classes to fit in tables");150 151 OS << "\n// Register classes\n\n";152 if (!Namespace.empty())153 OS << "namespace " << Namespace << " {\n";154 OS << "enum {\n";155 for (const auto &RC : RegisterClasses)156 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n";157 OS << "\n};\n";158 if (!Namespace.empty())159 OS << "} // end namespace " << Namespace << "\n\n";160 }161 162 ArrayRef<const Record *> RegAltNameIndices = Target.getRegAltNameIndices();163 // If the only definition is the default NoRegAltName, we don't need to164 // emit anything.165 if (RegAltNameIndices.size() > 1) {166 OS << "\n// Register alternate name indices\n\n";167 if (!Namespace.empty())168 OS << "namespace " << Namespace << " {\n";169 OS << "enum {\n";170 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)171 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";172 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";173 OS << "};\n";174 if (!Namespace.empty())175 OS << "} // end namespace " << Namespace << "\n\n";176 }177 178 auto &SubRegIndices = RegBank.getSubRegIndices();179 if (!SubRegIndices.empty()) {180 OS << "\n// Subregister indices\n\n";181 std::string Namespace = SubRegIndices.front().getNamespace();182 if (!Namespace.empty())183 OS << "namespace " << Namespace << " {\n";184 OS << "enum : uint16_t {\n NoSubRegister,\n";185 unsigned i = 0;186 for (const auto &Idx : SubRegIndices)187 OS << " " << Idx.getName() << ",\t// " << ++i << "\n";188 OS << " NUM_TARGET_SUBREGS\n};\n";189 if (!Namespace.empty())190 OS << "} // end namespace " << Namespace << "\n\n";191 }192 193 OS << "// Register pressure sets enum.\n";194 if (!Namespace.empty())195 OS << "namespace " << Namespace << " {\n";196 OS << "enum RegisterPressureSets {\n";197 unsigned NumSets = RegBank.getNumRegPressureSets();198 for (unsigned i = 0; i < NumSets; ++i) {199 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);200 OS << " " << RegUnits.Name << " = " << i << ",\n";201 }202 OS << "};\n";203 if (!Namespace.empty())204 OS << "} // end namespace " << Namespace << '\n';205 OS << '\n';206 207 OS << "} // end namespace llvm\n\n";208}209 210static void printInt(raw_ostream &OS, int Val) { OS << Val; }211 212void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,213 StringRef ClassName) {214 unsigned NumRCs = RegBank.getRegClasses().size();215 unsigned NumSets = RegBank.getNumRegPressureSets();216 217 OS << "/// Get the weight in units of pressure for this register class.\n"218 << "const RegClassWeight &" << ClassName << "::\n"219 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"220 << " static const RegClassWeight RCWeightTable[] = {\n";221 for (const auto &RC : RegBank.getRegClasses()) {222 const CodeGenRegister::Vec &Regs = RC.getMembers();223 OS << " {" << RC.getWeight(RegBank) << ", ";224 if (Regs.empty() || RC.Artificial)225 OS << '0';226 else {227 std::vector<unsigned> RegUnits;228 RC.buildRegUnitSet(RegBank, RegUnits);229 OS << RegBank.getRegUnitSetWeight(RegUnits);230 }231 OS << "}, \t// " << RC.getName() << "\n";232 }233 OS << " };\n"234 << " return RCWeightTable[RC->getID()];\n"235 << "}\n\n";236 237 // Reasonable targets (not ARMv7) have unit weight for all units, so don't238 // bother generating a table.239 bool RegUnitsHaveUnitWeight = true;240 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();241 UnitIdx < UnitEnd; ++UnitIdx) {242 if (RegBank.getRegUnit(UnitIdx).Weight > 1)243 RegUnitsHaveUnitWeight = false;244 }245 OS << "/// Get the weight in units of pressure for this register unit.\n"246 << "unsigned " << ClassName << "::\n"247 << "getRegUnitWeight(MCRegUnit RegUnit) const {\n"248 << " assert(static_cast<unsigned>(RegUnit) < "249 << RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n";250 if (!RegUnitsHaveUnitWeight) {251 OS << " static const uint8_t RUWeightTable[] = {\n ";252 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();253 UnitIdx < UnitEnd; ++UnitIdx) {254 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);255 assert(RU.Weight < 256 && "RegUnit too heavy");256 OS << RU.Weight << ", ";257 }258 OS << "};\n"259 << " return RUWeightTable[static_cast<unsigned>(RegUnit)];\n";260 } else {261 OS << " // All register units have unit weight.\n"262 << " return 1;\n";263 }264 OS << "}\n\n";265 266 OS << "\n"267 << "// Get the number of dimensions of register pressure.\n"268 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"269 << " return " << NumSets << ";\n}\n\n";270 271 OS << "// Get the name of this register unit pressure set.\n"272 << "const char *" << ClassName << "::\n"273 << "getRegPressureSetName(unsigned Idx) const {\n"274 << " static const char *PressureNameTable[] = {\n";275 unsigned MaxRegUnitWeight = 0;276 for (unsigned i = 0; i < NumSets; ++i) {277 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);278 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);279 OS << " \"" << RegUnits.Name << "\",\n";280 }281 OS << " };\n"282 << " return PressureNameTable[Idx];\n"283 << "}\n\n";284 285 OS << "// Get the register unit pressure limit for this dimension.\n"286 << "// This limit must be adjusted dynamically for reserved registers.\n"287 << "unsigned " << ClassName << "::\n"288 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const "289 "{\n"290 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32)291 << " PressureLimitTable[] = {\n";292 for (unsigned i = 0; i < NumSets; ++i) {293 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);294 OS << " " << RegUnits.Weight << ", \t// " << i << ": " << RegUnits.Name295 << "\n";296 }297 OS << " };\n"298 << " return PressureLimitTable[Idx];\n"299 << "}\n\n";300 301 SequenceToOffsetTable<std::vector<int>> PSetsSeqs(/*Terminator=*/-1);302 303 // This table may be larger than NumRCs if some register units needed a list304 // of unit sets that did not correspond to a register class.305 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();306 std::vector<std::vector<int>> PSets(NumRCUnitSets);307 308 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {309 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);310 PSets[i].reserve(PSetIDs.size());311 for (unsigned PSetID : PSetIDs) {312 PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order);313 }314 llvm::sort(PSets[i]);315 PSetsSeqs.add(PSets[i]);316 }317 318 PSetsSeqs.layout();319 320 OS << "/// Table of pressure sets per register class or unit.\n"321 << "static const int RCSetsTable[] = {\n";322 PSetsSeqs.emit(OS, printInt);323 OS << "};\n\n";324 325 OS << "/// Get the dimensions of register pressure impacted by this "326 << "register class.\n"327 << "/// Returns a -1 terminated array of pressure set IDs\n"328 << "const int *" << ClassName << "::\n"329 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";330 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)331 << " RCSetStartTable[] = {\n ";332 for (unsigned i = 0, e = NumRCs; i != e; ++i) {333 OS << PSetsSeqs.get(PSets[i]) << ",";334 }335 OS << "};\n"336 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"337 << "}\n\n";338 339 OS << "/// Get the dimensions of register pressure impacted by this "340 << "register unit.\n"341 << "/// Returns a -1 terminated array of pressure set IDs\n"342 << "const int *" << ClassName << "::\n"343 << "getRegUnitPressureSets(MCRegUnit RegUnit) const {\n"344 << " assert(static_cast<unsigned>(RegUnit) < "345 << RegBank.getNumNativeRegUnits() << " && \"invalid register unit\");\n";346 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)347 << " RUSetStartTable[] = {\n ";348 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();349 UnitIdx < UnitEnd; ++UnitIdx) {350 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])351 << ",";352 }353 OS << "};\n"354 << " return "355 "&RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];\n"356 << "}\n\n";357}358 359using DwarfRegNumsMapPair = std::pair<const Record *, std::vector<int64_t>>;360using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>;361 362static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) {363 // Sort and unique to get a map-like vector. We want the last assignment to364 // match previous behaviour.365 llvm::stable_sort(DwarfRegNums, on_first<LessRecordRegister>());366 // Warn about duplicate assignments.367 const Record *LastSeenReg = nullptr;368 for (const auto &X : DwarfRegNums) {369 const auto &Reg = X.first;370 // The only way LessRecordRegister can return equal is if they're the same371 // string. Use simple equality instead.372 if (LastSeenReg && Reg->getName() == LastSeenReg->getName())373 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +374 getQualifiedName(Reg) +375 "specified multiple times");376 LastSeenReg = Reg;377 }378 auto Last = llvm::unique(DwarfRegNums, [](const DwarfRegNumsMapPair &A,379 const DwarfRegNumsMapPair &B) {380 return A.first->getName() == B.first->getName();381 });382 DwarfRegNums.erase(Last, DwarfRegNums.end());383}384 385void RegisterInfoEmitter::EmitRegMappingTables(386 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {387 // Collect all information about dwarf register numbers388 DwarfRegNumsVecTy DwarfRegNums;389 390 // First, just pull all provided information to the map391 unsigned maxLength = 0;392 for (auto &RE : Regs) {393 const Record *Reg = RE.TheDef;394 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");395 maxLength = std::max((size_t)maxLength, RegNums.size());396 DwarfRegNums.emplace_back(Reg, std::move(RegNums));397 }398 finalizeDwarfRegNumsKeys(DwarfRegNums);399 400 if (!maxLength)401 return;402 403 // Now we know maximal length of number list. Append -1's, where needed404 for (auto &DwarfRegNum : DwarfRegNums)405 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I)406 DwarfRegNum.second.push_back(-1);407 408 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");409 410 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";411 412 // Emit reverse information about the dwarf register numbers.413 for (unsigned j = 0; j < 2; ++j) {414 for (unsigned I = 0, E = maxLength; I != E; ++I) {415 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;416 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");417 OS << I << "Dwarf2L[]";418 419 if (!isCtor) {420 OS << " = {\n";421 422 // Store the mapping sorted by the LLVM reg num so lookup can be done423 // with a binary search.424 std::map<uint64_t, const Record *> Dwarf2LMap;425 for (auto &DwarfRegNum : DwarfRegNums) {426 int DwarfRegNo = DwarfRegNum.second[I];427 if (DwarfRegNo < 0)428 continue;429 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first;430 }431 432 for (auto &I : Dwarf2LMap)433 OS << " { " << I.first << "U, " << getQualifiedName(I.second)434 << " },\n";435 436 OS << "};\n";437 } else {438 OS << ";\n";439 }440 441 // We have to store the size in a const global, it's used in multiple442 // places.443 OS << "extern const unsigned " << Namespace444 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize";445 if (!isCtor)446 OS << " = std::size(" << Namespace447 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n";448 else449 OS << ";\n\n";450 }451 }452 453 for (auto &RE : Regs) {454 const Record *Reg = RE.TheDef;455 const RecordVal *V = Reg->getValue("DwarfAlias");456 if (!V || !V->getValue())457 continue;458 459 const DefInit *DI = cast<DefInit>(V->getValue());460 const Record *Alias = DI->getDef();461 const auto &AliasIter = llvm::lower_bound(462 DwarfRegNums, Alias, [](const DwarfRegNumsMapPair &A, const Record *B) {463 return LessRecordRegister()(A.first, B);464 });465 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias &&466 "Expected Alias to be present in map");467 const auto &RegIter = llvm::lower_bound(468 DwarfRegNums, Reg, [](const DwarfRegNumsMapPair &A, const Record *B) {469 return LessRecordRegister()(A.first, B);470 });471 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg &&472 "Expected Reg to be present in map");473 RegIter->second = AliasIter->second;474 }475 476 // Emit information about the dwarf register numbers.477 for (unsigned j = 0; j < 2; ++j) {478 for (unsigned i = 0, e = maxLength; i != e; ++i) {479 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;480 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");481 OS << i << "L2Dwarf[]";482 if (!isCtor) {483 OS << " = {\n";484 // Store the mapping sorted by the Dwarf reg num so lookup can be done485 // with a binary search.486 for (auto &DwarfRegNum : DwarfRegNums) {487 int RegNo = DwarfRegNum.second[i];488 if (RegNo == -1) // -1 is the default value, don't emit a mapping.489 continue;490 491 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo492 << "U },\n";493 }494 OS << "};\n";495 } else {496 OS << ";\n";497 }498 499 // We have to store the size in a const global, it's used in multiple500 // places.501 OS << "extern const unsigned " << Namespace502 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";503 if (!isCtor)504 OS << " = std::size(" << Namespace505 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";506 else507 OS << ";\n\n";508 }509 }510}511 512void RegisterInfoEmitter::EmitRegMapping(513 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {514 // Emit the initializer so the tables from EmitRegMappingTables get wired up515 // to the MCRegisterInfo object.516 unsigned maxLength = 0;517 for (auto &RE : Regs) {518 const Record *Reg = RE.TheDef;519 maxLength = std::max((size_t)maxLength,520 Reg->getValueAsListOfInts("DwarfNumbers").size());521 }522 523 if (!maxLength)524 return;525 526 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");527 528 // Emit reverse information about the dwarf register numbers.529 for (unsigned j = 0; j < 2; ++j) {530 OS << " switch (";531 if (j == 0)532 OS << "DwarfFlavour";533 else534 OS << "EHFlavour";535 OS << ") {\n"536 << " default:\n"537 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";538 539 for (unsigned i = 0, e = maxLength; i != e; ++i) {540 OS << " case " << i << ":\n";541 OS << " ";542 if (!isCtor)543 OS << "RI->";544 std::string Tmp;545 raw_string_ostream(Tmp)546 << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i547 << "Dwarf2L";548 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";549 if (j == 0)550 OS << "false";551 else552 OS << "true";553 OS << ");\n";554 OS << " break;\n";555 }556 OS << " }\n";557 }558 559 // Emit information about the dwarf register numbers.560 for (unsigned j = 0; j < 2; ++j) {561 OS << " switch (";562 if (j == 0)563 OS << "DwarfFlavour";564 else565 OS << "EHFlavour";566 OS << ") {\n"567 << " default:\n"568 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";569 570 for (unsigned i = 0, e = maxLength; i != e; ++i) {571 OS << " case " << i << ":\n";572 OS << " ";573 if (!isCtor)574 OS << "RI->";575 std::string Tmp;576 raw_string_ostream(Tmp)577 << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i578 << "L2Dwarf";579 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";580 if (j == 0)581 OS << "false";582 else583 OS << "true";584 OS << ");\n";585 OS << " break;\n";586 }587 OS << " }\n";588 }589}590 591// Print a BitVector as a sequence of hex numbers using a little-endian mapping.592// Width is the number of bits per hex number.593static void printBitVectorAsHex(raw_ostream &OS, const BitVector &Bits,594 unsigned Width) {595 assert(Width <= 32 && "Width too large");596 unsigned Digits = (Width + 3) / 4;597 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {598 unsigned Value = 0;599 for (unsigned j = 0; j != Width && i + j != e; ++j)600 Value |= Bits.test(i + j) << j;601 OS << format("0x%0*x, ", Digits, Value);602 }603}604 605// Helper to emit a set of bits into a constant byte array.606class BitVectorEmitter {607 BitVector Values;608 609public:610 void add(unsigned v) {611 if (v >= Values.size())612 Values.resize(((v / 8) + 1) * 8); // Round up to the next byte.613 Values[v] = true;614 }615 616 void print(raw_ostream &OS) { printBitVectorAsHex(OS, Values, 8); }617};618 619static void printSimpleValueType(raw_ostream &OS, MVT VT) {620 OS << getEnumName(VT);621}622 623static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {624 OS << (Idx ? Idx->EnumValue : 0);625}626 627// Differentially encoded register and regunit lists allow for better628// compression on regular register banks. The sequence is computed from the629// differential list as:630//631// out[0] = InitVal;632// out[n+1] = out[n] + diff[n]; // n = 0, 1, ...633//634// The initial value depends on the specific list. The list is terminated by a635// 0 differential which means we can't encode repeated elements.636 637using DiffVec = SmallVector<int16_t, 4>;638using MaskVec = SmallVector<LaneBitmask, 4>;639 640// Fills V with differentials between every two consecutive elements of List.641static DiffVec &diffEncode(DiffVec &V, SparseBitVector<> List) {642 assert(V.empty() && "Clear DiffVec before diffEncode.");643 SparseBitVector<>::iterator I = List.begin(), E = List.end();644 unsigned Val = *I;645 while (++I != E) {646 unsigned Cur = *I;647 V.push_back(Cur - Val);648 Val = Cur;649 }650 return V;651}652 653template <typename Iter>654static DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {655 assert(V.empty() && "Clear DiffVec before diffEncode.");656 unsigned Val = InitVal;657 for (Iter I = Begin; I != End; ++I) {658 unsigned Cur = (*I)->EnumValue;659 V.push_back(Cur - Val);660 Val = Cur;661 }662 return V;663}664 665static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; }666 667static void printMask(raw_ostream &OS, LaneBitmask Val) {668 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')';669}670 671// Try to combine Idx's compose map into Vec if it is compatible.672// Return false if it's not possible.673static bool combine(const CodeGenSubRegIndex *Idx,674 SmallVectorImpl<const CodeGenSubRegIndex *> &Vec) {675 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();676 for (const auto &I : Map) {677 const CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];678 if (Entry && Entry != I.second)679 return false;680 }681 682 // All entries are compatible. Make it so.683 for (const auto &I : Map) {684 const CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];685 assert((!Entry || Entry == I.second) && "Expected EnumValue to be unique");686 Entry = I.second;687 }688 return true;689}690 691void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,692 StringRef ClassName) {693 const auto &SubRegIndices = RegBank.getSubRegIndices();694 695 // Many sub-register indexes are composition-compatible, meaning that696 //697 // compose(IdxA, IdxB) == compose(IdxA', IdxB)698 //699 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.700 // The illegal entries can be use as wildcards to compress the table further.701 702 // Map each Sub-register index to a compatible table row.703 SmallVector<unsigned, 4> RowMap;704 SmallVector<SmallVector<const CodeGenSubRegIndex *, 4>, 4> Rows;705 706 size_t SubRegIndicesSize = llvm::size(SubRegIndices);707 for (const auto &Idx : SubRegIndices) {708 unsigned Found = ~0u;709 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {710 if (combine(&Idx, Rows[r])) {711 Found = r;712 break;713 }714 }715 if (Found == ~0u) {716 Found = Rows.size();717 Rows.resize(Found + 1);718 Rows.back().resize(SubRegIndicesSize);719 combine(&Idx, Rows.back());720 }721 RowMap.push_back(Found);722 }723 724 OS << "unsigned " << ClassName725 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";726 727 // Output the row map if there are multiple rows.728 if (Rows.size() > 1) {729 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32)730 << " RowMap[" << SubRegIndicesSize << "] = {\n ";731 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)732 OS << RowMap[i] << ", ";733 OS << "\n };\n";734 }735 736 // Output the rows.737 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32)738 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";739 for (const auto &Row : Rows) {740 OS << " { ";741 for (const llvm::CodeGenSubRegIndex *Elem :742 ArrayRef(&Row[0], SubRegIndicesSize))743 if (Elem)744 OS << Elem->getQualifiedName() << ", ";745 else746 OS << "0, ";747 OS << "},\n";748 }749 OS << " };\n\n";750 751 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n"752 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";753 if (Rows.size() > 1)754 OS << " return Rows[RowMap[IdxA]][IdxB];\n";755 else756 OS << " return Rows[0][IdxB];\n";757 OS << "}\n\n";758 759 // Generate the reverse case.760 //761 // FIXME: This is the brute force approach. Compress the table similar to the762 // forward case.763 OS << "unsigned " << ClassName764 << "::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const "765 "{\n";766 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32)767 << " Table[" << SubRegIndicesSize << "][" << SubRegIndicesSize768 << "] = {\n";769 770 // Find values where composeSubReg(A, X) == B;771 for (const auto &IdxA : SubRegIndices) {772 OS << " { ";773 774 SmallVectorImpl<const CodeGenSubRegIndex *> &Row =775 Rows[RowMap[IdxA.EnumValue - 1]];776 for (const auto &IdxB : SubRegIndices) {777 const CodeGenSubRegIndex *FoundReverse = nullptr;778 779 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) {780 const CodeGenSubRegIndex *This = &SubRegIndices[i];781 const CodeGenSubRegIndex *Composed = Row[i];782 if (Composed == &IdxB) {783 if (FoundReverse && FoundReverse != This) // Not unique784 break;785 FoundReverse = This;786 }787 }788 789 if (FoundReverse) {790 OS << FoundReverse->getQualifiedName() << ", ";791 } else {792 OS << "0, ";793 }794 }795 OS << "},\n";796 }797 798 OS << " };\n\n";799 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"800 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";801 OS << " return Table[IdxA][IdxB];\n";802 OS << " }\n\n";803}804 805void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,806 StringRef ClassName) {807 // See the comments in computeSubRegLaneMasks() for our goal here.808 const auto &SubRegIndices = RegBank.getSubRegIndices();809 810 // Create a list of Mask+Rotate operations, with equivalent entries merged.811 SmallVector<unsigned, 4> SubReg2SequenceIndexMap;812 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences;813 for (const auto &Idx : SubRegIndices) {814 const SmallVector<MaskRolPair, 1> &IdxSequence =815 Idx.CompositionLaneMaskTransform;816 817 unsigned Found = ~0u;818 unsigned SIdx = 0;819 unsigned NextSIdx;820 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) {821 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];822 NextSIdx = SIdx + Sequence.size() + 1;823 if (Sequence == IdxSequence) {824 Found = SIdx;825 break;826 }827 }828 if (Found == ~0u) {829 Sequences.push_back(IdxSequence);830 Found = SIdx;831 }832 SubReg2SequenceIndexMap.push_back(Found);833 }834 835 OS << " struct MaskRolOp {\n"836 " LaneBitmask Mask;\n"837 " uint8_t RotateLeft;\n"838 " };\n"839 " static const MaskRolOp LaneMaskComposeSequences[] = {\n";840 unsigned Idx = 0;841 for (size_t s = 0, se = Sequences.size(); s != se; ++s) {842 OS << " ";843 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];844 for (const MaskRolPair &P : Sequence) {845 printMask(OS << "{ ", P.Mask);846 OS << format(", %2u }, ", P.RotateLeft);847 }848 OS << "{ LaneBitmask::getNone(), 0 }";849 if (s + 1 != se)850 OS << ", ";851 OS << " // Sequence " << Idx << "\n";852 Idx += Sequence.size() + 1;853 }854 auto *IntType =855 getMinimalTypeForRange(*llvm::max_element(SubReg2SequenceIndexMap));856 OS << " };\n"857 " static const "858 << IntType << " CompositeSequences[] = {\n";859 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) {860 OS << " ";861 OS << SubReg2SequenceIndexMap[i];862 if (i + 1 != e)863 OS << ",";864 OS << " // to " << SubRegIndices[i].getName() << "\n";865 }866 OS << " };\n\n";867 868 OS << "LaneBitmask " << ClassName869 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)"870 " const {\n"871 " --IdxA; assert(IdxA < "872 << SubRegIndices.size()873 << " && \"Subregister index out of bounds\");\n"874 " LaneBitmask Result;\n"875 " for (const MaskRolOp *Ops =\n"876 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n"877 " Ops->Mask.any(); ++Ops) {\n"878 " LaneBitmask::Type M = LaneMask.getAsInteger() & "879 "Ops->Mask.getAsInteger();\n"880 " if (unsigned S = Ops->RotateLeft)\n"881 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - "882 "S)));\n"883 " else\n"884 " Result |= LaneBitmask(M);\n"885 " }\n"886 " return Result;\n"887 "}\n\n";888 889 OS << "LaneBitmask " << ClassName890 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, "891 " LaneBitmask LaneMask) const {\n"892 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n"893 " --IdxA; assert(IdxA < "894 << SubRegIndices.size()895 << " && \"Subregister index out of bounds\");\n"896 " LaneBitmask Result;\n"897 " for (const MaskRolOp *Ops =\n"898 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n"899 " Ops->Mask.any(); ++Ops) {\n"900 " LaneBitmask::Type M = LaneMask.getAsInteger();\n"901 " if (unsigned S = Ops->RotateLeft)\n"902 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - "903 "S)));\n"904 " else\n"905 " Result |= LaneBitmask(M);\n"906 " }\n"907 " return Result;\n"908 "}\n\n";909}910 911//912// runMCDesc - Print out MC register descriptions.913//914void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,915 StringRef FilenamePrefix) {916 emitInclude(FilenamePrefix, "MCDesc.inc", "GET_REGINFO_MC_DESC", MainOS);917 918 emitSourceFileHeader("MC Register Information", OS);919 920 const auto &Regs = RegBank.getRegisters();921 922 auto &SubRegIndices = RegBank.getSubRegIndices();923 // The lists of sub-registers and super-registers go in the same array. That924 // allows us to share suffixes.925 using RegVec = std::vector<const CodeGenRegister *>;926 927 // Differentially encoded lists.928 SequenceToOffsetTable<DiffVec> DiffSeqs;929 SmallVector<DiffVec, 4> SubRegLists(Regs.size());930 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());931 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());932 933 // List of lane masks accompanying register unit sequences.934 SequenceToOffsetTable<MaskVec> LaneMaskSeqs(/*Terminator=*/std::nullopt);935 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());936 937 // Keep track of sub-register names as well. These are not differentially938 // encoded.939 using SubRegIdxVec = SmallVector<const CodeGenSubRegIndex *, 4>;940 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs(941 /*Terminator=*/std::nullopt);942 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());943 944 SequenceToOffsetTable<std::string> RegStrings;945 946 // Precompute register lists for the SequenceToOffsetTable.947 unsigned i = 0;948 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {949 const auto &Reg = *I;950 RegStrings.add(Reg.getName().str());951 952 // Compute the ordered sub-register list.953 SetVector<const CodeGenRegister *> SR;954 Reg.addSubRegsPreOrder(SR, RegBank);955 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());956 DiffSeqs.add(SubRegLists[i]);957 958 // Compute the corresponding sub-register indexes.959 SubRegIdxVec &SRIs = SubRegIdxLists[i];960 for (const CodeGenRegister *S : SR)961 SRIs.push_back(Reg.getSubRegIndex(S));962 SubRegIdxSeqs.add(SRIs);963 964 // Super-registers are already computed.965 const RegVec &SuperRegList = Reg.getSuperRegs();966 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),967 SuperRegList.end());968 DiffSeqs.add(SuperRegLists[i]);969 970 const SparseBitVector<> &RUs = Reg.getNativeRegUnits();971 DiffSeqs.add(diffEncode(RegUnitLists[i], RUs));972 973 const auto &RUMasks = Reg.getRegUnitLaneMasks();974 MaskVec &LaneMaskVec = RegUnitLaneMasks[i];975 assert(LaneMaskVec.empty());976 llvm::append_range(LaneMaskVec, RUMasks);977 LaneMaskSeqs.add(LaneMaskVec);978 }979 980 // Compute the final layout of the sequence table.981 DiffSeqs.layout();982 LaneMaskSeqs.layout();983 SubRegIdxSeqs.layout();984 985 OS << "namespace llvm {\n\n";986 987 const std::string &TargetName = Target.getName().str();988 989 // Emit the shared table of differential lists.990 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n";991 DiffSeqs.emit(OS, printDiff16);992 OS << "};\n\n";993 994 // Emit the shared table of regunit lane mask sequences.995 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n";996 LaneMaskSeqs.emit(OS, printMask);997 OS << "};\n\n";998 999 // Emit the table of sub-register indexes.1000 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";1001 SubRegIdxSeqs.emit(OS, printSubRegIndex);1002 OS << "};\n\n";1003 1004 // Emit the string table.1005 RegStrings.layout();1006 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName +1007 "RegStrings[]");1008 1009 OS << "extern const MCRegisterDesc " << TargetName1010 << "RegDesc[] = { // Descriptors\n";1011 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0, 0, 0 },\n";1012 1013 // Emit the register descriptors now.1014 i = 0;1015 for (const auto &Reg : Regs) {1016 unsigned FirstRU = Reg.getNativeRegUnits().find_first();1017 unsigned Offset = DiffSeqs.get(RegUnitLists[i]);1018 // The value must be kept in sync with MCRegisterInfo.h.1019 constexpr unsigned RegUnitBits = 12;1020 assert(isUInt<RegUnitBits>(FirstRU) && "Too many regunits");1021 assert(isUInt<32 - RegUnitBits>(Offset) && "Offset is too big");1022 OS << " { " << RegStrings.get(Reg.getName().str()) << ", "1023 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])1024 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "1025 << (Offset << RegUnitBits | FirstRU) << ", "1026 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << ", " << Reg.Constant << ", "1027 << Reg.Artificial << " },\n";1028 ++i;1029 }1030 OS << "};\n\n"; // End of register descriptors...1031 1032 // Emit the table of register unit roots. Each regunit has one or two root1033 // registers.1034 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";1035 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {1036 ArrayRef<const CodeGenRegister *> Roots = RegBank.getRegUnit(i).getRoots();1037 assert(!Roots.empty() && "All regunits must have a root register.");1038 assert(Roots.size() <= 2 && "More than two roots not supported yet.");1039 OS << " { ";1040 ListSeparator LS;1041 for (const CodeGenRegister *R : Roots)1042 OS << LS << getQualifiedName(R->TheDef);1043 OS << " },\n";1044 }1045 OS << "};\n\n";1046 1047 const auto &RegisterClasses = RegBank.getRegClasses();1048 1049 // Loop over all of the register classes... emitting each one.1050 OS << "namespace { // Register classes...\n";1051 1052 SequenceToOffsetTable<std::string> RegClassStrings;1053 1054 // Emit the register enum value arrays for each RegisterClass1055 for (const auto &RC : RegisterClasses) {1056 ArrayRef<const Record *> Order = RC.getOrder();1057 1058 // Give the register class a legal C name if it's anonymous.1059 const std::string &Name = RC.getName();1060 1061 RegClassStrings.add(Name);1062 1063 // Emit the register list now (unless it would be a zero-length array).1064 if (!Order.empty()) {1065 OS << " // " << Name << " Register Class...\n"1066 << " const MCPhysReg " << Name << "[] = {\n ";1067 for (const Record *Reg : Order) {1068 OS << getQualifiedName(Reg) << ", ";1069 }1070 OS << "\n };\n\n";1071 1072 OS << " // " << Name << " Bit set.\n"1073 << " const uint8_t " << Name << "Bits[] = {\n ";1074 BitVectorEmitter BVE;1075 for (const Record *Reg : Order) {1076 BVE.add(RegBank.getReg(Reg)->EnumValue);1077 }1078 BVE.print(OS);1079 OS << "\n };\n\n";1080 }1081 }1082 OS << "} // end anonymous namespace\n\n";1083 1084 RegClassStrings.layout();1085 RegClassStrings.emitStringLiteralDef(1086 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]");1087 1088 OS << "extern const MCRegisterClass " << TargetName1089 << "MCRegisterClasses[] = {\n";1090 1091 for (const auto &RC : RegisterClasses) {1092 ArrayRef<const Record *> Order = RC.getOrder();1093 std::string RCName = Order.empty() ? "nullptr" : RC.getName();1094 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits";1095 std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName + ")";1096 uint32_t RegSize = 0;1097 if (RC.RSI.isSimple())1098 RegSize = RC.RSI.getSimple().RegSize;1099 OS << " { " << RCName << ", " << RCBitsName << ", "1100 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size()1101 << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", "1102 << RegSize << ", " << static_cast<unsigned>(RC.CopyCost) << ", "1103 << (RC.Allocatable ? "true" : "false") << ", "1104 << (RC.getBaseClassOrder() ? "true" : "false") << " },\n";1105 }1106 1107 OS << "};\n\n";1108 1109 EmitRegMappingTables(OS, Regs, false);1110 1111 // Emit Reg encoding table1112 OS << "extern const uint16_t " << TargetName;1113 OS << "RegEncodingTable[] = {\n";1114 // Add entry for NoRegister1115 OS << " 0,\n";1116 for (const auto &RE : Regs) {1117 const Record *Reg = RE.TheDef;1118 const BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");1119 uint64_t Value = BI->convertKnownBitsToInt();1120 OS << " " << Value << ",\n";1121 }1122 OS << "};\n"; // End of HW encoding table1123 1124 // MCRegisterInfo initialization routine.1125 OS << "static inline void Init" << TargetName1126 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "1127 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "1128 "{\n"1129 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "1130 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "1131 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "1132 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "1133 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "1134 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "1135 << (llvm::size(SubRegIndices) + 1) << ",\n"1136 << TargetName << "RegEncodingTable);\n\n";1137 1138 EmitRegMapping(OS, Regs, false);1139 1140 OS << "}\n\n";1141 1142 OS << "} // end namespace llvm\n\n";1143}1144 1145void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS,1146 StringRef FilenamePrefix) {1147 emitInclude(FilenamePrefix, "Header.inc", "GET_REGINFO_HEADER", MainOS);1148 1149 emitSourceFileHeader("Register Information Header Fragment", OS);1150 1151 const std::string &TargetName = Target.getName().str();1152 std::string ClassName = TargetName + "GenRegisterInfo";1153 1154 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n";1155 1156 OS << "namespace llvm {\n\n";1157 1158 OS << "class " << TargetName << "FrameLowering;\n\n";1159 1160 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"1161 << " explicit " << ClassName1162 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n"1163 << " unsigned PC = 0, unsigned HwMode = 0);\n";1164 if (!RegBank.getSubRegIndices().empty()) {1165 OS << " unsigned composeSubRegIndicesImpl"1166 << "(unsigned, unsigned) const override;\n"1167 << " unsigned reverseComposeSubRegIndicesImpl"1168 << "(unsigned, unsigned) const override;\n"1169 << " LaneBitmask composeSubRegIndexLaneMaskImpl"1170 << "(unsigned, LaneBitmask) const override;\n"1171 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl"1172 << "(unsigned, LaneBitmask) const override;\n"1173 << " const TargetRegisterClass *getSubClassWithSubReg"1174 << "(const TargetRegisterClass *, unsigned) const override;\n"1175 << " const TargetRegisterClass *getSubRegisterClass"1176 << "(const TargetRegisterClass *, unsigned) const override;\n";1177 }1178 OS << " const RegClassWeight &getRegClassWeight("1179 << "const TargetRegisterClass *RC) const override;\n"1180 << " unsigned getRegUnitWeight(MCRegUnit RegUnit) const override;\n"1181 << " unsigned getNumRegPressureSets() const override;\n"1182 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"1183 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned "1184 "Idx) const override;\n"1185 << " const int *getRegClassPressureSets("1186 << "const TargetRegisterClass *RC) const override;\n"1187 << " const int *getRegUnitPressureSets("1188 << "MCRegUnit RegUnit) const override;\n"1189 << " ArrayRef<const char *> getRegMaskNames() const override;\n"1190 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n"1191 << " bool isGeneralPurposeRegister(const MachineFunction &, "1192 << "MCRegister) const override;\n"1193 << " bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)"1194 << " const override;\n"1195 << " bool isFixedRegister(const MachineFunction &, "1196 << "MCRegister) const override;\n"1197 << " bool isArgumentRegister(const MachineFunction &, "1198 << "MCRegister) const override;\n"1199 << " bool isConstantPhysReg(MCRegister PhysReg) const override final;\n"1200 << " /// Devirtualized TargetFrameLowering.\n"1201 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n"1202 << " const MachineFunction &MF);\n";1203 1204 const auto &RegisterClasses = RegBank.getRegClasses();1205 if (llvm::any_of(RegisterClasses,1206 [](const auto &RC) { return RC.getBaseClassOrder(); })) {1207 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) "1208 "const override;\n";1209 }1210 1211 OS << "};\n\n";1212 1213 if (!RegisterClasses.empty()) {1214 OS << "namespace " << RegisterClasses.front().Namespace1215 << " { // Register classes\n";1216 1217 for (const auto &RC : RegisterClasses) {1218 const std::string &Name = RC.getName();1219 1220 // Output the extern for the instance.1221 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";1222 }1223 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n";1224 }1225 OS << "} // end namespace llvm\n\n";1226}1227 1228//1229// runTargetDesc - Output the target register and register file descriptions.1230//1231void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,1232 StringRef FilenamePrefix) {1233 emitInclude(FilenamePrefix, "TargetDesc.inc", "GET_REGINFO_TARGET_DESC",1234 MainOS);1235 1236 emitSourceFileHeader("Target Register and Register Classes Information", OS);1237 1238 OS << "namespace llvm {\n\n";1239 1240 // Get access to MCRegisterClass data.1241 OS << "extern const MCRegisterClass " << Target.getName()1242 << "MCRegisterClasses[];\n";1243 1244 // Start out by emitting each of the register classes.1245 const auto &RegisterClasses = RegBank.getRegClasses();1246 const auto &SubRegIndices = RegBank.getSubRegIndices();1247 1248 // Collect all registers belonging to any allocatable class.1249 std::set<const Record *> AllocatableRegs;1250 1251 // Collect allocatable registers.1252 for (const auto &RC : RegisterClasses) {1253 ArrayRef<const Record *> Order = RC.getOrder();1254 1255 if (RC.Allocatable)1256 AllocatableRegs.insert(Order.begin(), Order.end());1257 }1258 1259 const CodeGenHwModes &CGH = Target.getHwModes();1260 unsigned NumModes = CGH.getNumModeIds();1261 1262 // Build a shared array of value types.1263 SequenceToOffsetTable<std::vector<MVT>> VTSeqs(1264 /*Terminator=*/MVT::Other);1265 for (unsigned M = 0; M < NumModes; ++M) {1266 for (const auto &RC : RegisterClasses) {1267 std::vector<MVT> S;1268 for (const ValueTypeByHwMode &VVT : RC.VTs)1269 if (VVT.hasDefault() || VVT.hasMode(M))1270 S.push_back(VVT.get(M));1271 VTSeqs.add(S);1272 }1273 }1274 VTSeqs.layout();1275 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";1276 VTSeqs.emit(OS, printSimpleValueType);1277 OS << "};\n";1278 1279 // Emit SubRegIndex names, skipping 0.1280 OS << "\nstatic const char *SubRegIndexNameTable[] = { \"";1281 1282 for (const auto &Idx : SubRegIndices) {1283 OS << Idx.getName();1284 OS << "\", \"";1285 }1286 OS << "\" };\n\n";1287 1288 // Emit the table of sub-register index sizes.1289 OS << "static const TargetRegisterInfo::SubRegCoveredBits "1290 "SubRegIdxRangeTable[] = {\n";1291 for (unsigned M = 0; M < NumModes; ++M) {1292 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";1293 for (const auto &Idx : SubRegIndices) {1294 const SubRegRange &Range = Idx.Range.get(M);1295 OS << " { " << Range.Offset << ", " << Range.Size << " },\t// "1296 << Idx.getName() << "\n";1297 }1298 }1299 OS << "};\n\n";1300 1301 // Emit SubRegIndex lane masks, including 0.1302 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n "1303 "LaneBitmask::getAll(),\n";1304 for (const auto &Idx : SubRegIndices) {1305 printMask(OS << " ", Idx.LaneMask);1306 OS << ", // " << Idx.getName() << '\n';1307 }1308 OS << " };\n\n";1309 1310 OS << "\n";1311 1312 // Now that all of the structs have been emitted, emit the instances.1313 if (!RegisterClasses.empty()) {1314 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]"1315 << " = {\n";1316 for (unsigned M = 0; M < NumModes; ++M) {1317 unsigned EV = 0;1318 OS << " // Mode = " << M << " (";1319 if (M == 0)1320 OS << "Default";1321 else1322 OS << CGH.getMode(M).Name;1323 OS << ")\n";1324 for (const auto &RC : RegisterClasses) {1325 assert(RC.EnumValue == EV && "Unexpected order of register classes");1326 ++EV;1327 (void)EV;1328 const RegSizeInfo &RI = RC.RSI.get(M);1329 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", "1330 << RI.SpillAlignment;1331 std::vector<MVT> VTs;1332 for (const ValueTypeByHwMode &VVT : RC.VTs)1333 if (VVT.hasDefault() || VVT.hasMode(M))1334 VTs.push_back(VVT.get(M));1335 OS << ", /*VTLists+*/" << VTSeqs.get(VTs) << " }, // "1336 << RC.getName() << '\n';1337 }1338 }1339 OS << "};\n";1340 1341 // Emit register class bit mask tables. The first bit mask emitted for a1342 // register class, RC, is the set of sub-classes, including RC itself.1343 //1344 // If RC has super-registers, also create a list of subreg indices and bit1345 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,1346 // SuperRC, that satisfies:1347 //1348 // For all SuperReg in SuperRC: SuperReg:Idx in RC1349 //1350 // The 0-terminated list of subreg indices starts at:1351 //1352 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...1353 //1354 // The corresponding bitmasks follow the sub-class mask in memory. Each1355 // mask has RCMaskWords uint32_t entries.1356 //1357 // Every bit mask present in the list has at least one bit set.1358 1359 // Compress the sub-reg index lists.1360 using IdxList = std::vector<const CodeGenSubRegIndex *>;1361 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());1362 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs;1363 BitVector MaskBV(RegisterClasses.size());1364 1365 for (const auto &RC : RegisterClasses) {1366 OS << "static const uint32_t " << RC.getName()1367 << "SubClassMask[] = {\n ";1368 printBitVectorAsHex(OS, RC.getSubClasses(), 32);1369 1370 // Emit super-reg class masks for any relevant SubRegIndices that can1371 // project into RC.1372 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];1373 for (auto &Idx : SubRegIndices) {1374 MaskBV.reset();1375 RC.getSuperRegClasses(&Idx, MaskBV);1376 if (MaskBV.none())1377 continue;1378 SRIList.push_back(&Idx);1379 OS << "\n ";1380 printBitVectorAsHex(OS, MaskBV, 32);1381 OS << "// " << Idx.getName();1382 }1383 SuperRegIdxSeqs.add(SRIList);1384 OS << "\n};\n\n";1385 }1386 1387 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";1388 SuperRegIdxSeqs.layout();1389 SuperRegIdxSeqs.emit(OS, printSubRegIndex);1390 OS << "};\n\n";1391 1392 // Emit super-class lists.1393 for (const auto &RC : RegisterClasses) {1394 ArrayRef<CodeGenRegisterClass *> Supers = RC.getSuperClasses();1395 1396 // Skip classes without supers.1397 if (Supers.empty())1398 continue;1399 1400 OS << "static unsigned const " << RC.getName() << "Superclasses[] = {\n";1401 for (const auto *Super : Supers)1402 OS << " " << Super->getQualifiedIdName() << ",\n";1403 OS << "};\n\n";1404 }1405 1406 // Emit methods.1407 for (const auto &RC : RegisterClasses) {1408 if (!RC.AltOrderSelect.empty()) {1409 OS << "\nstatic inline unsigned " << RC.getName()1410 << "AltOrderSelect(const MachineFunction &MF, bool Rev) {"1411 << RC.AltOrderSelect << "}\n\n"1412 << "static ArrayRef<MCPhysReg> " << RC.getName()1413 << "GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {\n";1414 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) {1415 ArrayRef<const Record *> Elems = RC.getOrder(oi);1416 if (!Elems.empty()) {1417 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";1418 for (unsigned elem = 0; elem != Elems.size(); ++elem)1419 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);1420 OS << " };\n";1421 }1422 }1423 OS << " const MCRegisterClass &MCR = " << Target.getName()1424 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"1425 << " const ArrayRef<MCPhysReg> Order[] = {\n"1426 << " ArrayRef(MCR.begin(), MCR.getNumRegs()";1427 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)1428 if (RC.getOrder(oi).empty())1429 OS << "),\n ArrayRef<MCPhysReg>(";1430 else1431 OS << "),\n ArrayRef(AltOrder" << oi;1432 OS << ")\n };\n const unsigned Select = " << RC.getName()1433 << "AltOrderSelect(MF, Rev);\n assert(Select < "1434 << RC.getNumOrders() << ");\n return Order[Select];\n}\n";1435 }1436 }1437 1438 // Now emit the actual value-initialized register class instances.1439 OS << "\nnamespace " << RegisterClasses.front().Namespace1440 << " { // Register class instances\n";1441 1442 for (const auto &RC : RegisterClasses) {1443 OS << " extern const TargetRegisterClass " << RC.getName()1444 << "RegClass = {\n " << '&' << Target.getName()1445 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "1446 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "1447 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n ";1448 printMask(OS, RC.LaneMask);1449 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n "1450 << (RC.GlobalPriority ? "true" : "false") << ",\n "1451 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n "1452 << (RC.HasDisjunctSubRegs ? "true" : "false")1453 << ", /* HasDisjunctSubRegs */\n "1454 << (RC.CoveredBySubRegs ? "true" : "false")1455 << ", /* CoveredBySubRegs */\n ";1456 if (RC.getSuperClasses().empty())1457 OS << "nullptr, ";1458 else1459 OS << RC.getName() << "Superclasses, ";1460 OS << RC.getSuperClasses().size() << ",\n ";1461 if (RC.AltOrderSelect.empty())1462 OS << "nullptr\n";1463 else1464 OS << RC.getName() << "GetRawAllocationOrder\n";1465 OS << " };\n\n";1466 }1467 1468 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";1469 }1470 1471 OS << "\nnamespace {\n";1472 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n";1473 for (const auto &RC : RegisterClasses)1474 OS << " &" << RC.getQualifiedName() << "RegClass,\n";1475 OS << " };\n";1476 OS << "} // end anonymous namespace\n";1477 1478 // Emit extra information about registers.1479 const std::string &TargetName = Target.getName().str();1480 const auto &Regs = RegBank.getRegisters();1481 unsigned NumRegCosts = 1;1482 for (const auto &Reg : Regs)1483 NumRegCosts = std::max((size_t)NumRegCosts, Reg.CostPerUse.size());1484 1485 std::vector<unsigned> AllRegCostPerUse;1486 llvm::BitVector InAllocClass(Regs.size() + 1, false);1487 AllRegCostPerUse.insert(AllRegCostPerUse.end(), NumRegCosts, 0);1488 1489 // Populate the vector RegCosts with the CostPerUse list of the registers1490 // in the order they are read. Have at most NumRegCosts entries for1491 // each register. Fill with zero for values which are not explicitly given.1492 for (const auto &Reg : Regs) {1493 auto Costs = Reg.CostPerUse;1494 llvm::append_range(AllRegCostPerUse, Costs);1495 if (NumRegCosts > Costs.size())1496 AllRegCostPerUse.insert(AllRegCostPerUse.end(),1497 NumRegCosts - Costs.size(), 0);1498 1499 if (AllocatableRegs.count(Reg.TheDef))1500 InAllocClass.set(Reg.EnumValue);1501 }1502 1503 // Emit the cost values as a 1D-array after grouping them by their indices,1504 // i.e. the costs for all registers corresponds to index 0, 1, 2, etc.1505 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1).1506 OS << "\nstatic const uint8_t "1507 << "CostPerUseTable[] = { \n";1508 for (unsigned int I = 0; I < NumRegCosts; ++I) {1509 for (unsigned J = I, E = AllRegCostPerUse.size(); J < E; J += NumRegCosts)1510 OS << AllRegCostPerUse[J] << ", ";1511 }1512 OS << "};\n\n";1513 1514 OS << "\nstatic const bool "1515 << "InAllocatableClassTable[] = { \n";1516 for (unsigned I = 0, E = InAllocClass.size(); I < E; ++I) {1517 OS << (InAllocClass[I] ? "true" : "false") << ", ";1518 }1519 OS << "};\n\n";1520 1521 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName1522 << "RegInfoDesc = { // Extra Descriptors\n";1523 OS << "CostPerUseTable, " << NumRegCosts << ", "1524 << "InAllocatableClassTable";1525 OS << "};\n\n"; // End of register descriptors...1526 1527 std::string ClassName = Target.getName().str() + "GenRegisterInfo";1528 1529 size_t SubRegIndicesSize = llvm::size(SubRegIndices);1530 1531 if (!SubRegIndices.empty()) {1532 emitComposeSubRegIndices(OS, ClassName);1533 emitComposeSubRegIndexLaneMask(OS, ClassName);1534 }1535 1536 if (!SubRegIndices.empty()) {1537 // Emit getSubClassWithSubReg.1538 OS << "const TargetRegisterClass *" << ClassName1539 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"1540 << " const {\n";1541 // Use the smallest type that can hold a regclass ID with room for a1542 // sentinel.1543 if (RegisterClasses.size() <= UINT8_MAX)1544 OS << " static const uint8_t Table[";1545 else if (RegisterClasses.size() <= UINT16_MAX)1546 OS << " static const uint16_t Table[";1547 else1548 PrintFatalError("Too many register classes.");1549 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";1550 for (const auto &RC : RegisterClasses) {1551 OS << " {\t// " << RC.getName() << "\n";1552 for (auto &Idx : SubRegIndices) {1553 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))1554 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()1555 << " -> " << SRC->getName() << "\n";1556 else1557 OS << " 0,\t// " << Idx.getName() << "\n";1558 }1559 OS << " },\n";1560 }1561 OS << " };\n assert(RC && \"Missing regclass\");\n"1562 << " if (!Idx) return RC;\n --Idx;\n"1563 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"1564 << " unsigned TV = Table[RC->getID()][Idx];\n"1565 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";1566 1567 // Emit getSubRegisterClass1568 OS << "const TargetRegisterClass *" << ClassName1569 << "::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx)"1570 << " const {\n";1571 1572 // Use the smallest type that can hold a regclass ID with room for a1573 // sentinel.1574 if (RegisterClasses.size() <= UINT8_MAX)1575 OS << " static const uint8_t Table[";1576 else if (RegisterClasses.size() <= UINT16_MAX)1577 OS << " static const uint16_t Table[";1578 else1579 PrintFatalError("Too many register classes.");1580 1581 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";1582 1583 for (const auto &RC : RegisterClasses) {1584 OS << " {\t// " << RC.getName() << '\n';1585 for (auto &Idx : SubRegIndices) {1586 std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>1587 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx);1588 1589 unsigned EnumValue = 0;1590 if (MatchingSubClass) {1591 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second;1592 EnumValue = SubRegClass->EnumValue + 1;1593 }1594 1595 OS << " " << EnumValue << ",\t// " << RC.getName() << ':'1596 << Idx.getName();1597 1598 if (MatchingSubClass) {1599 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second;1600 OS << " -> " << SubRegClass->getName();1601 }1602 1603 OS << '\n';1604 }1605 1606 OS << " },\n";1607 }1608 OS << " };\n assert(RC && \"Missing regclass\");\n"1609 << " if (!Idx) return RC;\n --Idx;\n"1610 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"1611 << " unsigned TV = Table[RC->getID()][Idx];\n"1612 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";1613 }1614 1615 EmitRegUnitPressure(OS, ClassName);1616 1617 // Emit register base class mapper1618 if (!RegisterClasses.empty()) {1619 // Collect base classes1620 SmallVector<const CodeGenRegisterClass *> BaseClasses;1621 for (const auto &RC : RegisterClasses) {1622 if (RC.getBaseClassOrder())1623 BaseClasses.push_back(&RC);1624 }1625 if (!BaseClasses.empty()) {1626 assert(BaseClasses.size() < UINT16_MAX &&1627 "Too many base register classes");1628 1629 // Apply order1630 struct BaseClassOrdering {1631 bool operator()(const CodeGenRegisterClass *LHS,1632 const CodeGenRegisterClass *RHS) const {1633 return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) <1634 std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue);1635 }1636 };1637 llvm::stable_sort(BaseClasses, BaseClassOrdering());1638 1639 OS << "\n// Register to base register class mapping\n\n";1640 OS << "\n";1641 OS << "const TargetRegisterClass *" << ClassName1642 << "::getPhysRegBaseClass(MCRegister Reg)"1643 << " const {\n";1644 OS << " static const uint16_t InvalidRegClassID = UINT16_MAX;\n\n";1645 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n";1646 OS << " InvalidRegClassID, // NoRegister\n";1647 for (const CodeGenRegister &Reg : Regs) {1648 const CodeGenRegisterClass *BaseRC = nullptr;1649 for (const CodeGenRegisterClass *RC : BaseClasses) {1650 if (RC->contains(&Reg)) {1651 BaseRC = RC;1652 break;1653 }1654 }1655 1656 OS << " "1657 << (BaseRC ? BaseRC->getQualifiedIdName() : "InvalidRegClassID")1658 << ", // " << Reg.getName() << "\n";1659 }1660 OS << " };\n\n"1661 " assert(Reg < ArrayRef(Mapping).size());\n"1662 " unsigned RCID = Mapping[Reg.id()];\n"1663 " if (RCID == InvalidRegClassID)\n"1664 " return nullptr;\n"1665 " return RegisterClasses[RCID];\n"1666 "}\n";1667 }1668 }1669 1670 // Emit the constructor of the class...1671 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";1672 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n";1673 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n";1674 OS << "extern const char " << TargetName << "RegStrings[];\n";1675 OS << "extern const char " << TargetName << "RegClassStrings[];\n";1676 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";1677 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";1678 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";1679 1680 EmitRegMappingTables(OS, Regs, true);1681 1682 OS << ClassName << "::\n"1683 << ClassName1684 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n"1685 " unsigned PC, unsigned HwMode)\n"1686 << " : TargetRegisterInfo(&" << TargetName << "RegInfoDesc"1687 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n"1688 << " SubRegIndexNameTable, SubRegIdxRangeTable, "1689 "SubRegIndexLaneMaskTable,\n"1690 << " ";1691 printMask(OS, RegBank.CoveringLanes);1692 OS << ", RegClassInfos, VTLists, HwMode) {\n"1693 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 11694 << ", RA, PC,\n " << TargetName1695 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"1696 << " " << TargetName << "RegUnitRoots,\n"1697 << " " << RegBank.getNumNativeRegUnits() << ",\n"1698 << " " << TargetName << "RegDiffLists,\n"1699 << " " << TargetName << "LaneMaskLists,\n"1700 << " " << TargetName << "RegStrings,\n"1701 << " " << TargetName << "RegClassStrings,\n"1702 << " " << TargetName << "SubRegIdxLists,\n"1703 << " " << SubRegIndicesSize + 1 << ",\n"1704 << " " << TargetName << "RegEncodingTable);\n\n";1705 1706 EmitRegMapping(OS, Regs, true);1707 1708 OS << "}\n\n";1709 1710 // Emit CalleeSavedRegs information.1711 ArrayRef<const Record *> CSRSets =1712 Records.getAllDerivedDefinitions("CalleeSavedRegs");1713 for (const Record *CSRSet : CSRSets) {1714 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);1715 assert(Regs && "Cannot expand CalleeSavedRegs instance");1716 1717 // Emit the *_SaveList list of callee-saved registers.1718 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { ";1719 for (const Record *Reg : *Regs)1720 OS << getQualifiedName(Reg) << ", ";1721 OS << "0 };\n";1722 1723 // Emit the *_RegMask bit mask of call-preserved registers.1724 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);1725 1726 // Check for an optional OtherPreserved set.1727 // Add those registers to RegMask, but not to SaveList.1728 if (const DagInit *OPDag =1729 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {1730 SetTheory::RecSet OPSet;1731 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());1732 Covered |= RegBank.computeCoveredRegisters(OPSet.getArrayRef());1733 }1734 1735 // Add all constant physical registers to the preserved mask:1736 SetTheory::RecSet ConstantSet;1737 for (const auto &Reg : RegBank.getRegisters()) {1738 if (Reg.Constant)1739 ConstantSet.insert(Reg.TheDef);1740 }1741 Covered |= RegBank.computeCoveredRegisters(ConstantSet.getArrayRef());1742 1743 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { ";1744 printBitVectorAsHex(OS, Covered, 32);1745 OS << "};\n";1746 }1747 OS << "\n\n";1748 1749 OS << "ArrayRef<const uint32_t *> " << ClassName1750 << "::getRegMasks() const {\n";1751 if (!CSRSets.empty()) {1752 OS << " static const uint32_t *const Masks[] = {\n";1753 for (const Record *CSRSet : CSRSets)1754 OS << " " << CSRSet->getName() << "_RegMask,\n";1755 OS << " };\n";1756 OS << " return ArrayRef(Masks);\n";1757 } else {1758 OS << " return {};\n";1759 }1760 OS << "}\n\n";1761 1762 const std::list<CodeGenRegisterCategory> &RegCategories =1763 RegBank.getRegCategories();1764 OS << "bool " << ClassName << "::\n"1765 << "isGeneralPurposeRegister(const MachineFunction &MF, "1766 << "MCRegister PhysReg) const {\n"1767 << " return\n";1768 for (const CodeGenRegisterCategory &Category : RegCategories)1769 if (Category.getName() == "GeneralPurposeRegisters") {1770 for (const CodeGenRegisterClass *RC : Category.getClasses())1771 OS << " " << RC->getQualifiedName()1772 << "RegClass.contains(PhysReg) ||\n";1773 break;1774 }1775 OS << " false;\n";1776 OS << "}\n\n";1777 1778 OS << "bool " << ClassName << "::\n"1779 << "isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)"1780 << " const {\n"1781 << " return\n";1782 for (const CodeGenRegisterCategory &Category : RegCategories)1783 if (Category.getName() == "GeneralPurposeRegisters") {1784 for (const CodeGenRegisterClass *RC : Category.getClasses())1785 OS << " " << RC->getQualifiedName()1786 << "RegClass.hasSubClassEq(RC) ||\n";1787 break;1788 }1789 OS << " false;\n";1790 OS << "}\n\n";1791 1792 OS << "bool " << ClassName << "::\n"1793 << "isFixedRegister(const MachineFunction &MF, "1794 << "MCRegister PhysReg) const {\n"1795 << " return\n";1796 for (const CodeGenRegisterCategory &Category : RegCategories)1797 if (Category.getName() == "FixedRegisters") {1798 for (const CodeGenRegisterClass *RC : Category.getClasses())1799 OS << " " << RC->getQualifiedName()1800 << "RegClass.contains(PhysReg) ||\n";1801 break;1802 }1803 OS << " false;\n";1804 OS << "}\n\n";1805 1806 OS << "bool " << ClassName << "::\n"1807 << "isArgumentRegister(const MachineFunction &MF, "1808 << "MCRegister PhysReg) const {\n"1809 << " return\n";1810 for (const CodeGenRegisterCategory &Category : RegCategories)1811 if (Category.getName() == "ArgumentRegisters") {1812 for (const CodeGenRegisterClass *RC : Category.getClasses())1813 OS << " " << RC->getQualifiedName()1814 << "RegClass.contains(PhysReg) ||\n";1815 break;1816 }1817 OS << " false;\n";1818 OS << "}\n\n";1819 1820 OS << "bool " << ClassName << "::\n"1821 << "isConstantPhysReg(MCRegister PhysReg) const {\n"1822 << " return\n";1823 for (const auto &Reg : Regs)1824 if (Reg.Constant)1825 OS << " PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n";1826 OS << " false;\n";1827 OS << "}\n\n";1828 1829 OS << "ArrayRef<const char *> " << ClassName1830 << "::getRegMaskNames() const {\n";1831 if (!CSRSets.empty()) {1832 OS << " static const char *Names[] = {\n";1833 for (const Record *CSRSet : CSRSets)1834 OS << " " << '"' << CSRSet->getName() << '"' << ",\n";1835 OS << " };\n";1836 OS << " return ArrayRef(Names);\n";1837 } else {1838 OS << " return {};\n";1839 }1840 OS << "}\n\n";1841 1842 OS << "const " << TargetName << "FrameLowering *\n"1843 << TargetName1844 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n"1845 << " return static_cast<const " << TargetName << "FrameLowering *>(\n"1846 << " MF.getSubtarget().getFrameLowering());\n"1847 << "}\n\n";1848 1849 OS << "} // end namespace llvm\n\n";1850}1851 1852TableGenOutputFiles RegisterInfoEmitter::run(StringRef FilenamePrefix) {1853 TGTimer &Timer = Records.getTimer();1854 Timer.startTimer("Print enums");1855 std::string Main;1856 raw_string_ostream MainOS(Main);1857 std::string Enums;1858 raw_string_ostream EnumsOS(Enums);1859 runEnums(EnumsOS, MainOS, FilenamePrefix);1860 1861 Timer.startTimer("Print MC registers");1862 std::string MCDesc;1863 raw_string_ostream MCDescOS(MCDesc);1864 runMCDesc(MCDescOS, MainOS, FilenamePrefix);1865 1866 Timer.startTimer("Print header fragment");1867 std::string Header;1868 raw_string_ostream HeaderOS(Header);1869 runTargetHeader(HeaderOS, MainOS, FilenamePrefix);1870 1871 Timer.startTimer("Print target registers");1872 std::string TargetDesc;1873 raw_string_ostream TargetDescOS(TargetDesc);1874 runTargetDesc(TargetDescOS, MainOS, FilenamePrefix);1875 1876 if (RegisterInfoDebug)1877 debugDump(errs());1878 1879 // The suffixes should be in sync with the tablegen function in1880 // llvm/cmake/modules/TableGen.cmake.1881 return {Main,1882 {{"Enums.inc", Enums},1883 {"MCDesc.inc", MCDesc},1884 {"Header.inc", Header},1885 {"TargetDesc.inc", TargetDesc}}};1886}1887 1888void RegisterInfoEmitter::debugDump(raw_ostream &OS) {1889 const CodeGenHwModes &CGH = Target.getHwModes();1890 unsigned NumModes = CGH.getNumModeIds();1891 auto getModeName = [CGH](unsigned M) -> StringRef {1892 if (M == 0)1893 return "Default";1894 return CGH.getMode(M).Name;1895 };1896 1897 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {1898 OS << "RegisterClass " << RC.getName() << ":\n";1899 OS << "\tSpillSize: {";1900 for (unsigned M = 0; M != NumModes; ++M)1901 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize;1902 OS << " }\n\tSpillAlignment: {";1903 for (unsigned M = 0; M != NumModes; ++M)1904 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment;1905 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n';1906 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';1907 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';1908 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';1909 OS << "\tAllocatable: " << RC.Allocatable << '\n';1910 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n';1911 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n';1912 OS << "\tRegs:";1913 for (const CodeGenRegister *R : RC.getMembers()) {1914 OS << " " << R->getName();1915 }1916 OS << '\n';1917 OS << "\tSubClasses:";1918 const BitVector &SubClasses = RC.getSubClasses();1919 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {1920 if (!SubClasses.test(SRC.EnumValue))1921 continue;1922 OS << " " << SRC.getName();1923 }1924 OS << '\n';1925 OS << "\tSuperClasses:";1926 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) {1927 OS << " " << SRC->getName();1928 }1929 OS << '\n';1930 }1931 1932 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {1933 OS << "SubRegIndex " << SRI.getName() << ":\n";1934 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n';1935 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n';1936 OS << "\tOffset: {";1937 for (unsigned M = 0; M != NumModes; ++M)1938 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset;1939 OS << " }\n\tSize: {";1940 for (unsigned M = 0; M != NumModes; ++M)1941 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size;1942 OS << " }\n";1943 }1944 1945 for (const CodeGenRegister &R : RegBank.getRegisters()) {1946 OS << "Register " << R.getName() << ":\n";1947 OS << "\tCostPerUse: ";1948 for (const auto &Cost : R.CostPerUse)1949 OS << Cost << " ";1950 OS << '\n';1951 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n';1952 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n';1953 for (auto &[SubIdx, SubReg] : R.getSubRegs()) {1954 OS << "\tSubReg " << SubIdx->getName() << " = " << SubReg->getName()1955 << '\n';1956 }1957 for (unsigned U : R.getNativeRegUnits())1958 OS << "\tRegUnit " << U << '\n';1959 }1960}1961 1962static TableGen::Emitter::MultiFileOptClass<RegisterInfoEmitter>1963 X("gen-register-info", "Generate registers and register classes info");1964