2216 lines · cpp
1//===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This tablegen backend emits subtarget enumerations.10//11//===----------------------------------------------------------------------===//12 13#include "Basic/TargetFeaturesEmitter.h"14#include "Common/CodeGenHwModes.h"15#include "Common/CodeGenSchedule.h"16#include "Common/CodeGenTarget.h"17#include "Common/PredicateExpander.h"18#include "Common/SubtargetFeatureInfo.h"19#include "Common/Utils.h"20#include "llvm/ADT/STLExtras.h"21#include "llvm/ADT/SmallPtrSet.h"22#include "llvm/ADT/StringExtras.h"23#include "llvm/ADT/StringMap.h"24#include "llvm/ADT/StringRef.h"25#include "llvm/MC/MCInstrItineraries.h"26#include "llvm/MC/MCSchedule.h"27#include "llvm/Support/Debug.h"28#include "llvm/Support/Format.h"29#include "llvm/Support/raw_ostream.h"30#include "llvm/TableGen/CodeGenHelpers.h"31#include "llvm/TableGen/Error.h"32#include "llvm/TableGen/Record.h"33#include "llvm/TableGen/StringToOffsetTable.h"34#include "llvm/TableGen/TableGenBackend.h"35#include <algorithm>36#include <cassert>37#include <cstdint>38#include <iterator>39#include <string>40#include <vector>41 42using namespace llvm;43 44#define DEBUG_TYPE "subtarget-emitter"45 46namespace {47 48class SubtargetEmitter : TargetFeaturesEmitter {49 // Each processor has a SchedClassDesc table with an entry for each50 // SchedClass. The SchedClassDesc table indexes into a global write resource51 // table, write latency table, and read advance table.52 struct SchedClassTables {53 std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;54 std::vector<MCWriteProcResEntry> WriteProcResources;55 std::vector<MCWriteLatencyEntry> WriteLatencies;56 std::vector<std::string> WriterNames;57 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;58 59 // Reserve an invalid entry at index 060 SchedClassTables() {61 ProcSchedClasses.resize(1);62 WriteProcResources.resize(1);63 WriteLatencies.resize(1);64 WriterNames.push_back("InvalidWrite");65 ReadAdvanceEntries.resize(1);66 }67 };68 69 struct LessWriteProcResources {70 bool operator()(const MCWriteProcResEntry &LHS,71 const MCWriteProcResEntry &RHS) {72 return LHS.ProcResourceIdx < RHS.ProcResourceIdx;73 }74 };75 76 CodeGenTarget TGT;77 CodeGenSchedModels &SchedModels;78 79 FeatureMapTy emitEnums(raw_ostream &OS);80 void emitSubtargetInfoMacroCalls(raw_ostream &OS);81 std::tuple<unsigned, unsigned, unsigned>82 emitMCDesc(raw_ostream &OS, const FeatureMapTy &FeatureMap);83 void emitTargetDesc(raw_ostream &OS);84 void emitHeader(raw_ostream &OS);85 void emitCtor(raw_ostream &OS, unsigned NumNames, unsigned NumFeatures,86 unsigned NumProcs);87 88 unsigned featureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);89 unsigned cpuKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap);90 unsigned cpuNames(raw_ostream &OS);91 void formItineraryStageString(const std::string &Names,92 const Record *ItinData, std::string &ItinString,93 unsigned &NStages);94 void formItineraryOperandCycleString(const Record *ItinData,95 std::string &ItinString,96 unsigned &NOperandCycles);97 void formItineraryBypassString(const std::string &Names,98 const Record *ItinData,99 std::string &ItinString,100 unsigned NOperandCycles);101 void emitStageAndOperandCycleData(102 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists);103 void emitItineraries(raw_ostream &OS,104 ArrayRef<std::vector<InstrItinerary>> ProcItinLists);105 unsigned emitRegisterFileTables(const CodeGenProcModel &ProcModel,106 raw_ostream &OS);107 void emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,108 raw_ostream &OS);109 void emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,110 raw_ostream &OS);111 void emitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,112 char Separator);113 void emitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,114 raw_ostream &OS);115 void emitProcessorResources(const CodeGenProcModel &ProcModel,116 raw_ostream &OS);117 const Record *findWriteResources(const CodeGenSchedRW &SchedWrite,118 const CodeGenProcModel &ProcModel);119 const Record *findReadAdvance(const CodeGenSchedRW &SchedRead,120 const CodeGenProcModel &ProcModel);121 void expandProcResources(ConstRecVec &PRVec,122 std::vector<int64_t> &ReleaseAtCycles,123 std::vector<int64_t> &AcquireAtCycles,124 const CodeGenProcModel &ProcModel);125 void genSchedClassTables(const CodeGenProcModel &ProcModel,126 SchedClassTables &SchedTables);127 void emitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);128 void emitProcessorModels(raw_ostream &OS);129 void emitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);130 void emitSchedModelHelpersImpl(raw_ostream &OS,131 bool OnlyExpandMCInstPredicates = false);132 void emitGenMCSubtargetInfo(raw_ostream &OS);133 void emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS);134 135 void emitSchedModel(raw_ostream &OS);136 void emitGetMacroFusions(const std::string &ClassName, raw_ostream &OS);137 void emitHwModeCheck(const std::string &ClassName, raw_ostream &OS,138 bool IsMC);139 void parseFeaturesFunction(raw_ostream &OS);140 141public:142 SubtargetEmitter(const RecordKeeper &R)143 : TargetFeaturesEmitter(R), TGT(R), SchedModels(TGT.getSchedModels()) {}144 145 void run(raw_ostream &O) override;146};147 148} // end anonymous namespace149 150/// Emit some information about the SubtargetFeature as calls to a macro so151/// that they can be used from C++.152void SubtargetEmitter::emitSubtargetInfoMacroCalls(raw_ostream &OS) {153 // Undef the GET_SUBTARGETINFO_MACRO macro at the end of the scope since it's154 // used within the scope.155 IfDefEmitter IfDefMacro(OS, "GET_SUBTARGETINFO_MACRO", /*LateUndef=*/true);156 157 std::vector<const Record *> FeatureList =158 Records.getAllDerivedDefinitions("SubtargetFeature");159 llvm::sort(FeatureList, LessRecordFieldFieldName());160 161 for (const Record *Feature : FeatureList) {162 const StringRef FieldName = Feature->getValueAsString("FieldName");163 const StringRef Value = Feature->getValueAsString("Value");164 165 // Only handle boolean features for now, excluding BitVectors and enums.166 const bool IsBool = (Value == "false" || Value == "true") &&167 !StringRef(FieldName).contains('[');168 if (!IsBool)169 continue;170 171 // Some features default to true, with values set to false if enabled.172 const char *Default = Value == "false" ? "true" : "false";173 174 // Define the getter with lowercased first char: xxxYyy() { return XxxYyy; }175 const std::string Getter =176 FieldName.substr(0, 1).lower() + FieldName.substr(1).str();177 178 OS << "GET_SUBTARGETINFO_MACRO(" << FieldName << ", " << Default << ", "179 << Getter << ")\n";180 }181}182 183//184// FeatureKeyValues - Emit data of all the subtarget features. Used by the185// command line.186//187unsigned SubtargetEmitter::featureKeyValues(raw_ostream &OS,188 const FeatureMapTy &FeatureMap) {189 std::vector<const Record *> FeatureList =190 Records.getAllDerivedDefinitions("SubtargetFeature");191 192 // Remove features with empty name.193 llvm::erase_if(FeatureList, [](const Record *Rec) {194 return Rec->getValueAsString("Name").empty();195 });196 if (FeatureList.empty())197 return 0;198 199 // Sort and check duplicate Feature name.200 sortAndReportDuplicates(FeatureList, "Feature");201 202 // Begin feature table.203 OS << "// Sorted (by key) array of values for CPU features.\n"204 << "extern const llvm::SubtargetFeatureKV " << Target205 << "FeatureKV[] = {\n";206 207 for (const Record *Feature : FeatureList) {208 // Next feature209 StringRef Name = Feature->getName();210 StringRef CommandLineName = Feature->getValueAsString("Name");211 StringRef Desc = Feature->getValueAsString("Desc");212 213 // Emit as { "feature", "description", { featureEnum }, { i1 , i2 , ... , in214 // } }215 OS << " { "216 << "\"" << CommandLineName << "\", "217 << "\"" << Desc << "\", " << Target << "::" << Name << ", ";218 219 ConstRecVec ImpliesList = Feature->getValueAsListOfDefs("Implies");220 221 printFeatureMask(OS, ImpliesList, FeatureMap);222 223 OS << " },\n";224 }225 226 // End feature table.227 OS << "};\n";228 229 return FeatureList.size();230}231 232unsigned SubtargetEmitter::cpuNames(raw_ostream &OS) {233 // Begin processor name table.234 OS << "// Sorted array of names of CPU subtypes, including aliases.\n"235 << "extern const llvm::StringRef " << Target << "Names[] = {\n";236 237 std::vector<const Record *> ProcessorList =238 Records.getAllDerivedDefinitions("Processor");239 240 std::vector<const Record *> ProcessorAliasList =241 Records.getAllDerivedDefinitionsIfDefined("ProcessorAlias");242 243 SmallVector<StringRef> Names;244 Names.reserve(ProcessorList.size() + ProcessorAliasList.size());245 246 for (const Record *Processor : ProcessorList) {247 StringRef Name = Processor->getValueAsString("Name");248 Names.push_back(Name);249 }250 251 for (const Record *Rec : ProcessorAliasList) {252 auto Name = Rec->getValueAsString("Name");253 Names.push_back(Name);254 }255 256 llvm::sort(Names);257 llvm::interleave(258 Names, OS, [&](StringRef Name) { OS << '"' << Name << '"'; }, ",\n");259 260 // End processor name table.261 OS << "};\n";262 263 return Names.size();264}265 266static void checkDuplicateCPUFeatures(StringRef CPUName,267 ArrayRef<const Record *> Features,268 ArrayRef<const Record *> TuneFeatures) {269 // We have made sure each SubtargetFeature Record has a unique name, so we can270 // simply use pointer sets here.271 SmallPtrSet<const Record *, 8> FeatureSet, TuneFeatureSet;272 for (const auto *FeatureRec : Features) {273 if (!FeatureSet.insert(FeatureRec).second)274 PrintWarning("Processor " + CPUName + " contains duplicate feature '" +275 FeatureRec->getValueAsString("Name") + "'");276 }277 278 for (const auto *TuneFeatureRec : TuneFeatures) {279 if (!TuneFeatureSet.insert(TuneFeatureRec).second)280 PrintWarning("Processor " + CPUName +281 " contains duplicate tune feature '" +282 TuneFeatureRec->getValueAsString("Name") + "'");283 if (FeatureSet.contains(TuneFeatureRec))284 PrintWarning("Processor " + CPUName + " has '" +285 TuneFeatureRec->getValueAsString("Name") +286 "' in both feature and tune feature sets");287 }288}289 290//291// CPUKeyValues - Emit data of all the subtarget processors. Used by command292// line.293//294unsigned SubtargetEmitter::cpuKeyValues(raw_ostream &OS,295 const FeatureMapTy &FeatureMap) {296 // Gather and sort processor information297 std::vector<const Record *> ProcessorList =298 Records.getAllDerivedDefinitions("Processor");299 llvm::sort(ProcessorList, LessRecordFieldName());300 301 // Note that unlike `FeatureKeyValues`, here we do not need to check for302 // duplicate processors, since that is already done when the SubtargetEmitter303 // constructor calls `getSchedModels` to build a `CodeGenSchedModels` object,304 // which does the duplicate processor check.305 306 // Begin processor table.307 OS << "// Sorted (by key) array of values for CPU subtype.\n"308 << "extern const llvm::SubtargetSubTypeKV " << Target309 << "SubTypeKV[] = {\n";310 311 for (const Record *Processor : ProcessorList) {312 StringRef Name = Processor->getValueAsString("Name");313 ConstRecVec FeatureList = Processor->getValueAsListOfDefs("Features");314 ConstRecVec TuneFeatureList =315 Processor->getValueAsListOfDefs("TuneFeatures");316 317 // Warn the user if there are duplicate processor features or tune318 // features.319 checkDuplicateCPUFeatures(Name, FeatureList, TuneFeatureList);320 321 // Emit as "{ "cpu", "description", 0, { f1 , f2 , ... fn } },".322 OS << " { "323 << "\"" << Name << "\", ";324 325 printFeatureMask(OS, FeatureList, FeatureMap);326 OS << ", ";327 printFeatureMask(OS, TuneFeatureList, FeatureMap);328 329 // Emit the scheduler model pointer.330 const std::string &ProcModelName =331 SchedModels.getModelForProc(Processor).ModelName;332 OS << ", &" << ProcModelName << " },\n";333 }334 335 // End processor table.336 OS << "};\n";337 338 return ProcessorList.size();339}340 341//342// FormItineraryStageString - Compose a string containing the stage343// data initialization for the specified itinerary. N is the number344// of stages.345//346void SubtargetEmitter::formItineraryStageString(const std::string &Name,347 const Record *ItinData,348 std::string &ItinString,349 unsigned &NStages) {350 // Get states list351 ConstRecVec StageList = ItinData->getValueAsListOfDefs("Stages");352 353 // For each stage354 unsigned N = NStages = StageList.size();355 for (unsigned I = 0; I < N;) {356 // Next stage357 const Record *Stage = StageList[I];358 359 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }360 int Cycles = Stage->getValueAsInt("Cycles");361 ItinString += " { " + itostr(Cycles) + ", ";362 363 // Get unit list364 ConstRecVec UnitList = Stage->getValueAsListOfDefs("Units");365 366 // For each unit367 for (unsigned J = 0, M = UnitList.size(); J < M;) {368 // Add name and bitwise or369 ItinString += Name + "FU::" + UnitList[J]->getName().str();370 if (++J < M)371 ItinString += " | ";372 }373 374 int TimeInc = Stage->getValueAsInt("TimeInc");375 ItinString += ", " + itostr(TimeInc);376 377 int Kind = Stage->getValueAsInt("Kind");378 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);379 380 // Close off stage381 ItinString += " }";382 if (++I < N)383 ItinString += ", ";384 }385}386 387//388// FormItineraryOperandCycleString - Compose a string containing the389// operand cycle initialization for the specified itinerary. N is the390// number of operands that has cycles specified.391//392void SubtargetEmitter::formItineraryOperandCycleString(393 const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) {394 // Get operand cycle list395 std::vector<int64_t> OperandCycleList =396 ItinData->getValueAsListOfInts("OperandCycles");397 398 // For each operand cycle399 NOperandCycles = OperandCycleList.size();400 ListSeparator LS;401 for (int OCycle : OperandCycleList) {402 // Next operand cycle403 ItinString += LS;404 ItinString += " " + itostr(OCycle);405 }406}407 408void SubtargetEmitter::formItineraryBypassString(const std::string &Name,409 const Record *ItinData,410 std::string &ItinString,411 unsigned NOperandCycles) {412 ConstRecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses");413 unsigned N = BypassList.size();414 unsigned I = 0;415 ListSeparator LS;416 for (; I < N; ++I) {417 ItinString += LS;418 ItinString += Name + "Bypass::" + BypassList[I]->getName().str();419 }420 for (; I < NOperandCycles; ++I) {421 ItinString += LS;422 ItinString += " 0";423 }424}425 426//427// EmitStageAndOperandCycleData - Generate unique itinerary stages and operand428// cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed429// by CodeGenSchedClass::Index.430//431void SubtargetEmitter::emitStageAndOperandCycleData(432 raw_ostream &OS, std::vector<std::vector<InstrItinerary>> &ProcItinLists) {433 // Multiple processor models may share an itinerary record. Emit it once.434 SmallPtrSet<const Record *, 8> ItinsDefSet;435 436 // Emit functional units for all the itineraries.437 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {438 if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)439 continue;440 441 ConstRecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");442 if (FUs.empty())443 continue;444 445 StringRef Name = ProcModel.ItinsDef->getName();446 {447 OS << "\n// Functional units for \"" << Name << "\"\n";448 NamespaceEmitter FUNamespace(OS, (Name + Twine("FU")).str());449 450 for (const auto &[Idx, FU] : enumerate(FUs))451 OS << " const InstrStage::FuncUnits " << FU->getName() << " = 1ULL << "452 << Idx << ";\n";453 }454 455 ConstRecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");456 if (BPs.empty())457 continue;458 OS << "\n// Pipeline forwarding paths for itineraries \"" << Name << "\"\n";459 NamespaceEmitter BypassNamespace(OS, (Name + Twine("Bypass")).str());460 461 OS << " const unsigned NoBypass = 0;\n";462 for (const auto &[Idx, BP] : enumerate(BPs))463 OS << " const unsigned " << BP->getName() << " = 1 << " << Idx << ";\n";464 }465 466 // Begin stages table467 std::string StageTable =468 "\nextern const llvm::InstrStage " + Target + "Stages[] = {\n";469 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";470 471 // Begin operand cycle table472 std::string OperandCycleTable =473 "extern const unsigned " + Target + "OperandCycles[] = {\n";474 OperandCycleTable += " 0, // No itinerary\n";475 476 // Begin pipeline bypass table477 std::string BypassTable =478 "extern const unsigned " + Target + "ForwardingPaths[] = {\n";479 BypassTable += " 0, // No itinerary\n";480 481 // For each Itinerary across all processors, add a unique entry to the stages,482 // operand cycles, and pipeline bypass tables. Then add the new Itinerary483 // object with computed offsets to the ProcItinLists result.484 unsigned StageCount = 1, OperandCycleCount = 1;485 StringMap<unsigned> ItinStageMap, ItinOperandMap;486 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {487 // Add process itinerary to the list.488 std::vector<InstrItinerary> &ItinList = ProcItinLists.emplace_back();489 490 // If this processor defines no itineraries, then leave the itinerary list491 // empty.492 if (!ProcModel.hasItineraries())493 continue;494 495 StringRef Name = ProcModel.ItinsDef->getName();496 497 ItinList.resize(SchedModels.numInstrSchedClasses());498 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");499 500 for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size();501 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {502 503 // Next itinerary data504 const Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];505 506 // Get string and stage count507 std::string ItinStageString;508 unsigned NStages = 0;509 if (ItinData)510 formItineraryStageString(Name.str(), ItinData, ItinStageString,511 NStages);512 513 // Get string and operand cycle count514 std::string ItinOperandCycleString;515 unsigned NOperandCycles = 0;516 std::string ItinBypassString;517 if (ItinData) {518 formItineraryOperandCycleString(ItinData, ItinOperandCycleString,519 NOperandCycles);520 521 formItineraryBypassString(Name.str(), ItinData, ItinBypassString,522 NOperandCycles);523 }524 525 // Check to see if stage already exists and create if it doesn't526 uint16_t FindStage = 0;527 if (NStages > 0) {528 FindStage = ItinStageMap[ItinStageString];529 if (FindStage == 0) {530 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices531 StageTable += ItinStageString + ", // " + itostr(StageCount);532 if (NStages > 1)533 StageTable += "-" + itostr(StageCount + NStages - 1);534 StageTable += "\n";535 // Record Itin class number.536 ItinStageMap[ItinStageString] = FindStage = StageCount;537 StageCount += NStages;538 }539 }540 541 // Check to see if operand cycle already exists and create if it doesn't542 uint16_t FindOperandCycle = 0;543 if (NOperandCycles > 0) {544 std::string ItinOperandString =545 ItinOperandCycleString + ItinBypassString;546 FindOperandCycle = ItinOperandMap[ItinOperandString];547 if (FindOperandCycle == 0) {548 // Emit as cycle, // index549 OperandCycleTable += ItinOperandCycleString + ", // ";550 std::string OperandIdxComment = itostr(OperandCycleCount);551 if (NOperandCycles > 1)552 OperandIdxComment +=553 "-" + itostr(OperandCycleCount + NOperandCycles - 1);554 OperandCycleTable += OperandIdxComment + "\n";555 // Record Itin class number.556 ItinOperandMap[ItinOperandCycleString] = FindOperandCycle =557 OperandCycleCount;558 // Emit as bypass, // index559 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";560 OperandCycleCount += NOperandCycles;561 }562 }563 564 // Set up itinerary as location and location + stage count565 int16_t NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;566 InstrItinerary Intinerary = {567 NumUOps,568 FindStage,569 uint16_t(FindStage + NStages),570 FindOperandCycle,571 uint16_t(FindOperandCycle + NOperandCycles),572 };573 574 // Inject - empty slots will be 0, 0575 ItinList[SchedClassIdx] = Intinerary;576 }577 }578 579 // Closing stage580 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";581 StageTable += "};\n";582 583 // Closing operand cycles584 OperandCycleTable += " 0 // End operand cycles\n";585 OperandCycleTable += "};\n";586 587 BypassTable += " 0 // End bypass tables\n";588 BypassTable += "};\n";589 590 // Emit tables.591 OS << StageTable;592 OS << OperandCycleTable;593 OS << BypassTable;594}595 596//597// EmitProcessorData - Generate data for processor itineraries that were598// computed during EmitStageAndOperandCycleData(). ProcItinLists lists all599// Itineraries for each processor. The Itinerary lists are indexed on600// CodeGenSchedClass::Index.601//602void SubtargetEmitter::emitItineraries(603 raw_ostream &OS, ArrayRef<std::vector<InstrItinerary>> ProcItinLists) {604 // Multiple processor models may share an itinerary record. Emit it once.605 SmallPtrSet<const Record *, 8> ItinsDefSet;606 607 for (const auto &[Proc, ItinList] :608 zip_equal(SchedModels.procModels(), ProcItinLists)) {609 const Record *ItinsDef = Proc.ItinsDef;610 if (!ItinsDefSet.insert(ItinsDef).second)611 continue;612 613 // Empty itineraries aren't referenced anywhere in the tablegen output614 // so don't emit them.615 if (ItinList.empty())616 continue;617 618 // Begin processor itinerary table619 OS << "\n";620 OS << "static constexpr llvm::InstrItinerary " << ItinsDef->getName()621 << "[] = {\n";622 623 ArrayRef<CodeGenSchedClass> ItinSchedClasses =624 SchedModels.schedClasses().take_front(ItinList.size());625 626 // For each itinerary class in CodeGenSchedClass::Index order.627 for (const auto &[Idx, Intinerary, SchedClass] :628 enumerate(ItinList, ItinSchedClasses)) {629 // Emit Itinerary in the form of630 // { NumMicroOps, FirstStage, LastStage, FirstOperandCycle,631 // LastOperandCycle } // index class name632 OS << " { " << Intinerary.NumMicroOps << ", " << Intinerary.FirstStage633 << ", " << Intinerary.LastStage << ", " << Intinerary.FirstOperandCycle634 << ", " << Intinerary.LastOperandCycle << " }" << ", // " << Idx << " "635 << SchedClass.Name << "\n";636 }637 // End processor itinerary table638 OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"639 "// end marker\n";640 OS << "};\n";641 }642}643 644// Emit either the value defined in the TableGen Record, or the default645// value defined in the C++ header. The Record is null if the processor does not646// define a model.647void SubtargetEmitter::emitProcessorProp(raw_ostream &OS, const Record *R,648 StringRef Name, char Separator) {649 OS << " ";650 int V = R ? R->getValueAsInt(Name) : -1;651 if (V >= 0)652 OS << V << Separator << " // " << Name;653 else654 OS << "MCSchedModel::Default" << Name << Separator;655 OS << '\n';656}657 658void SubtargetEmitter::emitProcessorResourceSubUnits(659 const CodeGenProcModel &ProcModel, raw_ostream &OS) {660 OS << "\nstatic const unsigned " << ProcModel.ModelName661 << "ProcResourceSubUnits[] = {\n"662 << " 0, // Invalid\n";663 664 for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {665 const Record *PRDef = ProcModel.ProcResourceDefs[I];666 if (!PRDef->isSubClassOf("ProcResGroup"))667 continue;668 for (const Record *RUDef : PRDef->getValueAsListOfDefs("Resources")) {669 const Record *RU =670 SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc());671 for (unsigned J = 0; J < RU->getValueAsInt("NumUnits"); ++J) {672 OS << " " << ProcModel.getProcResourceIdx(RU) << ", ";673 }674 }675 OS << " // " << PRDef->getName() << "\n";676 }677 OS << "};\n";678}679 680static void emitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,681 raw_ostream &OS) {682 int64_t ReorderBufferSize = 0, MaxRetirePerCycle = 0;683 if (const Record *RCU = ProcModel.RetireControlUnit) {684 ReorderBufferSize =685 std::max(ReorderBufferSize, RCU->getValueAsInt("ReorderBufferSize"));686 MaxRetirePerCycle =687 std::max(MaxRetirePerCycle, RCU->getValueAsInt("MaxRetirePerCycle"));688 }689 690 OS << ReorderBufferSize << ", // ReorderBufferSize\n ";691 OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n ";692}693 694static void emitRegisterFileInfo(const CodeGenProcModel &ProcModel,695 unsigned NumRegisterFiles,696 unsigned NumCostEntries, raw_ostream &OS) {697 if (NumRegisterFiles)698 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles);699 else700 OS << "nullptr,\n 0";701 702 OS << ", // Number of register files.\n ";703 if (NumCostEntries)704 OS << ProcModel.ModelName << "RegisterCosts,\n ";705 else706 OS << "nullptr,\n ";707 OS << NumCostEntries << ", // Number of register cost entries.\n";708}709 710unsigned711SubtargetEmitter::emitRegisterFileTables(const CodeGenProcModel &ProcModel,712 raw_ostream &OS) {713 if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) {714 return RF.hasDefaultCosts();715 }))716 return 0;717 718 // Print the RegisterCost table first.719 OS << "\n// {RegisterClassID, Register Cost, AllowMoveElimination }\n";720 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName721 << "RegisterCosts"722 << "[] = {\n";723 724 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {725 // Skip register files with a default cost table.726 if (RF.hasDefaultCosts())727 continue;728 // Add entries to the cost table.729 for (const CodeGenRegisterCost &RC : RF.Costs) {730 OS << " { ";731 const Record *Rec = RC.RCDef;732 if (Rec->getValue("Namespace"))733 OS << Rec->getValueAsString("Namespace") << "::";734 OS << Rec->getName() << "RegClassID, " << RC.Cost << ", "735 << RC.AllowMoveElimination << "},\n";736 }737 }738 OS << "};\n";739 740 // Now generate a table with register file info.741 OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl, "742 << "MaxMovesEliminatedPerCycle, AllowZeroMoveEliminationOnly }\n";743 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName744 << "RegisterFiles"745 << "[] = {\n"746 << " { \"InvalidRegisterFile\", 0, 0, 0, 0, 0 },\n";747 unsigned CostTblIndex = 0;748 749 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {750 OS << " { ";751 OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", ";752 unsigned NumCostEntries = RD.Costs.size();753 OS << NumCostEntries << ", " << CostTblIndex << ", "754 << RD.MaxMovesEliminatedPerCycle << ", "755 << RD.AllowZeroMoveEliminationOnly << "},\n";756 CostTblIndex += NumCostEntries;757 }758 OS << "};\n";759 760 return CostTblIndex;761}762 763void SubtargetEmitter::emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,764 raw_ostream &OS) {765 unsigned QueueID = 0;766 if (ProcModel.LoadQueue) {767 const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor");768 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),769 find(ProcModel.ProcResourceDefs, Queue));770 }771 OS << " " << QueueID << ", // Resource Descriptor for the Load Queue\n";772 773 QueueID = 0;774 if (ProcModel.StoreQueue) {775 const Record *Queue =776 ProcModel.StoreQueue->getValueAsDef("QueueDescriptor");777 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),778 find(ProcModel.ProcResourceDefs, Queue));779 }780 OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n";781}782 783void SubtargetEmitter::emitExtraProcessorInfo(const CodeGenProcModel &ProcModel,784 raw_ostream &OS) {785 // Generate a table of register file descriptors (one entry per each user786 // defined register file), and a table of register costs.787 unsigned NumCostEntries = emitRegisterFileTables(ProcModel, OS);788 789 // Now generate a table for the extra processor info.790 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName791 << "ExtraInfo = {\n ";792 793 // Add information related to the retire control unit.794 emitRetireControlUnitInfo(ProcModel, OS);795 796 // Add information related to the register files (i.e. where to find register797 // file descriptors and register costs).798 emitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(),799 NumCostEntries, OS);800 801 // Add information about load/store queues.802 emitLoadStoreQueueInfo(ProcModel, OS);803 804 OS << "};\n";805}806 807void SubtargetEmitter::emitProcessorResources(const CodeGenProcModel &ProcModel,808 raw_ostream &OS) {809 emitProcessorResourceSubUnits(ProcModel, OS);810 811 OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n";812 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName813 << "ProcResources"814 << "[] = {\n"815 << " {\"InvalidUnit\", 0, 0, 0, 0},\n";816 817 unsigned SubUnitsOffset = 1;818 for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) {819 const Record *PRDef = ProcModel.ProcResourceDefs[I];820 821 const Record *SuperDef = nullptr;822 unsigned SuperIdx = 0;823 unsigned NumUnits = 0;824 const unsigned SubUnitsBeginOffset = SubUnitsOffset;825 int BufferSize = PRDef->getValueAsInt("BufferSize");826 if (PRDef->isSubClassOf("ProcResGroup")) {827 for (const Record *RU : PRDef->getValueAsListOfDefs("Resources")) {828 NumUnits += RU->getValueAsInt("NumUnits");829 SubUnitsOffset += RU->getValueAsInt("NumUnits");830 }831 } else {832 // Find the SuperIdx833 if (PRDef->getValueInit("Super")->isComplete()) {834 SuperDef = SchedModels.findProcResUnits(PRDef->getValueAsDef("Super"),835 ProcModel, PRDef->getLoc());836 SuperIdx = ProcModel.getProcResourceIdx(SuperDef);837 }838 NumUnits = PRDef->getValueAsInt("NumUnits");839 }840 // Emit the ProcResourceDesc841 OS << " {\"" << PRDef->getName() << "\", ";842 if (PRDef->getName().size() < 15)843 OS.indent(15 - PRDef->getName().size());844 OS << NumUnits << ", " << SuperIdx << ", " << BufferSize << ", ";845 if (SubUnitsBeginOffset != SubUnitsOffset) {846 OS << ProcModel.ModelName << "ProcResourceSubUnits + "847 << SubUnitsBeginOffset;848 } else {849 OS << "nullptr";850 }851 OS << "}, // #" << I + 1;852 if (SuperDef)853 OS << ", Super=" << SuperDef->getName();854 OS << "\n";855 }856 OS << "};\n";857}858 859// Find the WriteRes Record that defines processor resources for this860// SchedWrite.861const Record *862SubtargetEmitter::findWriteResources(const CodeGenSchedRW &SchedWrite,863 const CodeGenProcModel &ProcModel) {864 865 // Check if the SchedWrite is already subtarget-specific and directly866 // specifies a set of processor resources.867 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))868 return SchedWrite.TheDef;869 870 const Record *AliasDef = nullptr;871 for (const Record *A : SchedWrite.Aliases) {872 const CodeGenSchedRW &AliasRW =873 SchedModels.getSchedRW(A->getValueAsDef("AliasRW"));874 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {875 const Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");876 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)877 continue;878 }879 if (AliasDef)880 PrintFatalError(AliasRW.TheDef->getLoc(),881 "Multiple aliases "882 "defined for processor " +883 ProcModel.ModelName +884 " Ensure only one SchedAlias exists per RW.");885 AliasDef = AliasRW.TheDef;886 }887 if (AliasDef && AliasDef->isSubClassOf("SchedWriteRes"))888 return AliasDef;889 890 // Check this processor's list of write resources.891 const Record *ResDef = nullptr;892 893 auto I = ProcModel.WriteResMap.find(SchedWrite.TheDef);894 if (I != ProcModel.WriteResMap.end())895 ResDef = I->second;896 897 if (AliasDef) {898 I = ProcModel.WriteResMap.find(AliasDef);899 if (I != ProcModel.WriteResMap.end()) {900 if (ResDef)901 PrintFatalError(I->second->getLoc(),902 "Resources are defined for both SchedWrite and its "903 "alias on processor " +904 ProcModel.ModelName);905 ResDef = I->second;906 }907 }908 909 // TODO: If ProcModel has a base model (previous generation processor),910 // then call FindWriteResources recursively with that model here.911 if (!ResDef) {912 PrintFatalError(ProcModel.ModelDef->getLoc(),913 Twine("Processor does not define resources for ") +914 SchedWrite.TheDef->getName());915 }916 return ResDef;917}918 919/// Find the ReadAdvance record for the given SchedRead on this processor or920/// return NULL.921const Record *922SubtargetEmitter::findReadAdvance(const CodeGenSchedRW &SchedRead,923 const CodeGenProcModel &ProcModel) {924 // Check for SchedReads that directly specify a ReadAdvance.925 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))926 return SchedRead.TheDef;927 928 // Check this processor's list of aliases for SchedRead.929 const Record *AliasDef = nullptr;930 for (const Record *A : SchedRead.Aliases) {931 const CodeGenSchedRW &AliasRW =932 SchedModels.getSchedRW(A->getValueAsDef("AliasRW"));933 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {934 const Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");935 if (&SchedModels.getProcModel(ModelDef) != &ProcModel)936 continue;937 }938 if (AliasDef)939 PrintFatalError(AliasRW.TheDef->getLoc(),940 "Multiple aliases "941 "defined for processor " +942 ProcModel.ModelName +943 " Ensure only one SchedAlias exists per RW.");944 AliasDef = AliasRW.TheDef;945 }946 if (AliasDef && AliasDef->isSubClassOf("SchedReadAdvance"))947 return AliasDef;948 949 // Check this processor's ReadAdvanceList.950 const Record *ResDef = nullptr;951 952 auto I = ProcModel.ReadAdvanceMap.find(SchedRead.TheDef);953 if (I != ProcModel.ReadAdvanceMap.end())954 ResDef = I->second;955 956 if (AliasDef) {957 I = ProcModel.ReadAdvanceMap.find(AliasDef);958 if (I != ProcModel.ReadAdvanceMap.end()) {959 if (ResDef)960 PrintFatalError(961 I->second->getLoc(),962 "Resources are defined for both SchedRead and its alias on "963 "processor " +964 ProcModel.ModelName);965 ResDef = I->second;966 }967 }968 969 // TODO: If ProcModel has a base model (previous generation processor),970 // then call FindReadAdvance recursively with that model here.971 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {972 PrintFatalError(ProcModel.ModelDef->getLoc(),973 Twine("Processor does not define resources for ") +974 SchedRead.TheDef->getName());975 }976 return ResDef;977}978 979// Expand an explicit list of processor resources into a full list of implied980// resource groups and super resources that cover them.981void SubtargetEmitter::expandProcResources(982 ConstRecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,983 std::vector<int64_t> &AcquireAtCycles, const CodeGenProcModel &PM) {984 assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition");985 for (unsigned I = 0, E = PRVec.size(); I != E; ++I) {986 const Record *PRDef = PRVec[I];987 ConstRecVec SubResources;988 if (PRDef->isSubClassOf("ProcResGroup")) {989 SubResources = PRDef->getValueAsListOfDefs("Resources");990 } else {991 SubResources.push_back(PRDef);992 PRDef = SchedModels.findProcResUnits(PRDef, PM, PRDef->getLoc());993 for (const Record *SubDef = PRDef;994 SubDef->getValueInit("Super")->isComplete();) {995 if (SubDef->isSubClassOf("ProcResGroup")) {996 // Disallow this for simplicitly.997 PrintFatalError(SubDef->getLoc(), "Processor resource group "998 " cannot be a super resources.");999 }1000 const Record *SuperDef = SchedModels.findProcResUnits(1001 SubDef->getValueAsDef("Super"), PM, SubDef->getLoc());1002 PRVec.push_back(SuperDef);1003 ReleaseAtCycles.push_back(ReleaseAtCycles[I]);1004 AcquireAtCycles.push_back(AcquireAtCycles[I]);1005 SubDef = SuperDef;1006 }1007 }1008 for (const Record *PR : PM.ProcResourceDefs) {1009 if (PR == PRDef || !PR->isSubClassOf("ProcResGroup"))1010 continue;1011 ConstRecVec SuperResources = PR->getValueAsListOfDefs("Resources");1012 bool AllContained =1013 all_of(SubResources, [SuperResources](const Record *SubResource) {1014 return is_contained(SuperResources, SubResource);1015 });1016 if (AllContained) {1017 PRVec.push_back(PR);1018 ReleaseAtCycles.push_back(ReleaseAtCycles[I]);1019 AcquireAtCycles.push_back(AcquireAtCycles[I]);1020 }1021 }1022 }1023}1024 1025// Generate the SchedClass table for this processor and update global1026// tables. Must be called for each processor in order.1027void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel,1028 SchedClassTables &SchedTables) {1029 std::vector<MCSchedClassDesc> &SCTab =1030 SchedTables.ProcSchedClasses.emplace_back();1031 if (!ProcModel.hasInstrSchedModel())1032 return;1033 1034 LLVM_DEBUG(dbgs() << "\n+++ SCHED CLASSES (GenSchedClassTables) +++\n");1035 for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {1036 LLVM_DEBUG(SC.dump(&SchedModels));1037 1038 MCSchedClassDesc &SCDesc = SCTab.emplace_back();1039 // SCDesc.Name is guarded by NDEBUG1040 SCDesc.NumMicroOps = 0;1041 SCDesc.BeginGroup = false;1042 SCDesc.EndGroup = false;1043 SCDesc.RetireOOO = false;1044 SCDesc.WriteProcResIdx = 0;1045 SCDesc.WriteLatencyIdx = 0;1046 SCDesc.ReadAdvanceIdx = 0;1047 1048 // A Variant SchedClass has no resources of its own.1049 bool HasVariants = false;1050 for (const CodeGenSchedTransition &CGT : SC.Transitions) {1051 if (CGT.ProcIndex == ProcModel.Index) {1052 HasVariants = true;1053 break;1054 }1055 }1056 if (HasVariants) {1057 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;1058 continue;1059 }1060 1061 // Determine if the SchedClass is actually reachable on this processor. If1062 // not don't try to locate the processor resources, it will fail.1063 // If ProcIndices contains 0, this class applies to all processors.1064 assert(!SC.ProcIndices.empty() && "expect at least one procidx");1065 if (SC.ProcIndices[0] != 0) {1066 if (!is_contained(SC.ProcIndices, ProcModel.Index))1067 continue;1068 }1069 IdxVec Writes = SC.Writes;1070 IdxVec Reads = SC.Reads;1071 if (!SC.InstRWs.empty()) {1072 // This class has a default ReadWrite list which can be overridden by1073 // InstRW definitions.1074 const Record *RWDef = nullptr;1075 for (const Record *RW : SC.InstRWs) {1076 const Record *RWModelDef = RW->getValueAsDef("SchedModel");1077 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {1078 RWDef = RW;1079 break;1080 }1081 }1082 if (RWDef) {1083 Writes.clear();1084 Reads.clear();1085 SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),1086 Writes, Reads);1087 }1088 }1089 if (Writes.empty()) {1090 // Check this processor's itinerary class resources.1091 for (const Record *I : ProcModel.ItinRWDefs) {1092 ConstRecVec Matched = I->getValueAsListOfDefs("MatchedItinClasses");1093 if (is_contained(Matched, SC.ItinClassDef)) {1094 SchedModels.findRWs(I->getValueAsListOfDefs("OperandReadWrites"),1095 Writes, Reads);1096 break;1097 }1098 }1099 if (Writes.empty()) {1100 LLVM_DEBUG(dbgs() << ProcModel.ModelName1101 << " does not have resources for class " << SC.Name1102 << '\n');1103 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;1104 }1105 }1106 // Sum resources across all operand writes.1107 std::vector<MCWriteProcResEntry> WriteProcResources;1108 std::vector<MCWriteLatencyEntry> WriteLatencies;1109 std::vector<std::string> WriterNames;1110 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;1111 for (unsigned W : Writes) {1112 IdxVec WriteSeq;1113 SchedModels.expandRWSeqForProc(W, WriteSeq, /*IsRead=*/false, ProcModel);1114 1115 // For each operand, create a latency entry.1116 MCWriteLatencyEntry WLEntry;1117 WLEntry.Cycles = 0;1118 unsigned WriteID = WriteSeq.back();1119 WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);1120 // If this Write is not referenced by a ReadAdvance, don't distinguish it1121 // from other WriteLatency entries.1122 if (!ProcModel.hasReadOfWrite(SchedModels.getSchedWrite(WriteID).TheDef))1123 WriteID = 0;1124 WLEntry.WriteResourceID = WriteID;1125 1126 for (unsigned WS : WriteSeq) {1127 const Record *WriteRes =1128 findWriteResources(SchedModels.getSchedWrite(WS), ProcModel);1129 1130 // Mark the parent class as invalid for unsupported write types.1131 if (WriteRes->getValueAsBit("Unsupported")) {1132 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;1133 break;1134 }1135 WLEntry.Cycles += WriteRes->getValueAsInt("Latency");1136 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps");1137 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup");1138 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");1139 SCDesc.BeginGroup |= WriteRes->getValueAsBit("SingleIssue");1140 SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue");1141 SCDesc.RetireOOO |= WriteRes->getValueAsBit("RetireOOO");1142 1143 // Create an entry for each ProcResource listed in WriteRes.1144 ConstRecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");1145 std::vector<int64_t> ReleaseAtCycles =1146 WriteRes->getValueAsListOfInts("ReleaseAtCycles");1147 1148 std::vector<int64_t> AcquireAtCycles =1149 WriteRes->getValueAsListOfInts("AcquireAtCycles");1150 1151 // Check consistency of the two vectors carrying the start and1152 // stop cycles of the resources.1153 if (!ReleaseAtCycles.empty() &&1154 ReleaseAtCycles.size() != PRVec.size()) {1155 // If ReleaseAtCycles is provided, check consistency.1156 PrintFatalError(1157 WriteRes->getLoc(),1158 Twine("Inconsistent release at cycles: size(ReleaseAtCycles) != "1159 "size(ProcResources): ")1160 .concat(Twine(PRVec.size()))1161 .concat(" vs ")1162 .concat(Twine(ReleaseAtCycles.size())));1163 }1164 1165 if (!AcquireAtCycles.empty() &&1166 AcquireAtCycles.size() != PRVec.size()) {1167 PrintFatalError(1168 WriteRes->getLoc(),1169 Twine("Inconsistent resource cycles: size(AcquireAtCycles) != "1170 "size(ProcResources): ")1171 .concat(Twine(AcquireAtCycles.size()))1172 .concat(" vs ")1173 .concat(Twine(PRVec.size())));1174 }1175 1176 if (ReleaseAtCycles.empty()) {1177 // If ReleaseAtCycles is not provided, default to one cycle1178 // per resource.1179 ReleaseAtCycles.resize(PRVec.size(), 1);1180 }1181 1182 if (AcquireAtCycles.empty()) {1183 // If AcquireAtCycles is not provided, reserve the resource1184 // starting from cycle 0.1185 AcquireAtCycles.resize(PRVec.size(), 0);1186 }1187 1188 assert(AcquireAtCycles.size() == ReleaseAtCycles.size());1189 1190 expandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);1191 assert(AcquireAtCycles.size() == ReleaseAtCycles.size());1192 1193 for (unsigned PRIdx = 0, PREnd = PRVec.size(); PRIdx != PREnd;1194 ++PRIdx) {1195 MCWriteProcResEntry WPREntry;1196 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);1197 assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");1198 WPREntry.ReleaseAtCycle = ReleaseAtCycles[PRIdx];1199 WPREntry.AcquireAtCycle = AcquireAtCycles[PRIdx];1200 if (AcquireAtCycles[PRIdx] > ReleaseAtCycles[PRIdx]) {1201 PrintFatalError(1202 WriteRes->getLoc(),1203 Twine("Inconsistent resource cycles: AcquireAtCycles "1204 "<= ReleaseAtCycles must hold."));1205 }1206 if (AcquireAtCycles[PRIdx] < 0) {1207 PrintFatalError(WriteRes->getLoc(),1208 Twine("Invalid value: AcquireAtCycle "1209 "must be a non-negative value."));1210 }1211 // If this resource is already used in this sequence, add the current1212 // entry's cycles so that the same resource appears to be used1213 // serially, rather than multiple parallel uses. This is important for1214 // in-order machine where the resource consumption is a hazard.1215 unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();1216 for (; WPRIdx != WPREnd; ++WPRIdx) {1217 if (WriteProcResources[WPRIdx].ProcResourceIdx ==1218 WPREntry.ProcResourceIdx) {1219 // TODO: multiple use of the same resources would1220 // require either 1. thinking of how to handle multiple1221 // intervals for the same resource in1222 // `<Target>WriteProcResTable` (see1223 // `SubtargetEmitter::EmitSchedClassTables`), or1224 // 2. thinking how to merge multiple intervals into a1225 // single interval.1226 assert(WPREntry.AcquireAtCycle == 0 &&1227 "multiple use ofthe same resource is not yet handled");1228 WriteProcResources[WPRIdx].ReleaseAtCycle +=1229 WPREntry.ReleaseAtCycle;1230 break;1231 }1232 }1233 if (WPRIdx == WPREnd)1234 WriteProcResources.push_back(WPREntry);1235 }1236 }1237 WriteLatencies.push_back(WLEntry);1238 }1239 // Create an entry for each operand Read in this SchedClass.1240 // Entries must be sorted first by UseIdx then by WriteResourceID.1241 for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx;1242 ++UseIdx) {1243 const Record *ReadAdvance =1244 findReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);1245 if (!ReadAdvance)1246 continue;1247 1248 // Mark the parent class as invalid for unsupported write types.1249 if (ReadAdvance->getValueAsBit("Unsupported")) {1250 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;1251 break;1252 }1253 ConstRecVec ValidWrites =1254 ReadAdvance->getValueAsListOfDefs("ValidWrites");1255 std::vector<int64_t> CycleTunables =1256 ReadAdvance->getValueAsListOfInts("CycleTunables");1257 std::vector<std::pair<unsigned, int>> WriteIDs;1258 assert(CycleTunables.size() <= ValidWrites.size() && "Bad ReadAdvance");1259 CycleTunables.resize(ValidWrites.size(), 0);1260 if (ValidWrites.empty())1261 WriteIDs.emplace_back(0, 0);1262 else {1263 for (const auto [VW, CT] : zip_equal(ValidWrites, CycleTunables)) {1264 unsigned WriteID = SchedModels.getSchedRWIdx(VW, /*IsRead=*/false);1265 assert(WriteID != 0 &&1266 "Expected a valid SchedRW in the list of ValidWrites");1267 WriteIDs.emplace_back(WriteID, CT);1268 }1269 }1270 llvm::sort(WriteIDs);1271 for (const auto &[W, T] : WriteIDs) {1272 MCReadAdvanceEntry RAEntry;1273 RAEntry.UseIdx = UseIdx;1274 RAEntry.WriteResourceID = W;1275 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles") + T;1276 ReadAdvanceEntries.push_back(RAEntry);1277 }1278 }1279 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {1280 WriteProcResources.clear();1281 WriteLatencies.clear();1282 ReadAdvanceEntries.clear();1283 }1284 // Add the information for this SchedClass to the global tables using basic1285 // compression.1286 //1287 // WritePrecRes entries are sorted by ProcResIdx.1288 llvm::sort(WriteProcResources, LessWriteProcResources());1289 1290 SCDesc.NumWriteProcResEntries = WriteProcResources.size();1291 std::vector<MCWriteProcResEntry>::iterator WPRPos =1292 std::search(SchedTables.WriteProcResources.begin(),1293 SchedTables.WriteProcResources.end(),1294 WriteProcResources.begin(), WriteProcResources.end());1295 if (WPRPos != SchedTables.WriteProcResources.end())1296 SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();1297 else {1298 SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();1299 SchedTables.WriteProcResources.insert(WPRPos, WriteProcResources.begin(),1300 WriteProcResources.end());1301 }1302 // Latency entries must remain in operand order.1303 SCDesc.NumWriteLatencyEntries = WriteLatencies.size();1304 std::vector<MCWriteLatencyEntry>::iterator WLPos = std::search(1305 SchedTables.WriteLatencies.begin(), SchedTables.WriteLatencies.end(),1306 WriteLatencies.begin(), WriteLatencies.end());1307 if (WLPos != SchedTables.WriteLatencies.end()) {1308 unsigned Idx = WLPos - SchedTables.WriteLatencies.begin();1309 SCDesc.WriteLatencyIdx = Idx;1310 for (unsigned I = 0, E = WriteLatencies.size(); I < E; ++I)1311 if (SchedTables.WriterNames[Idx + I].find(WriterNames[I]) ==1312 std::string::npos) {1313 SchedTables.WriterNames[Idx + I] += "_" + WriterNames[I];1314 }1315 } else {1316 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();1317 llvm::append_range(SchedTables.WriteLatencies, WriteLatencies);1318 llvm::append_range(SchedTables.WriterNames, WriterNames);1319 }1320 // ReadAdvanceEntries must remain in operand order.1321 SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();1322 std::vector<MCReadAdvanceEntry>::iterator RAPos =1323 std::search(SchedTables.ReadAdvanceEntries.begin(),1324 SchedTables.ReadAdvanceEntries.end(),1325 ReadAdvanceEntries.begin(), ReadAdvanceEntries.end());1326 if (RAPos != SchedTables.ReadAdvanceEntries.end())1327 SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();1328 else {1329 SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();1330 llvm::append_range(SchedTables.ReadAdvanceEntries, ReadAdvanceEntries);1331 }1332 }1333}1334 1335// Emit SchedClass tables for all processors and associated global tables.1336void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables,1337 raw_ostream &OS) {1338 // Emit global WriteProcResTable.1339 OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n"1340 << "extern const llvm::MCWriteProcResEntry " << Target1341 << "WriteProcResTable[] = {\n"1342 << " { 0, 0, 0 }, // Invalid\n";1343 for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();1344 WPRIdx != WPREnd; ++WPRIdx) {1345 MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];1346 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "1347 << format("%2d", WPREntry.ReleaseAtCycle) << ", "1348 << format("%2d", WPREntry.AcquireAtCycle) << "}";1349 if (WPRIdx + 1 < WPREnd)1350 OS << ',';1351 OS << " // #" << WPRIdx << '\n';1352 }1353 OS << "}; // " << Target << "WriteProcResTable\n";1354 1355 // Emit global WriteLatencyTable.1356 OS << "\n// {Cycles, WriteResourceID}\n"1357 << "extern const llvm::MCWriteLatencyEntry " << Target1358 << "WriteLatencyTable[] = {\n"1359 << " { 0, 0}, // Invalid\n";1360 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();1361 WLIdx != WLEnd; ++WLIdx) {1362 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];1363 OS << " {" << format("%2d", WLEntry.Cycles) << ", "1364 << format("%2d", WLEntry.WriteResourceID) << "}";1365 if (WLIdx + 1 < WLEnd)1366 OS << ',';1367 OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';1368 }1369 OS << "}; // " << Target << "WriteLatencyTable\n";1370 1371 // Emit global ReadAdvanceTable.1372 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"1373 << "extern const llvm::MCReadAdvanceEntry " << Target1374 << "ReadAdvanceTable[] = {\n"1375 << " {0, 0, 0}, // Invalid\n";1376 for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();1377 RAIdx != RAEnd; ++RAIdx) {1378 MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];1379 OS << " {" << RAEntry.UseIdx << ", "1380 << format("%2d", RAEntry.WriteResourceID) << ", "1381 << format("%2d", RAEntry.Cycles) << "}";1382 if (RAIdx + 1 < RAEnd)1383 OS << ',';1384 OS << " // #" << RAIdx << '\n';1385 }1386 OS << "}; // " << Target << "ReadAdvanceTable\n";1387 1388 // Pool all SchedClass names in a string table.1389 StringToOffsetTable StrTab;1390 unsigned InvalidNameOff = StrTab.GetOrAddStringOffset("InvalidSchedClass");1391 1392 // Emit a SchedClass table for each processor.1393 for (const auto &[Idx, Proc] : enumerate(SchedModels.procModels())) {1394 if (!Proc.hasInstrSchedModel())1395 continue;1396 1397 std::vector<MCSchedClassDesc> &SCTab =1398 SchedTables.ProcSchedClasses[1 + Idx];1399 1400 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO,"1401 << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";1402 OS << "static const llvm::MCSchedClassDesc " << Proc.ModelName1403 << "SchedClasses[] = {\n";1404 1405 // The first class is always invalid. We no way to distinguish it except by1406 // name and position.1407 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" &&1408 "invalid class not first");1409 OS << " {DBGFIELD(" << InvalidNameOff << ") "1410 << MCSchedClassDesc::InvalidNumMicroOps1411 << ", false, false, false, 0, 0, 0, 0, 0, 0},\n";1412 1413 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {1414 MCSchedClassDesc &MCDesc = SCTab[SCIdx];1415 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);1416 unsigned NameOff = StrTab.GetOrAddStringOffset(SchedClass.Name);1417 OS << " {DBGFIELD(/*" << SchedClass.Name << "*/ " << NameOff << ") ";1418 if (SchedClass.Name.size() < 18)1419 OS.indent(18 - SchedClass.Name.size());1420 OS << MCDesc.NumMicroOps << ", " << (MCDesc.BeginGroup ? "true" : "false")1421 << ", " << (MCDesc.EndGroup ? "true" : "false") << ", "1422 << (MCDesc.RetireOOO ? "true" : "false") << ", "1423 << format("%2d", MCDesc.WriteProcResIdx) << ", "1424 << MCDesc.NumWriteProcResEntries << ", "1425 << format("%2d", MCDesc.WriteLatencyIdx) << ", "1426 << MCDesc.NumWriteLatencyEntries << ", "1427 << format("%2d", MCDesc.ReadAdvanceIdx) << ", "1428 << MCDesc.NumReadAdvanceEntries << "}, // #" << SCIdx << '\n';1429 }1430 OS << "}; // " << Proc.ModelName << "SchedClasses\n";1431 }1432 1433 StrTab.EmitStringTableDef(OS, Target + "SchedClassNames");1434}1435 1436void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) {1437 // For each processor model.1438 for (const CodeGenProcModel &PM : SchedModels.procModels()) {1439 // Emit extra processor info if available.1440 if (PM.hasExtraProcessorInfo())1441 emitExtraProcessorInfo(PM, OS);1442 // Emit processor resource table.1443 if (PM.hasInstrSchedModel())1444 emitProcessorResources(PM, OS);1445 else if (!PM.ProcResourceDefs.empty())1446 PrintFatalError(PM.ModelDef->getLoc(),1447 "SchedMachineModel defines "1448 "ProcResources without defining WriteRes SchedWriteRes");1449 1450 // Begin processor itinerary properties1451 OS << "\n";1452 OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n";1453 emitProcessorProp(OS, PM.ModelDef, "IssueWidth", ',');1454 emitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ',');1455 emitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ',');1456 emitProcessorProp(OS, PM.ModelDef, "LoadLatency", ',');1457 emitProcessorProp(OS, PM.ModelDef, "HighLatency", ',');1458 emitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ',');1459 1460 bool PostRAScheduler =1461 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false);1462 1463 OS << " " << (PostRAScheduler ? "true" : "false") << ", // "1464 << "PostRAScheduler\n";1465 1466 bool CompleteModel =1467 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false);1468 1469 OS << " " << (CompleteModel ? "true" : "false") << ", // "1470 << "CompleteModel\n";1471 1472 bool EnableIntervals =1473 (PM.ModelDef ? PM.ModelDef->getValueAsBit("EnableIntervals") : false);1474 1475 OS << " " << (EnableIntervals ? "true" : "false") << ", // "1476 << "EnableIntervals\n";1477 1478 OS << " " << PM.Index << ", // Processor ID\n";1479 if (PM.hasInstrSchedModel())1480 OS << " " << PM.ModelName << "ProcResources" << ",\n"1481 << " " << PM.ModelName << "SchedClasses" << ",\n"1482 << " " << PM.ProcResourceDefs.size() + 1 << ",\n"1483 << " " << SchedModels.schedClasses().size() << ",\n";1484 else1485 OS << " nullptr, nullptr, 0, 0,"1486 << " // No instruction-level machine model.\n";1487 OS << " DBGVAL_OR_NULLPTR(&" << Target1488 << "SchedClassNames), // SchedClassNames\n";1489 if (PM.hasItineraries())1490 OS << " " << PM.ItinsDef->getName() << ",\n";1491 else1492 OS << " nullptr, // No Itinerary\n";1493 if (PM.hasExtraProcessorInfo())1494 OS << " &" << PM.ModelName << "ExtraInfo,\n";1495 else1496 OS << " nullptr // No extra processor descriptor\n";1497 OS << "};\n";1498 }1499}1500 1501//1502// EmitSchedModel - Emits all scheduling model tables, folding common patterns.1503//1504void SubtargetEmitter::emitSchedModel(raw_ostream &OS) {1505 OS << "#ifdef DBGFIELD\n"1506 << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"1507 << "#endif\n"1508 << "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)\n"1509 << "#define DBGFIELD(x) x,\n"1510 << "#define DBGVAL_OR_NULLPTR(x) x\n"1511 << "#else\n"1512 << "#define DBGFIELD(x)\n"1513 << "#define DBGVAL_OR_NULLPTR(x) nullptr\n"1514 << "#endif\n";1515 1516 if (SchedModels.hasItineraries()) {1517 std::vector<std::vector<InstrItinerary>> ProcItinLists;1518 // Emit the stage data1519 emitStageAndOperandCycleData(OS, ProcItinLists);1520 emitItineraries(OS, ProcItinLists);1521 }1522 OS << "\n// ===============================================================\n"1523 << "// Data tables for the new per-operand machine model.\n";1524 1525 SchedClassTables SchedTables;1526 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {1527 genSchedClassTables(ProcModel, SchedTables);1528 }1529 emitSchedClassTables(SchedTables, OS);1530 1531 // Emit the processor machine model1532 emitProcessorModels(OS);1533 1534 OS << "\n#undef DBGFIELD\n";1535 OS << "\n#undef DBGVAL_OR_NULLPTR\n";1536}1537 1538static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {1539 std::string Buffer;1540 raw_string_ostream Stream(Buffer);1541 1542 // Print all PredicateProlog records to the output stream.1543 for (const Record *P : Records.getAllDerivedDefinitions("PredicateProlog"))1544 Stream << P->getValueAsString("Code") << '\n';1545 1546 OS << Buffer;1547}1548 1549static bool isTruePredicate(const Record *Rec) {1550 return Rec->isSubClassOf("MCSchedPredicate") &&1551 Rec->getValueAsDef("Pred")->isSubClassOf("MCTrue");1552}1553 1554static void emitPredicates(const CodeGenSchedTransition &T,1555 const CodeGenSchedClass &SC, PredicateExpander &PE,1556 raw_ostream &OS) {1557 std::string Buffer;1558 raw_string_ostream SS(Buffer);1559 1560 // If not all predicates are MCTrue, then we need an if-stmt.1561 unsigned NumNonTruePreds =1562 T.PredTerm.size() - count_if(T.PredTerm, isTruePredicate);1563 1564 SS << PE.getIndent();1565 1566 if (NumNonTruePreds) {1567 bool FirstNonTruePredicate = true;1568 SS << "if (";1569 1570 PE.getIndent() += 2;1571 1572 for (const Record *Rec : T.PredTerm) {1573 // Skip predicates that evaluate to "true".1574 if (isTruePredicate(Rec))1575 continue;1576 1577 if (FirstNonTruePredicate) {1578 FirstNonTruePredicate = false;1579 } else {1580 SS << "\n";1581 SS << PE.getIndent();1582 SS << "&& ";1583 }1584 1585 if (Rec->isSubClassOf("MCSchedPredicate")) {1586 PE.expandPredicate(SS, Rec->getValueAsDef("Pred"));1587 continue;1588 }1589 1590 if (Rec->isSubClassOf("FeatureSchedPredicate")) {1591 const Record *FR = Rec->getValueAsDef("Feature");1592 if (PE.shouldExpandForMC()) {1593 // MC version of this predicate will be emitted into1594 // resolveVariantSchedClassImpl, which accesses MCSubtargetInfo1595 // through argument STI.1596 SS << "STI.";1597 } else {1598 // Otherwise, this predicate will be emitted directly into1599 // TargetGenSubtargetInfo::resolveSchedClass, which can just access1600 // TargetSubtargetInfo / MCSubtargetInfo through `this`.1601 SS << "this->";1602 }1603 SS << "hasFeature(" << PE.getTargetName() << "::" << FR->getName()1604 << ")";1605 continue;1606 }1607 1608 // Expand this legacy predicate and wrap it around braces if there is more1609 // than one predicate to expand.1610 SS << ((NumNonTruePreds > 1) ? "(" : "")1611 << Rec->getValueAsString("Predicate")1612 << ((NumNonTruePreds > 1) ? ")" : "");1613 }1614 1615 SS << ")\n"; // end of if-stmt1616 --PE.getIndent();1617 SS << PE.getIndent();1618 --PE.getIndent();1619 }1620 1621 SS << "return " << T.ToClassIdx << "; // " << SC.Name << '\n';1622 OS << Buffer;1623}1624 1625// Used by method `SubtargetEmitter::emitSchedModelHelpersImpl()` to generate1626// epilogue code for the auto-generated helper.1627static void emitSchedModelHelperEpilogue(raw_ostream &OS,1628 bool ShouldReturnZero) {1629 if (ShouldReturnZero) {1630 OS << " // Don't know how to resolve this scheduling class.\n"1631 << " return 0;\n";1632 return;1633 }1634 1635 OS << " report_fatal_error(\"Expected a variant SchedClass\");\n";1636}1637 1638static bool hasMCSchedPredicates(const CodeGenSchedTransition &T) {1639 return all_of(T.PredTerm, [](const Record *Rec) {1640 return Rec->isSubClassOf("MCSchedPredicate") ||1641 Rec->isSubClassOf("FeatureSchedPredicate");1642 });1643}1644 1645static void collectVariantClasses(const CodeGenSchedModels &SchedModels,1646 IdxVec &VariantClasses,1647 bool OnlyExpandMCInstPredicates) {1648 for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {1649 // Ignore non-variant scheduling classes.1650 if (SC.Transitions.empty())1651 continue;1652 1653 if (OnlyExpandMCInstPredicates) {1654 // Ignore this variant scheduling class no transitions use any meaningful1655 // MCSchedPredicate definitions.1656 if (llvm::none_of(SC.Transitions, hasMCSchedPredicates))1657 continue;1658 }1659 1660 VariantClasses.push_back(SC.Index);1661 }1662}1663 1664static void collectProcessorIndices(const CodeGenSchedClass &SC,1665 IdxVec &ProcIndices) {1666 // A variant scheduling class may define transitions for multiple1667 // processors. This function identifies wich processors are associated with1668 // transition rules specified by variant class `SC`.1669 for (const CodeGenSchedTransition &T : SC.Transitions) {1670 IdxVec PI;1671 std::set_union(&T.ProcIndex, &T.ProcIndex + 1, ProcIndices.begin(),1672 ProcIndices.end(), std::back_inserter(PI));1673 ProcIndices = std::move(PI);1674 }1675}1676 1677static bool isAlwaysTrue(const CodeGenSchedTransition &T) {1678 return llvm::all_of(T.PredTerm, isTruePredicate);1679}1680 1681void SubtargetEmitter::emitSchedModelHelpersImpl(1682 raw_ostream &OS, bool OnlyExpandMCInstPredicates) {1683 IdxVec VariantClasses;1684 collectVariantClasses(SchedModels, VariantClasses,1685 OnlyExpandMCInstPredicates);1686 1687 if (VariantClasses.empty()) {1688 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates);1689 return;1690 }1691 1692 // Construct a switch statement where the condition is a check on the1693 // scheduling class identifier. There is a `case` for every variant class1694 // defined by the processor models of this target.1695 // Each `case` implements a number of rules to resolve (i.e. to transition1696 // from) a variant scheduling class to another scheduling class. Rules are1697 // described by instances of CodeGenSchedTransition. Note that transitions may1698 // not be valid for all processors.1699 OS << " switch (SchedClass) {\n";1700 for (unsigned VC : VariantClasses) {1701 IdxVec ProcIndices;1702 const CodeGenSchedClass &SC = SchedModels.getSchedClass(VC);1703 collectProcessorIndices(SC, ProcIndices);1704 1705 OS << " case " << VC << ": // " << SC.Name << '\n';1706 1707 PredicateExpander PE(Target);1708 PE.setByRef(false);1709 PE.setExpandForMC(OnlyExpandMCInstPredicates);1710 for (unsigned PI : ProcIndices) {1711 OS << " ";1712 1713 // Emit a guard on the processor ID.1714 if (PI != 0) {1715 OS << (OnlyExpandMCInstPredicates1716 ? "if (CPUID == "1717 : "if (SchedModel->getProcessorID() == ");1718 OS << PI << ") ";1719 OS << "{ // " << SchedModels.procModels()[PI].ModelName << '\n';1720 }1721 1722 // Now emit transitions associated with processor PI.1723 const CodeGenSchedTransition *FinalT = nullptr;1724 for (const CodeGenSchedTransition &T : SC.Transitions) {1725 if (PI != 0 && T.ProcIndex != PI)1726 continue;1727 1728 // Emit only transitions based on MCSchedPredicate, if it's the case.1729 // At least the transition specified by NoSchedPred is emitted,1730 // which becomes the default transition for those variants otherwise1731 // not based on MCSchedPredicate.1732 // FIXME: preferably, llvm-mca should instead assume a reasonable1733 // default when a variant transition is not based on MCSchedPredicate1734 // for a given processor.1735 if (OnlyExpandMCInstPredicates && !hasMCSchedPredicates(T))1736 continue;1737 1738 // If transition is folded to 'return X' it should be the last one.1739 if (isAlwaysTrue(T)) {1740 FinalT = &T;1741 continue;1742 }1743 PE.getIndent() = 3;1744 emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);1745 }1746 if (FinalT)1747 emitPredicates(*FinalT, SchedModels.getSchedClass(FinalT->ToClassIdx),1748 PE, OS);1749 1750 OS << " }\n";1751 1752 if (PI == 0)1753 break;1754 }1755 1756 if (SC.isInferred())1757 OS << " return " << SC.Index << ";\n";1758 OS << " break;\n";1759 }1760 1761 OS << " };\n";1762 1763 emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates);1764}1765 1766void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName,1767 raw_ostream &OS) {1768 OS << "unsigned " << ClassName1769 << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"1770 << " const TargetSchedModel *SchedModel) const {\n";1771 1772 // Emit the predicate prolog code.1773 emitPredicateProlog(Records, OS);1774 1775 // Emit target predicates.1776 emitSchedModelHelpersImpl(OS);1777 1778 OS << "} // " << ClassName << "::resolveSchedClass\n\n";1779 1780 OS << "unsigned " << ClassName1781 << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"1782 << " const MCInstrInfo *MCII, unsigned CPUID) const {\n"1783 << " return " << Target << "_MC"1784 << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n"1785 << "} // " << ClassName << "::resolveVariantSchedClass\n\n";1786 1787 STIPredicateExpander PE(Target, /*Indent=*/0);1788 PE.setClassPrefix(ClassName);1789 PE.setExpandDefinition(true);1790 PE.setByRef(false);1791 1792 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())1793 PE.expandSTIPredicate(OS, Fn);1794}1795 1796void SubtargetEmitter::emitHwModeCheck(const std::string &ClassName,1797 raw_ostream &OS, bool IsMC) {1798 const CodeGenHwModes &CGH = TGT.getHwModes();1799 assert(CGH.getNumModeIds() > 0);1800 if (CGH.getNumModeIds() == 1)1801 return;1802 1803 // Collect all HwModes and related features defined in the TD files,1804 // and store them as a bit set.1805 unsigned ValueTypeModes = 0;1806 unsigned RegInfoModes = 0;1807 unsigned EncodingInfoModes = 0;1808 for (const auto &MS : CGH.getHwModeSelects()) {1809 for (const HwModeSelect::PairType &P : MS.second.Items) {1810 if (P.first == DefaultMode)1811 continue;1812 if (P.second->isSubClassOf("ValueType")) {1813 ValueTypeModes |= (1 << (P.first - 1));1814 } else if (P.second->isSubClassOf("RegInfo") ||1815 P.second->isSubClassOf("SubRegRange") ||1816 P.second->isSubClassOf("RegisterClassLike")) {1817 RegInfoModes |= (1 << (P.first - 1));1818 } else if (P.second->isSubClassOf("InstructionEncoding")) {1819 EncodingInfoModes |= (1 << (P.first - 1));1820 }1821 }1822 }1823 1824 // Start emitting for getHwModeSet().1825 OS << "unsigned " << ClassName << "::getHwModeSet() const {\n";1826 if (IsMC) {1827 OS << " [[maybe_unused]] const FeatureBitset &FB = getFeatureBits();\n";1828 } else {1829 const ArrayRef<const Record *> &Prologs =1830 Records.getAllDerivedDefinitions("HwModePredicateProlog");1831 if (!Prologs.empty()) {1832 for (const Record *P : Prologs)1833 OS << P->getValueAsString("Code") << '\n';1834 } else {1835 // Works for most targets.1836 OS << " [[maybe_unused]] const auto *Subtarget =\n"1837 << " static_cast<const " << Target << "Subtarget *>(this);\n";1838 }1839 }1840 OS << " // Collect HwModes and store them as a bit set.\n";1841 OS << " unsigned Modes = 0;\n";1842 for (unsigned M = 1, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {1843 const HwMode &HM = CGH.getMode(M);1844 OS << " if (";1845 if (IsMC)1846 SubtargetFeatureInfo::emitMCPredicateCheck(OS, Target, HM.Predicates);1847 else1848 SubtargetFeatureInfo::emitPredicateCheck(OS, HM.Predicates);1849 OS << ") Modes |= (1 << " << (M - 1) << ");\n";1850 }1851 OS << " return Modes;\n}\n";1852 // End emitting for getHwModeSet().1853 1854 auto HandlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) {1855 OS << " case HwMode_" << ModeType << ":\n"1856 << " Modes &= " << ModeInBitSet << ";\n"1857 << " if (!Modes)\n return Modes;\n"1858 << " if (!llvm::has_single_bit<unsigned>(Modes))\n"1859 << " llvm_unreachable(\"Two or more HwModes for " << ModeType1860 << " were found!\");\n"1861 << " return llvm::countr_zero(Modes) + 1;\n";1862 };1863 1864 // Start emitting for getHwMode().1865 OS << "unsigned " << ClassName1866 << "::getHwMode(enum HwModeType type) const {\n";1867 OS << " unsigned Modes = getHwModeSet();\n\n";1868 OS << " if (!Modes)\n return Modes;\n\n";1869 OS << " switch (type) {\n";1870 OS << " case HwMode_Default:\n return llvm::countr_zero(Modes) + 1;\n";1871 HandlePerMode("ValueType", ValueTypeModes);1872 HandlePerMode("RegInfo", RegInfoModes);1873 HandlePerMode("EncodingInfo", EncodingInfoModes);1874 OS << " }\n";1875 OS << " llvm_unreachable(\"unexpected HwModeType\");\n"1876 << " return 0; // should not get here\n}\n";1877 // End emitting for getHwMode().1878}1879 1880void SubtargetEmitter::emitGetMacroFusions(const std::string &ClassName,1881 raw_ostream &OS) {1882 if (!TGT.hasMacroFusion())1883 return;1884 1885 OS << "std::vector<MacroFusionPredTy> " << ClassName1886 << "::getMacroFusions() const {\n";1887 OS.indent(2) << "std::vector<MacroFusionPredTy> Fusions;\n";1888 for (auto *Fusion : TGT.getMacroFusions()) {1889 std::string Name = Fusion->getNameInitAsString();1890 OS.indent(2) << "if (hasFeature(" << Target << "::" << Name1891 << ")) Fusions.push_back(llvm::is" << Name << ");\n";1892 }1893 1894 OS.indent(2) << "return Fusions;\n";1895 OS << "}\n";1896}1897 1898// Produces a subtarget specific function for parsing1899// the subtarget features string.1900void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) {1901 ArrayRef<const Record *> Features =1902 Records.getAllDerivedDefinitions("SubtargetFeature");1903 1904 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"1905 << "// subtarget options.\n"1906 << "void llvm::";1907 OS << Target;1908 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, "1909 << "StringRef FS) {\n"1910 << " LLVM_DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"1911 << " LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n"1912 << " LLVM_DEBUG(dbgs() << \"\\nTuneCPU:\" << TuneCPU << \"\\n\\n\");\n";1913 1914 if (Features.empty()) {1915 OS << "}\n";1916 return;1917 }1918 1919 if (Target == "AArch64")1920 OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"1921 << " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";1922 1923 OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"1924 << " const FeatureBitset &Bits = getFeatureBits();\n";1925 1926 for (const Record *R : Features) {1927 // Next record1928 StringRef Instance = R->getName();1929 StringRef Value = R->getValueAsString("Value");1930 StringRef FieldName = R->getValueAsString("FieldName");1931 1932 if (Value == "true" || Value == "false")1933 OS << " if (Bits[" << Target << "::" << Instance << "]) " << FieldName1934 << " = " << Value << ";\n";1935 else1936 OS << " if (Bits[" << Target << "::" << Instance << "] && " << FieldName1937 << " < " << Value << ") " << FieldName << " = " << Value << ";\n";1938 }1939 1940 OS << "}\n";1941}1942 1943void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {1944 {1945 NamespaceEmitter NS(OS, (Target + Twine("_MC")).str());1946 OS << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"1947 << " const MCInst *MI, const MCInstrInfo *MCII, "1948 << "const MCSubtargetInfo &STI, unsigned CPUID) {\n";1949 emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true);1950 OS << "}\n";1951 }1952 1953 OS << "struct " << Target1954 << "GenMCSubtargetInfo : public MCSubtargetInfo {\n";1955 OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT,\n"1956 << " StringRef CPU, StringRef TuneCPU, StringRef FS,\n"1957 << " ArrayRef<StringRef> PN,\n"1958 << " ArrayRef<SubtargetFeatureKV> PF,\n"1959 << " ArrayRef<SubtargetSubTypeKV> PD,\n"1960 << " const MCWriteProcResEntry *WPR,\n"1961 << " const MCWriteLatencyEntry *WL,\n"1962 << " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"1963 << " const unsigned *OC, const unsigned *FP) :\n"1964 << " MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,\n"1965 << " WPR, WL, RA, IS, OC, FP) { }\n\n"1966 << " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"1967 << " const MCInst *MI, const MCInstrInfo *MCII,\n"1968 << " unsigned CPUID) const override {\n"1969 << " return " << Target << "_MC"1970 << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n";1971 OS << " }\n";1972 if (TGT.getHwModes().getNumModeIds() > 1) {1973 OS << " unsigned getHwModeSet() const override;\n";1974 OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "1975 "override;\n";1976 }1977 if (Target == "AArch64")1978 OS << " bool isCPUStringValid(StringRef CPU) const override {\n"1979 << " CPU = AArch64::resolveCPUAlias(CPU);\n"1980 << " return MCSubtargetInfo::isCPUStringValid(CPU);\n"1981 << " }\n";1982 OS << "};\n";1983 emitHwModeCheck(Target + "GenMCSubtargetInfo", OS, /*IsMC=*/true);1984}1985 1986void SubtargetEmitter::emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS) {1987 STIPredicateExpander PE(Target, /*Indent=*/0);1988 1989 {1990 IfDefEmitter IfDefDecls(OS, "GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS");1991 PE.setExpandForMC(true);1992 PE.setByRef(true);1993 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())1994 PE.expandSTIPredicate(OS, Fn);1995 }1996 1997 IfDefEmitter IfDefDefs(OS, "GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS");1998 std::string ClassPrefix = Target + "MCInstrAnalysis";1999 PE.setExpandDefinition(true);2000 PE.setClassPrefix(ClassPrefix);2001 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())2002 PE.expandSTIPredicate(OS, Fn);2003}2004 2005FeatureMapTy SubtargetEmitter::emitEnums(raw_ostream &OS) {2006 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_ENUM");2007 NamespaceEmitter NS(OS, "llvm");2008 return enumeration(OS);2009}2010 2011std::tuple<unsigned, unsigned, unsigned>2012SubtargetEmitter::emitMCDesc(raw_ostream &OS, const FeatureMapTy &FeatureMap) {2013 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_MC_DESC");2014 if (Target == "AArch64")2015 OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";2016 NamespaceEmitter LlvmNS(OS, "llvm");2017 2018 unsigned NumFeatures = featureKeyValues(OS, FeatureMap);2019 OS << "\n";2020 emitSchedModel(OS);2021 OS << "\n";2022 unsigned NumProcs = cpuKeyValues(OS, FeatureMap);2023 OS << "\n";2024 unsigned NumNames = cpuNames(OS);2025 OS << "\n";2026 2027 // MCInstrInfo initialization routine.2028 emitGenMCSubtargetInfo(OS);2029 2030 OS << "\nstatic inline MCSubtargetInfo *create" << Target2031 << "MCSubtargetInfoImpl("2032 << "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n";2033 if (Target == "AArch64")2034 OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"2035 << " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";2036 OS << " return new " << Target2037 << "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";2038 if (NumNames)2039 OS << Target << "Names, ";2040 else2041 OS << "{}, ";2042 if (NumFeatures)2043 OS << Target << "FeatureKV, ";2044 else2045 OS << "{}, ";2046 if (NumProcs)2047 OS << Target << "SubTypeKV, ";2048 else2049 OS << "{}, ";2050 OS << '\n';2051 OS.indent(22);2052 OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "2053 << Target << "ReadAdvanceTable, ";2054 OS << '\n';2055 OS.indent(22);2056 if (SchedModels.hasItineraries()) {2057 OS << Target << "Stages, " << Target << "OperandCycles, " << Target2058 << "ForwardingPaths";2059 } else {2060 OS << "nullptr, nullptr, nullptr";2061 }2062 OS << ");\n}\n\n";2063 return {NumNames, NumFeatures, NumProcs};2064}2065 2066void SubtargetEmitter::emitTargetDesc(raw_ostream &OS) {2067 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_TARGET_DESC");2068 2069 OS << "#include \"llvm/ADT/BitmaskEnum.h\"\n";2070 OS << "#include \"llvm/Support/Debug.h\"\n";2071 OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";2072 if (Target == "AArch64")2073 OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";2074 parseFeaturesFunction(OS);2075}2076 2077void SubtargetEmitter::emitHeader(raw_ostream &OS) {2078 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.2079 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_HEADER");2080 NamespaceEmitter LLVMNS(OS, "llvm");2081 2082 std::string ClassName = Target + "GenSubtargetInfo";2083 OS << "class DFAPacketizer;\n";2084 {2085 NamespaceEmitter MCNS(OS, (Target + Twine("_MC")).str());2086 OS << "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"2087 << " const MCInst *MI, const MCInstrInfo *MCII, "2088 << "const MCSubtargetInfo &STI, unsigned CPUID);\n";2089 }2090 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"2091 << " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "2092 << "StringRef TuneCPU, StringRef FS);\n"2093 << "public:\n"2094 << " unsigned resolveSchedClass(unsigned SchedClass, "2095 << " const MachineInstr *DefMI,"2096 << " const TargetSchedModel *SchedModel) const override;\n"2097 << " unsigned resolveVariantSchedClass(unsigned SchedClass,"2098 << " const MCInst *MI, const MCInstrInfo *MCII,"2099 << " unsigned CPUID) const override;\n"2100 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"2101 << " const;\n";2102 2103 const CodeGenHwModes &CGH = TGT.getHwModes();2104 if (CGH.getNumModeIds() > 1) {2105 OS << " enum class " << Target << "HwModeBits : unsigned {\n";2106 for (unsigned M = 0, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {2107 StringRef ModeName = CGH.getModeName(M, /*IncludeDefault=*/true);2108 OS << " " << ModeName << " = ";2109 if (M == 0)2110 OS << "0";2111 else2112 OS << "(1 << " << (M - 1) << ")";2113 OS << ",\n";2114 if (M == NumModes - 1) {2115 OS << "\n";2116 OS << " LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/" << ModeName2117 << "),\n";2118 }2119 }2120 OS << " };\n";2121 2122 OS << " unsigned getHwModeSet() const override;\n";2123 OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "2124 "override;\n";2125 }2126 if (TGT.hasMacroFusion())2127 OS << " std::vector<MacroFusionPredTy> getMacroFusions() const "2128 "override;\n";2129 2130 STIPredicateExpander PE(Target);2131 PE.setByRef(false);2132 for (const STIPredicateFunction &Fn : SchedModels.getSTIPredicates())2133 PE.expandSTIPredicate(OS, Fn);2134 OS << "};\n";2135}2136 2137void SubtargetEmitter::emitCtor(raw_ostream &OS, unsigned NumNames,2138 unsigned NumFeatures, unsigned NumProcs) {2139 IfDefEmitter IfDef(OS, "GET_SUBTARGETINFO_CTOR");2140 OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n";2141 2142 NamespaceEmitter LLVMNS(OS, "llvm");2143 OS << "extern const llvm::StringRef " << Target << "Names[];\n";2144 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";2145 OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n";2146 OS << "extern const llvm::MCWriteProcResEntry " << Target2147 << "WriteProcResTable[];\n";2148 OS << "extern const llvm::MCWriteLatencyEntry " << Target2149 << "WriteLatencyTable[];\n";2150 OS << "extern const llvm::MCReadAdvanceEntry " << Target2151 << "ReadAdvanceTable[];\n";2152 2153 if (SchedModels.hasItineraries()) {2154 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";2155 OS << "extern const unsigned " << Target << "OperandCycles[];\n";2156 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";2157 }2158 2159 std::string ClassName = Target + "GenSubtargetInfo";2160 OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "2161 << "StringRef TuneCPU, StringRef FS)\n";2162 2163 if (Target == "AArch64")2164 OS << " : TargetSubtargetInfo(TT, AArch64::resolveCPUAlias(CPU),\n"2165 << " AArch64::resolveCPUAlias(TuneCPU), FS, ";2166 else2167 OS << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";2168 if (NumNames)2169 OS << "ArrayRef(" << Target << "Names, " << NumNames << "), ";2170 else2171 OS << "{}, ";2172 if (NumFeatures)2173 OS << "ArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";2174 else2175 OS << "{}, ";2176 if (NumProcs)2177 OS << "ArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";2178 else2179 OS << "{}, ";2180 OS << '\n';2181 OS.indent(24);2182 OS << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, "2183 << Target << "ReadAdvanceTable, ";2184 OS << '\n';2185 OS.indent(24);2186 if (SchedModels.hasItineraries()) {2187 OS << Target << "Stages, " << Target << "OperandCycles, " << Target2188 << "ForwardingPaths";2189 } else {2190 OS << "nullptr, nullptr, nullptr";2191 }2192 OS << ") {}\n\n";2193 2194 emitSchedModelHelpers(ClassName, OS);2195 emitHwModeCheck(ClassName, OS, /*IsMC=*/false);2196 emitGetMacroFusions(ClassName, OS);2197}2198 2199//2200// SubtargetEmitter::run - Main subtarget enumeration emitter.2201//2202void SubtargetEmitter::run(raw_ostream &OS) {2203 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);2204 2205 auto FeatureMap = emitEnums(OS);2206 emitSubtargetInfoMacroCalls(OS);2207 auto [NumNames, NumFeatures, NumProcs] = emitMCDesc(OS, FeatureMap);2208 emitTargetDesc(OS);2209 emitHeader(OS);2210 emitCtor(OS, NumNames, NumFeatures, NumProcs);2211 emitMcInstrAnalysisPredicateFunctions(OS);2212}2213 2214static TableGen::Emitter::OptClass<SubtargetEmitter>2215 X("gen-subtarget", "Generate subtarget enumerations");2216