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1// RUN: mlir-opt %s -convert-amdgpu-to-rocdl=chipset=gfx942 | FileCheck %s2 3// CHECK-LABEL: func @ext_scalar4// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %{{.+}} : f8E5M2FNUZ to i85// CHECK-DAG: [[UNDEF:%.+]] = llvm.mlir.undef : vector<4xi8>6// CHECK-DAG: [[C0_1:%.+]] = llvm.mlir.constant(0 : i32) : i327// CHECK: [[VEC:%.+]] = llvm.insertelement [[V]], [[UNDEF]]{{\[}}[[C0_1]] : i32] : vector<4xi8>8// CHECK: [[CAST:%.+]] = llvm.bitcast [[VEC]] : vector<4xi8> to i329// CHECK: [[EXT:%.+]] = rocdl.cvt.f32.bf8 [[CAST]][0] : f3210// CHECK: return [[EXT]] : f3211func.func @ext_scalar(%v: f8E5M2FNUZ) -> f32 {12 %ret = amdgpu.ext_packed_fp8 %v[0] : f8E5M2FNUZ to f3213 func.return %ret : f3214}15 16// CHECK-LABEL: func @ext_short_vec17// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %{{.+}} : vector<2xf8E4M3FNUZ> to vector<2xi8>18// CHECK-DAG: [[UNDEF:%.+]] = llvm.mlir.undef : vector<4xi8>19// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i3220// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>21// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[UNDEF]]{{\[}}[[C0]] : i32] : vector<4xi8>22// CHECK: [[C1_1:%.+]] = llvm.mlir.constant(1 : i32) : i3223// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1_1]] : i32] : vector<2xi8>24// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1_1]] : i32] : vector<4xi8>25// CHECK: [[CAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i3226// CHECK: [[EXT:%.+]] = rocdl.cvt.f32.fp8 [[CAST]][1] : f3227// CHECK: return [[EXT]] : f3228func.func @ext_short_vec(%v: vector<2xf8E4M3FNUZ>) -> f32 {29 %ret = amdgpu.ext_packed_fp8 %v[1] : vector<2xf8E4M3FNUZ> to f3230 func.return %ret : f3231}32 33// CHECK-LABEL: func @ext_full_vec34// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %{{.+}} : vector<4xf8E4M3FNUZ> to vector<4xi8>35// CHECK: [[CAST:%.+]] = llvm.bitcast [[V]] : vector<4xi8> to i3236// CHECK: [[EXT:%.+]] = rocdl.cvt.f32.fp8 [[CAST]][3] : f3237// CHECK: return [[EXT]] : f3238func.func @ext_full_vec(%v: vector<4xf8E4M3FNUZ>) -> f32 {39 %ret = amdgpu.ext_packed_fp8 %v[3] : vector<4xf8E4M3FNUZ> to f3240 func.return %ret : f3241}42 43// CHECK-LABEL: func @ext_packed_2xfp844// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %{{.+}} : vector<2xf8E4M3FNUZ> to vector<2xi8>45// CHECK-DAG: [[UNDEF:%.+]] = llvm.mlir.undef : vector<4xi8>46// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i3247// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>48// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[UNDEF]]{{\[}}[[C0]] : i32] : vector<4xi8>49// CHECK: [[C1_1:%.+]] = llvm.mlir.constant(1 : i32) : i3250// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1_1]] : i32] : vector<2xi8>51// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1_1]] : i32] : vector<4xi8>52// CHECK: [[CAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i3253// CHECK: [[EXT:%.+]] = rocdl.cvt.pk.f32.fp8 [[CAST]][false] : vector<2xf32>54// CHECK: return [[EXT]]55func.func @ext_packed_2xfp8(%v: vector<2xf8E4M3FNUZ>) -> vector<2xf32> {56 %ret = amdgpu.ext_packed_fp8 %v[0] : vector<2xf8E4M3FNUZ> to vector<2xf32>57 func.return %ret : vector<2xf32>58}59 60// CHECK-LABEL: func @ext_packed_4xfp8(61// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %{{.+}} : vector<4xf8E4M3FNUZ> to vector<4xi8>62// CHECK: [[CAST:%.+]] = llvm.bitcast [[V]] : vector<4xi8> to i3263// CHECK: [[EXT:%.+]] = rocdl.cvt.pk.f32.fp8 [[CAST]][true] : vector<2xf32>64// CHECK: return [[EXT]] : vector<2xf32>65func.func @ext_packed_4xfp8(%v: vector<4xf8E4M3FNUZ>) -> vector<2xf32> {66 %ret = amdgpu.ext_packed_fp8 %v[1] : vector<4xf8E4M3FNUZ> to vector<2xf32>67 func.return %ret : vector<2xf32>68}69 70// CHECK-LABEL: func @packed_trunc71// CHECK-SAME: ([[V:%.+]]: f32)72// CHECK: [[V2:%.+]] = llvm.mlir.undef : f3273// CHECK: [[EXISTING:%.+]] = llvm.mlir.undef : i3274// CHECK: [[PACKED:%.+]] = rocdl.cvt.pk.fp8.f32 [[V]], [[V2]] -> [[EXISTING]][false] : i3275// CHECK: [[CAST:%.+]] = llvm.bitcast [[PACKED]] : i32 to vector<4xi8>76// CHECK: builtin.unrealized_conversion_cast [[CAST]] : vector<4xi8> to vector<4xf8E4M3FNUZ>77func.func @packed_trunc(%v: f32) -> vector<4xf8E4M3FNUZ> {78 %ret = amdgpu.packed_trunc_2xfp8 %v, undef into undef[word 0] : f32 to vector<4xf8E4M3FNUZ>79 func.return %ret : vector<4xf8E4M3FNUZ>80}81 82// CHECK-LABEL: func @packed_truncx283// CHECK-SAME: ([[V:%.+]]: f32, [[W:%.+]]: f32)84// CHECK: [[EXISTING:%.+]] = llvm.mlir.undef : i3285// CHECK: [[PACKED:%.+]] = rocdl.cvt.pk.fp8.f32 [[V]], [[W]] -> [[EXISTING]][false] : i3286// CHECK: [[CAST:%.+]] = llvm.bitcast [[PACKED]] : i32 to vector<4xi8>87// CHECK: builtin.unrealized_conversion_cast [[CAST]] : vector<4xi8> to vector<4xf8E4M3FNUZ>88func.func @packed_truncx2(%v: f32, %w: f32) -> vector<4xf8E4M3FNUZ> {89 %ret = amdgpu.packed_trunc_2xfp8 %v, %w into undef[word 0] : f32 to vector<4xf8E4M3FNUZ>90 func.return %ret : vector<4xf8E4M3FNUZ>91}92 93// CHECK-LABEL: func @packed_truncx2_into94// CHECK-SAME: ([[V:%.+]]: f32, [[W:%.+]]: f32, [[EXISTING:%.+]]: vector<4xf8E5M2FNUZ>)95// CHECK: [[EXISTING_BYTES:%.+]] = builtin.unrealized_conversion_cast [[EXISTING]] : vector<4xf8E5M2FNUZ> to vector<4xi8>96// CHECK: [[EXISTING_INT:%.+]] = llvm.bitcast [[EXISTING_BYTES]] : vector<4xi8> to i3297// CHECK: [[PACKED:%.+]] = rocdl.cvt.pk.bf8.f32 [[V]], [[W]] -> [[EXISTING_INT]][true] : i3298// CHECK: [[CAST:%.+]] = llvm.bitcast [[PACKED]] : i32 to vector<4xi8>99// CHECK: builtin.unrealized_conversion_cast [[CAST]] : vector<4xi8> to vector<4xf8E5M2FNUZ>100func.func @packed_truncx2_into(%v: f32, %w: f32, %existing: vector<4xf8E5M2FNUZ>) -> vector<4xf8E5M2FNUZ> {101 %ret = amdgpu.packed_trunc_2xfp8 %v, %w into %existing[word 1] : f32 to vector<4xf8E5M2FNUZ> into vector<4xf8E5M2FNUZ>102 func.return %ret : vector<4xf8E5M2FNUZ>103}104 105// CHECK-LABEL: func @packed_stoch_round106// CHECK-SAME: ([[V:%.+]]: f32, [[S:%.+]]: i32)107// CHECK: [[EXISTING:%.+]] = llvm.mlir.undef : i32108// CHECK: [[PACKED:%.+]] = rocdl.cvt.sr.fp8.f32 [[V]], [[S]] -> [[EXISTING]][0] : i32109// CHECK: [[CAST:%.+]] = llvm.bitcast [[PACKED]] : i32 to vector<4xi8>110// CHECK: builtin.unrealized_conversion_cast [[CAST]] : vector<4xi8> to vector<4xf8E4M3FNUZ>111func.func @packed_stoch_round(%v: f32, %s: i32) -> vector<4xf8E4M3FNUZ> {112 %ret = amdgpu.packed_stoch_round_fp8 %v + %s into undef[0] : f32 to vector<4xf8E4M3FNUZ>113 func.return %ret : vector<4xf8E4M3FNUZ>114}115 116// CHECK-LABEL: func @packed_stoch_round_into117// CHECK-SAME: ([[V:%.+]]: f32, [[S:%.+]]: i32, [[EXISTING:%.+]]: vector<4xf8E5M2FNUZ>)118// CHECK: [[EXISTING_BYTES:%.+]] = builtin.unrealized_conversion_cast [[EXISTING]] : vector<4xf8E5M2FNUZ> to vector<4xi8>119// CHECK: [[EXISTING_INT:%.+]] = llvm.bitcast [[EXISTING_BYTES]] : vector<4xi8> to i32120// CHECK: [[PACKED:%.+]] = rocdl.cvt.sr.bf8.f32 [[V]], [[S]] -> [[EXISTING_INT]][1] : i32121// CHECK: [[CAST:%.+]] = llvm.bitcast [[PACKED]] : i32 to vector<4xi8>122// CHECK: builtin.unrealized_conversion_cast [[CAST]] : vector<4xi8> to vector<4xf8E5M2FNUZ>123func.func @packed_stoch_round_into(%v: f32, %s: i32, %existing: vector<4xf8E5M2FNUZ>) -> vector<4xf8E5M2FNUZ> {124 %ret = amdgpu.packed_stoch_round_fp8 %v + %s into %existing[1] : f32 to vector<4xf8E5M2FNUZ> into vector<4xf8E5M2FNUZ>125 func.return %ret : vector<4xf8E5M2FNUZ>126}127