493 lines · plain
1// RUN: mlir-opt %s -convert-amdgpu-to-rocdl=chipset=gfx950 | FileCheck %s2 3// CHECK-LABEL: func.func @scaled_ext_full_f8e4m3_f324// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<4xf8E4M3FN> to vector<4xi8>5// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<4xi8> to i326// CHECK: rocdl.cvt.scalef32.pk.f32.fp8 [[BITCAST]][false], %arg1 : vector<2xf32>7func.func @scaled_ext_full_f8e4m3_f32(%v: vector<4xf8E4M3FN>, %scale: f32) -> vector<2xf32> {8 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<4xf8E4M3FN> to vector<2xf32>9 func.return %ret : vector<2xf32>10}11 12// CHECK-LABEL: func.func @scaled_ext_full_f8e4m3_f1613// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<4xf8E4M3FN> to vector<4xi8>14// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<4xi8> to i3215// CHECK: rocdl.cvt.scalef32.pk.f16.fp8 [[BITCAST]][false], %arg1 : vector<2xf16>16func.func @scaled_ext_full_f8e4m3_f16(%v: vector<4xf8E4M3FN>, %scale: f32) -> vector<2xf16> {17 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<4xf8E4M3FN> to vector<2xf16>18 func.return %ret : vector<2xf16>19}20 21// CHECK-LABEL: func.func @scaled_ext_full_f8e4m3_bf1622// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<4xf8E4M3FN> to vector<4xi8>23// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<4xi8> to i3224// CHECK: rocdl.cvt.scalef32.pk.bf16.fp8 [[BITCAST]][false], %arg1 : vector<2xbf16>25func.func @scaled_ext_full_f8e4m3_bf16(%v: vector<4xf8E4M3FN>, %scale: f32) -> vector<2xbf16> {26 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<4xf8E4M3FN> to vector<2xbf16>27 func.return %ret : vector<2xbf16>28}29 30// CHECK-LABEL: func.func @scaled_ext_half_f8e4m3_f3231// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E4M3FN> to vector<2xi8>32// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>33// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i3234// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>35// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>36// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i3237// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>38// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>39// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i3240// CHECK: rocdl.cvt.scalef32.pk.f32.fp8 [[BITCAST]][false], %arg1 : vector<2xf32>41func.func @scaled_ext_half_f8e4m3_f32(%v: vector<2xf8E4M3FN>, %scale: f32) -> vector<2xf32> {42 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E4M3FN> to vector<2xf32>43 func.return %ret : vector<2xf32>44}45 46// CHECK-LABEL: func.func @scaled_ext_half_f8e4m3_f1647// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E4M3FN> to vector<2xi8>48// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>49// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i3250// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>51// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>52// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i3253// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>54// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>55// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i3256// CHECK: rocdl.cvt.scalef32.pk.f16.fp8 [[BITCAST]][false], %arg1 : vector<2xf16>57func.func @scaled_ext_half_f8e4m3_f16(%v: vector<2xf8E4M3FN>, %scale: f32) -> vector<2xf16> {58 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E4M3FN> to vector<2xf16>59 func.return %ret : vector<2xf16>60}61 62// CHECK-LABEL: func.func @scaled_ext_half_f8e4m3_bf1663// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E4M3FN> to vector<2xi8>64// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>65// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i3266// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>67// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>68// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i3269// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>70// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>71// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i3272// CHECK: rocdl.cvt.scalef32.pk.bf16.fp8 [[BITCAST]][false], %arg1 : vector<2xbf16>73func.func @scaled_ext_half_f8e4m3_bf16(%v: vector<2xf8E4M3FN>, %scale: f32) -> vector<2xbf16> {74 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E4M3FN> to vector<2xbf16>75 func.return %ret : vector<2xbf16>76}77 78// CHECK-LABEL: func.func @scaled_ext_scalar_f8e4m3_f3279// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E4M3FN> to vector<2xi8>80// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>81// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i3282// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>83// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>84// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i3285// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>86// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>87// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i3288// CHECK: rocdl.cvt.scalef32.pk.f32.fp8 [[BITCAST]][false], %arg1 : vector<2xf32>89func.func @scaled_ext_scalar_f8e4m3_f32(%v: vector<2xf8E4M3FN>, %scale: f32) -> vector<2xf32> {90 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E4M3FN> to vector<2xf32>91 func.return %ret : vector<2xf32>92}93 94// CHECK-LABEL: func.func @scaled_ext_scalar_f8e4m3_f1695// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E4M3FN> to vector<2xi8>96// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>97// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i3298// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>99// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>100// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32101// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>102// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>103// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i32104// CHECK: rocdl.cvt.scalef32.pk.f16.fp8 [[BITCAST]][false], %arg1 : vector<2xf16>105func.func @scaled_ext_scalar_f8e4m3_f16(%v: vector<2xf8E4M3FN>, %scale: f32) -> vector<2xf16> {106 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E4M3FN> to vector<2xf16>107 func.return %ret : vector<2xf16>108}109 110// CHECK-LABEL: func.func @scaled_ext_scalar_f8e4m3_bf16111// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E4M3FN> to vector<2xi8>112// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>113// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32114// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>115// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>116// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32117// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>118// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>119// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i32120// CHECK: rocdl.cvt.scalef32.pk.bf16.fp8 [[BITCAST]][false], %arg1 : vector<2xbf16>121func.func @scaled_ext_scalar_f8e4m3_bf16(%v: vector<2xf8E4M3FN>, %scale: f32) -> vector<2xbf16> {122 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E4M3FN> to vector<2xbf16>123 func.return %ret : vector<2xbf16>124}125 126// CHECK-LABEL: func.func @scaled_ext_full_f8e5m2_f32127// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<4xf8E5M2> to vector<4xi8>128// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<4xi8> to i32129// CHECK: rocdl.cvt.scalef32.pk.f32.bf8 [[BITCAST]][false], %arg1 : vector<2xf32>130func.func @scaled_ext_full_f8e5m2_f32(%v: vector<4xf8E5M2>, %scale: f32) -> vector<2xf32> {131 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<4xf8E5M2> to vector<2xf32>132 func.return %ret : vector<2xf32>133}134 135// CHECK-LABEL: func.func @scaled_ext_full_f8e5m2_f16136// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<4xf8E5M2> to vector<4xi8>137// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<4xi8> to i32138// CHECK: rocdl.cvt.scalef32.pk.f16.bf8 [[BITCAST]][false], %arg1 : vector<2xf16>139func.func @scaled_ext_full_f8e5m2_f16(%v: vector<4xf8E5M2>, %scale: f32) -> vector<2xf16> {140 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<4xf8E5M2> to vector<2xf16>141 func.return %ret : vector<2xf16>142}143 144// CHECK-LABEL: func.func @scaled_ext_full_f8e5m2_bf16145// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<4xf8E5M2> to vector<4xi8>146// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<4xi8> to i32147// CHECK: rocdl.cvt.scalef32.pk.bf16.bf8 [[BITCAST]][false], %arg1 : vector<2xbf16>148func.func @scaled_ext_full_f8e5m2_bf16(%v: vector<4xf8E5M2>, %scale: f32) -> vector<2xbf16> {149 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<4xf8E5M2> to vector<2xbf16>150 func.return %ret : vector<2xbf16>151}152 153// CHECK-LABEL: func.func @scaled_ext_half_f8e5m2_f32154// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E5M2> to vector<2xi8>155// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>156// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32157// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>158// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>159// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32160// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>161// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>162// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i32163// CHECK: rocdl.cvt.scalef32.pk.f32.bf8 [[BITCAST]][false], %arg1 : vector<2xf32>164func.func @scaled_ext_half_f8e5m2_f32(%v: vector<2xf8E5M2>, %scale: f32) -> vector<2xf32> {165 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E5M2> to vector<2xf32>166 func.return %ret : vector<2xf32>167}168 169// CHECK-LABEL: func.func @scaled_ext_half_f8e5m2_f16170// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E5M2> to vector<2xi8>171// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>172// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32173// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>174// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>175// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32176// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>177// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>178// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i32179// CHECK: rocdl.cvt.scalef32.pk.f16.bf8 [[BITCAST]][false], %arg1 : vector<2xf16>180func.func @scaled_ext_half_f8e5m2_f16(%v: vector<2xf8E5M2>, %scale: f32) -> vector<2xf16> {181 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E5M2> to vector<2xf16>182 func.return %ret : vector<2xf16>183}184 185// CHECK-LABEL: func.func @scaled_ext_half_f8e5m2_bf16186// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E5M2> to vector<2xi8>187// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>188// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32189// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>190// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>191// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32192// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>193// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>194// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i32195// CHECK: rocdl.cvt.scalef32.pk.bf16.bf8 [[BITCAST]][false], %arg1 : vector<2xbf16>196func.func @scaled_ext_half_f8e5m2_bf16(%v: vector<2xf8E5M2>, %scale: f32) -> vector<2xbf16> {197 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E5M2> to vector<2xbf16>198 func.return %ret : vector<2xbf16>199}200 201// CHECK-LABEL: func.func @scaled_ext_scalar_f8e5m2_f32202// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E5M2> to vector<2xi8>203// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>204// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32205// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>206// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>207// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32208// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>209// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>210// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i32211// CHECK: rocdl.cvt.scalef32.pk.f32.bf8 [[BITCAST]][false], %arg1 : vector<2xf32>212func.func @scaled_ext_scalar_f8e5m2_f32(%v: vector<2xf8E5M2>, %scale: f32) -> vector<2xf32> {213 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E5M2> to vector<2xf32>214 func.return %ret : vector<2xf32>215}216 217// CHECK-LABEL: func.func @scaled_ext_scalar_f8e5m2_f16218// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E5M2> to vector<2xi8>219// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>220// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32221// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>222// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>223// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32224// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>225// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>226// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i32227// CHECK: rocdl.cvt.scalef32.pk.f16.bf8 [[BITCAST]][false], %arg1 : vector<2xf16>228func.func @scaled_ext_scalar_f8e5m2_f16(%v: vector<2xf8E5M2>, %scale: f32) -> vector<2xf16> {229 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E5M2> to vector<2xf16>230 func.return %ret : vector<2xf16>231}232 233// CHECK-LABEL: func.func @scaled_ext_scalar_f8e5m2_bf16234// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf8E5M2> to vector<2xi8>235// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>236// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32237// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi8>238// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>239// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32240// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi8>241// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<4xi8>242// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<4xi8> to i32243// CHECK: rocdl.cvt.scalef32.pk.bf16.bf8 [[BITCAST]][false], %arg1 : vector<2xbf16>244func.func @scaled_ext_scalar_f8e5m2_bf16(%v: vector<2xf8E5M2>, %scale: f32) -> vector<2xbf16> {245 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf8E5M2> to vector<2xbf16>246 func.return %ret : vector<2xbf16>247}248 249// CHECK-LABEL: func.func @scaled_ext_full_f4e2m1_f32250// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<8xf4E2M1FN> to vector<8xi4>251// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<8xi4> to i32252// CHECK: rocdl.cvt.scalef32.pk.f32.fp4 [[BITCAST]][0], %arg1 : vector<2xf32>253func.func @scaled_ext_full_f4e2m1_f32(%v: vector<8xf4E2M1FN>, %scale: f32) -> vector<2xf32> {254 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<8xf4E2M1FN> to vector<2xf32>255 func.return %ret : vector<2xf32>256}257 258// CHECK-LABEL: func.func @scaled_ext_full_f4e2m1_f16259// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<8xf4E2M1FN> to vector<8xi4>260// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<8xi4> to i32261// CHECK: rocdl.cvt.scalef32.pk.f16.fp4 [[BITCAST]][0], %arg1 : vector<2xf16>262func.func @scaled_ext_full_f4e2m1_f16(%v: vector<8xf4E2M1FN>, %scale: f32) -> vector<2xf16> {263 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<8xf4E2M1FN> to vector<2xf16>264 func.return %ret : vector<2xf16>265}266 267// CHECK-LABEL: func.func @scaled_ext_full_f4e2m1_bf16268// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<8xf4E2M1FN> to vector<8xi4>269// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<8xi4> to i32270// CHECK: rocdl.cvt.scalef32.pk.bf16.fp4 [[BITCAST]][0], %arg1 : vector<2xbf16>271func.func @scaled_ext_full_f4e2m1_bf16(%v: vector<8xf4E2M1FN>, %scale: f32) -> vector<2xbf16> {272 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<8xf4E2M1FN> to vector<2xbf16>273 func.return %ret : vector<2xbf16>274}275 276// CHECK-LABEL: func.func @scaled_ext_half_f4e2m1_f32277// CHECK-DAG: [[CAST:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<8xf4E2M1FN> to vector<8xi4>278// CHECK-DAG: [[BITCAST:%.+]] = llvm.bitcast [[CAST]] : vector<8xi4> to i32279// CHECK: rocdl.cvt.scalef32.pk.f32.fp4 [[BITCAST]][0], %arg1 : vector<2xf32>280func.func @scaled_ext_half_f4e2m1_f32(%v: vector<8xf4E2M1FN>, %scale: f32) -> vector<2xf32> {281 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<8xf4E2M1FN> to vector<2xf32>282 func.return %ret : vector<2xf32>283}284 285// CHECK-LABEL: func.func @scaled_ext_half_f4e2m1_f16286// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<4xf4E2M1FN> to vector<4xi4>287// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<8xi4>288// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32289// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<4xi4>290// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<8xi4>291// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32292// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<4xi4>293// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<8xi4>294// CHECK-DAG: [[C2:%.+]] = llvm.mlir.constant(2 : i32) : i32295// CHECK: [[ELEM_2:%.+]] = llvm.extractelement [[V]]{{\[}}[[C2]] : i32] : vector<4xi4>296// CHECK: [[VEC_2:%.+]] = llvm.insertelement [[ELEM_2]], [[VEC_1]]{{\[}}[[C2]] : i32] : vector<8xi4>297// CHECK-DAG: [[C3:%.+]] = llvm.mlir.constant(3 : i32) : i32298// CHECK: [[ELEM_3:%.+]] = llvm.extractelement [[V]]{{\[}}[[C3]] : i32] : vector<4xi4>299// CHECK: [[VEC_3:%.+]] = llvm.insertelement [[ELEM_3]], [[VEC_2]]{{\[}}[[C3]] : i32] : vector<8xi4>300// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_3]] : vector<8xi4> to i32301// CHECK: rocdl.cvt.scalef32.pk.f16.fp4 [[BITCAST]][0], %arg1 : vector<2xf16>302func.func @scaled_ext_half_f4e2m1_f16(%v: vector<4xf4E2M1FN>, %scale: f32) -> vector<2xf16> {303 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<4xf4E2M1FN> to vector<2xf16>304 func.return %ret : vector<2xf16>305}306 307// CHECK-LABEL: func.func @scaled_ext_half_f4e2m1_bf16308// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<4xf4E2M1FN> to vector<4xi4>309// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<8xi4>310// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32311// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<4xi4>312// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<8xi4>313// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32314// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<4xi4>315// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<8xi4>316// CHECK-DAG: [[C2:%.+]] = llvm.mlir.constant(2 : i32) : i32317// CHECK: [[ELEM_2:%.+]] = llvm.extractelement [[V]]{{\[}}[[C2]] : i32] : vector<4xi4>318// CHECK: [[VEC_2:%.+]] = llvm.insertelement [[ELEM_2]], [[VEC_1]]{{\[}}[[C2]] : i32] : vector<8xi4>319// CHECK-DAG: [[C3:%.+]] = llvm.mlir.constant(3 : i32) : i32320// CHECK: [[ELEM_3:%.+]] = llvm.extractelement [[V]]{{\[}}[[C3]] : i32] : vector<4xi4>321// CHECK: [[VEC_3:%.+]] = llvm.insertelement [[ELEM_3]], [[VEC_2]]{{\[}}[[C3]] : i32] : vector<8xi4>322// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_3]] : vector<8xi4> to i32323// CHECK: rocdl.cvt.scalef32.pk.bf16.fp4 [[BITCAST]][0], %arg1 : vector<2xbf16>324func.func @scaled_ext_half_f4e2m1_bf16(%v: vector<4xf4E2M1FN>, %scale: f32) -> vector<2xbf16> {325 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<4xf4E2M1FN> to vector<2xbf16>326 func.return %ret : vector<2xbf16>327}328 329// CHECK-LABEL: func.func @scaled_ext_scalar_f4e2m1_f32330// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf4E2M1FN> to vector<2xi4>331// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<8xi4>332// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32333// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi4>334// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<8xi4>335// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32336// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi4>337// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<8xi4>338// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<8xi4> to i32339// CHECK: rocdl.cvt.scalef32.pk.f32.fp4 [[BITCAST]][0], %arg1 : vector<2xf32>340func.func @scaled_ext_scalar_f4e2m1_f32(%v: vector<2xf4E2M1FN>, %scale: f32) -> vector<2xf32> {341 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf4E2M1FN> to vector<2xf32>342 func.return %ret : vector<2xf32>343}344 345// CHECK-LABEL: func.func @scaled_ext_scalar_f4e2m1_f16346// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf4E2M1FN> to vector<2xi4>347// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<8xi4>348// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32349// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi4>350// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<8xi4>351// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32352// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi4>353// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<8xi4>354// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<8xi4> to i32355// CHECK: rocdl.cvt.scalef32.pk.f16.fp4 [[BITCAST]][0], %arg1 : vector<2xf16>356func.func @scaled_ext_scalar_f4e2m1_f16(%v: vector<2xf4E2M1FN>, %scale: f32) -> vector<2xf16> {357 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf4E2M1FN> to vector<2xf16>358 func.return %ret : vector<2xf16>359}360 361// CHECK-LABEL: func.func @scaled_ext_scalar_f4e2m1_bf16362// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<2xf4E2M1FN> to vector<2xi4>363// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<8xi4>364// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32365// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<2xi4>366// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<8xi4>367// CHECK-DAG: [[C1:%.+]] = llvm.mlir.constant(1 : i32) : i32368// CHECK: [[ELEM_1:%.+]] = llvm.extractelement [[V]]{{\[}}[[C1]] : i32] : vector<2xi4>369// CHECK: [[VEC_1:%.+]] = llvm.insertelement [[ELEM_1]], [[VEC_0]]{{\[}}[[C1]] : i32] : vector<8xi4>370// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_1]] : vector<8xi4> to i32371// CHECK: rocdl.cvt.scalef32.pk.bf16.fp4 [[BITCAST]][0], %arg1 : vector<2xbf16>372func.func @scaled_ext_scalar_f4e2m1_bf16(%v: vector<2xf4E2M1FN>, %scale: f32) -> vector<2xbf16> {373 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<2xf4E2M1FN> to vector<2xbf16>374 func.return %ret : vector<2xbf16>375}376 377// CHECK-LABEL: func.func @scaled_ext_one_f8e4m3_f32378// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf8E4M3FN> to vector<1xi8>379// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>380// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32381// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi8>382// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>383// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<4xi8> to i32384// CHECK: rocdl.cvt.scalef32.pk.f32.fp8 [[BITCAST]][false], %arg1 : vector<2xf32>385func.func @scaled_ext_one_f8e4m3_f32(%v: vector<1xf8E4M3FN>, %scale: f32) -> vector<2xf32> {386 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf8E4M3FN> to vector<2xf32>387 func.return %ret : vector<2xf32>388}389 390// CHECK-LABEL: func.func @scaled_ext_one_f8e4m3_f16391// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf8E4M3FN> to vector<1xi8>392// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>393// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32394// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi8>395// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>396// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<4xi8> to i32397// CHECK: rocdl.cvt.scalef32.pk.f16.fp8 [[BITCAST]][false], %arg1 : vector<2xf16>398func.func @scaled_ext_one_f8e4m3_f16(%v: vector<1xf8E4M3FN>, %scale: f32) -> vector<2xf16> {399 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf8E4M3FN> to vector<2xf16>400 func.return %ret : vector<2xf16>401}402 403// CHECK-LABEL: func.func @scaled_ext_one_f8e4m3_bf16404// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf8E4M3FN> to vector<1xi8>405// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>406// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32407// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi8>408// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>409// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<4xi8> to i32410// CHECK: rocdl.cvt.scalef32.pk.bf16.fp8 [[BITCAST]][false], %arg1 : vector<2xbf16>411func.func @scaled_ext_one_f8e4m3_bf16(%v: vector<1xf8E4M3FN>, %scale: f32) -> vector<2xbf16> {412 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf8E4M3FN> to vector<2xbf16>413 func.return %ret : vector<2xbf16>414}415 416// CHECK-LABEL: func.func @scaled_ext_one_f8e5m2_f32417// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf8E5M2> to vector<1xi8>418// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>419// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32420// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi8>421// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>422// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<4xi8> to i32423// CHECK: rocdl.cvt.scalef32.pk.f32.bf8 [[BITCAST]][false], %arg1 : vector<2xf32>424func.func @scaled_ext_one_f8e5m2_f32(%v: vector<1xf8E5M2>, %scale: f32) -> vector<2xf32> {425 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf8E5M2> to vector<2xf32>426 func.return %ret : vector<2xf32>427}428 429// CHECK-LABEL: func.func @scaled_ext_one_f8e5m2_f16430// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf8E5M2> to vector<1xi8>431// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>432// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32433// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi8>434// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>435// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<4xi8> to i32436// CHECK: rocdl.cvt.scalef32.pk.f16.bf8 [[BITCAST]][false], %arg1 : vector<2xf16>437func.func @scaled_ext_one_f8e5m2_f16(%v: vector<1xf8E5M2>, %scale: f32) -> vector<2xf16> {438 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf8E5M2> to vector<2xf16>439 func.return %ret : vector<2xf16>440}441 442// CHECK-LABEL: func.func @scaled_ext_one_f8e5m2_bf16443// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf8E5M2> to vector<1xi8>444// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<4xi8>445// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32446// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi8>447// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<4xi8>448// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<4xi8> to i32449// CHECK: rocdl.cvt.scalef32.pk.bf16.bf8 [[BITCAST]][false], %arg1 : vector<2xbf16>450func.func @scaled_ext_one_f8e5m2_bf16(%v: vector<1xf8E5M2>, %scale: f32) -> vector<2xbf16> {451 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf8E5M2> to vector<2xbf16>452 func.return %ret : vector<2xbf16>453}454 455// CHECK-LABEL: func.func @scaled_ext_one_f4e2m1_f32456// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf4E2M1FN> to vector<1xi4>457// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<8xi4>458// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32459// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi4>460// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<8xi4>461// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<8xi4> to i32462// CHECK: rocdl.cvt.scalef32.pk.f32.fp4 [[BITCAST]][0], %arg1 : vector<2xf32>463func.func @scaled_ext_one_f4e2m1_f32(%v: vector<1xf4E2M1FN>, %scale: f32) -> vector<2xf32> {464 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf4E2M1FN> to vector<2xf32>465 func.return %ret : vector<2xf32>466}467 468// CHECK-LABEL: func.func @scaled_ext_one_f4e2m1_f16469// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf4E2M1FN> to vector<1xi4>470// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<8xi4>471// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32472// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi4>473// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<8xi4>474// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<8xi4> to i32475// CHECK: rocdl.cvt.scalef32.pk.f16.fp4 [[BITCAST]][0], %arg1 : vector<2xf16>476func.func @scaled_ext_one_f4e2m1_f16(%v: vector<1xf4E2M1FN>, %scale: f32) -> vector<2xf16> {477 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf4E2M1FN> to vector<2xf16>478 func.return %ret : vector<2xf16>479}480 481// CHECK-LABEL: func.func @scaled_ext_one_f4e2m1_bf16482// CHECK: [[V:%.+]] = builtin.unrealized_conversion_cast %arg0 : vector<1xf4E2M1FN> to vector<1xi4>483// CHECK-DAG: [[ZERO:%.+]] = llvm.mlir.zero : vector<8xi4>484// CHECK-DAG: [[C0:%.+]] = llvm.mlir.constant(0 : i32) : i32485// CHECK: [[ELEM_0:%.+]] = llvm.extractelement [[V]]{{\[}}[[C0]] : i32] : vector<1xi4>486// CHECK: [[VEC_0:%.+]] = llvm.insertelement [[ELEM_0]], [[ZERO]]{{\[}}[[C0]] : i32] : vector<8xi4>487// CHECK: [[BITCAST:%.+]] = llvm.bitcast [[VEC_0]] : vector<8xi4> to i32488// CHECK: rocdl.cvt.scalef32.pk.bf16.fp4 [[BITCAST]][0], %arg1 : vector<2xbf16>489func.func @scaled_ext_one_f4e2m1_bf16(%v: vector<1xf4E2M1FN>, %scale: f32) -> vector<2xbf16> {490 %ret = amdgpu.scaled_ext_packed %v[0], %scale : vector<1xf4E2M1FN> to vector<2xbf16>491 func.return %ret : vector<2xbf16>492}493