120 lines · plain
1// RUN: mlir-opt %s -gpu-module-to-binary="format=isa" \2// RUN: -debug-only=serialize-to-isa 2> %t 3// RUN: FileCheck --input-file=%t %s4// REQUIRES: asserts5//6// MathToXeVM pass generates OpenCL intrinsics function calls when converting7// Math ops with `fastmath` attr to native function calls. It is assumed that8// the SPIRV backend would correctly convert these intrinsics calls to OpenCL9// ExtInst instructions in SPIRV (See llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp).10//11// To ensure this assumption holds, this test verifies that the SPIRV backend12// behaves as expected.13 14module @test_ocl_intrinsics attributes {gpu.container_module} {15 gpu.module @kernel [#xevm.target] {16 llvm.func spir_kernelcc @native_fcns() attributes {gpu.kernel} {17 // CHECK-DAG: %[[F16T:.+]] = OpTypeFloat 1618 // CHECK-DAG: %[[ZERO_F16:.+]] = OpConstantNull %[[F16T]]19 %c0_f16 = llvm.mlir.constant(0. : f16) : f1620 // CHECK-DAG: %[[F32T:.+]] = OpTypeFloat 3221 // CHECK-DAG: %[[ZERO_F32:.+]] = OpConstantNull %[[F32T]]22 %c0_f32 = llvm.mlir.constant(0. : f32) : f3223 // CHECK-DAG: %[[F64T:.+]] = OpTypeFloat 6424 // CHECK-DAG: %[[ZERO_F64:.+]] = OpConstantNull %[[F64T]]25 %c0_f64 = llvm.mlir.constant(0. : f64) : f6426 27 // CHECK-DAG: %[[V2F64T:.+]] = OpTypeVector %[[F64T]] 228 // CHECK-DAG: %[[V2_ZERO_F64:.+]] = OpConstantNull %[[V2F64T]]29 %v2_c0_f64 = llvm.mlir.constant(dense<0.> : vector<2xf64>) : vector<2xf64>30 // CHECK-DAG: %[[V3F32T:.+]] = OpTypeVector %[[F32T]] 331 // CHECK-DAG: %[[V3_ZERO_F32:.+]] = OpConstantNull %[[V3F32T]]32 %v3_c0_f32 = llvm.mlir.constant(dense<0.> : vector<3xf32>) : vector<3xf32>33 // CHECK-DAG: %[[V4F64T:.+]] = OpTypeVector %[[F64T]] 434 // CHECK-DAG: %[[V4_ZERO_F64:.+]] = OpConstantNull %[[V4F64T]]35 %v4_c0_f64 = llvm.mlir.constant(dense<0.> : vector<4xf64>) : vector<4xf64>36 // CHECK-DAG: %[[V8F64T:.+]] = OpTypeVector %[[F64T]] 837 // CHECK-DAG: %[[V8_ZERO_F64:.+]] = OpConstantNull %[[V8F64T]]38 %v8_c0_f64 = llvm.mlir.constant(dense<0.> : vector<8xf64>) : vector<8xf64>39 // CHECK-DAG: %[[V16F16T:.+]] = OpTypeVector %[[F16T]] 1640 // CHECK-DAG: %[[V16_ZERO_F16:.+]] = OpConstantNull %[[V16F16T]]41 %v16_c0_f16 = llvm.mlir.constant(dense<0.> : vector<16xf16>) : vector<16xf16> 42 43 // CHECK: OpExtInst %[[F16T]] %{{.+}} native_exp %[[ZERO_F16]]44 %exp_f16 = llvm.call @_Z22__spirv_ocl_native_expDh(%c0_f16) : (f16) -> f1645 // CHECK: OpExtInst %[[F32T]] %{{.+}} native_exp %[[ZERO_F32]]46 %exp_f32 = llvm.call @_Z22__spirv_ocl_native_expf(%c0_f32) : (f32) -> f3247 // CHECK: OpExtInst %[[F64T]] %{{.+}} native_exp %[[ZERO_F64]]48 %exp_f64 = llvm.call @_Z22__spirv_ocl_native_expd(%c0_f64) : (f64) -> f6449 50 // CHECK: OpExtInst %[[V2F64T]] %{{.+}} native_exp %[[V2_ZERO_F64]]51 %exp_v2_f64 = llvm.call @_Z22__spirv_ocl_native_expDv2_f64(%v2_c0_f64) : (vector<2xf64>) -> vector<2xf64>52 // CHECK: OpExtInst %[[V3F32T]] %{{.+}} native_exp %[[V3_ZERO_F32]]53 %exp_v3_f32 = llvm.call @_Z22__spirv_ocl_native_expDv3_f32(%v3_c0_f32) : (vector<3xf32>) -> vector<3xf32>54 // CHECK: OpExtInst %[[V4F64T]] %{{.+}} native_exp %[[V4_ZERO_F64]]55 %exp_v4_f64 = llvm.call @_Z22__spirv_ocl_native_expDv4_f64(%v4_c0_f64) : (vector<4xf64>) -> vector<4xf64>56 // CHECK: OpExtInst %[[V8F64T]] %{{.+}} native_exp %[[V8_ZERO_F64]]57 %exp_v8_f64 = llvm.call @_Z22__spirv_ocl_native_expDv8_f64(%v8_c0_f64) : (vector<8xf64>) -> vector<8xf64>58 // CHECK: OpExtInst %[[V16F16T]] %{{.+}} native_exp %[[V16_ZERO_F16]]59 %exp_v16_f16 = llvm.call @_Z22__spirv_ocl_native_expDv16_f16(%v16_c0_f16) : (vector<16xf16>) -> vector<16xf16>60 61 // SPIRV backend does not currently handle fastmath flags: The SPIRV62 // backend would need to generate OpDecorate calls to decorate math ops63 // with FPFastMathMode/FPFastMathModeINTEL decorations.64 //65 // FIXME: When support for fastmath flags in the SPIRV backend is added, 66 // add tests here to ensure fastmath flags are converted to the correct67 // OpDecorate calls.68 // 69 // See:70 // - https://registry.khronos.org/SPIR-V/specs/unified1/OpenCL.ExtendedInstructionSet.100.html#_math_extended_instructions71 // - https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpDecorate72 73 // CHECK: OpExtInst %[[F16T]] %{{.+}} native_cos %[[ZERO_F16]]74 %cos_afn_f16 = llvm.call @_Z22__spirv_ocl_native_cosDh(%c0_f16) {fastmathFlags = #llvm.fastmath<afn>} : (f16) -> f1675 // CHECK: OpExtInst %[[F32T]] %{{.+}} native_exp2 %[[ZERO_F32]]76 %exp2_afn_f32 = llvm.call @_Z23__spirv_ocl_native_exp2f(%c0_f32) {fastmathFlags = #llvm.fastmath<afn>} : (f32) -> f3277 // CHECK: OpExtInst %[[F16T]] %{{.+}} native_log %[[ZERO_F16]]78 %log_afn_f16 = llvm.call @_Z22__spirv_ocl_native_logDh(%c0_f16) {fastmathFlags = #llvm.fastmath<afn>} : (f16) -> f1679 // CHECK: OpExtInst %[[F32T]] %{{.+}} native_log2 %[[ZERO_F32]]80 %log2_afn_f32 = llvm.call @_Z23__spirv_ocl_native_log2f(%c0_f32) {fastmathFlags = #llvm.fastmath<afn>} : (f32) -> f3281 // CHECK: OpExtInst %[[V8F64T]] %{{.+}} native_log10 %[[V8_ZERO_F64]]82 %log10_afn_f64 = llvm.call @_Z24__spirv_ocl_native_log10Dv8_d(%v8_c0_f64) {fastmathFlags = #llvm.fastmath<afn>} : (vector<8xf64>) -> vector<8xf64>83 // CHECK: OpExtInst %[[V16F16T]] %{{.+}} native_powr %[[V16_ZERO_F16]] %[[V16_ZERO_F16]]84 %powr_afn_f16 = llvm.call @_Z23__spirv_ocl_native_powrDv16_DhS_(%v16_c0_f16, %v16_c0_f16) {fastmathFlags = #llvm.fastmath<afn>} : (vector<16xf16>, vector<16xf16>) -> vector<16xf16>85 // CHECK: OpExtInst %[[F64T]] %{{.+}} native_rsqrt %[[ZERO_F64]]86 %rsqrt_afn_f64 = llvm.call @_Z24__spirv_ocl_native_rsqrtd(%c0_f64) {fastmathFlags = #llvm.fastmath<afn>} : (f64) -> f6487 // CHECK: OpExtInst %[[F16T]] %{{.+}} native_sin %[[ZERO_F16]]88 %sin_afn_f16 = llvm.call @_Z22__spirv_ocl_native_sinDh(%c0_f16) {fastmathFlags = #llvm.fastmath<afn>} : (f16) -> f1689 // CHECK: OpExtInst %[[F32T]] %{{.+}} native_sqrt %[[ZERO_F32]]90 %sqrt_afn_f32 = llvm.call @_Z23__spirv_ocl_native_sqrtf(%c0_f32) {fastmathFlags = #llvm.fastmath<afn>} : (f32) -> f3291 // CHECK: OpExtInst %[[F64T]] %{{.+}} native_tan %[[ZERO_F64]]92 %tan_afn_f64 = llvm.call @_Z22__spirv_ocl_native_tand(%c0_f64) {fastmathFlags = #llvm.fastmath<afn>} : (f64) -> f6493 // CHECK: OpExtInst %[[F32T]] %{{.+}} native_divide %[[ZERO_F32]] %[[ZERO_F32]]94 %divide_afn_f32 = llvm.call @_Z25__spirv_ocl_native_divideff(%c0_f32, %c0_f32) {fastmathFlags = #llvm.fastmath<afn>} : (f32, f32) -> f3295 96 llvm.return97 }98 99 llvm.func @_Z22__spirv_ocl_native_expDh(f16) -> f16100 llvm.func @_Z22__spirv_ocl_native_expf(f32) -> f32101 llvm.func @_Z22__spirv_ocl_native_expd(f64) -> f64102 llvm.func @_Z22__spirv_ocl_native_expDv2_f64(vector<2xf64>) -> vector<2xf64>103 llvm.func @_Z22__spirv_ocl_native_expDv3_f32(vector<3xf32>) -> vector<3xf32>104 llvm.func @_Z22__spirv_ocl_native_expDv4_f64(vector<4xf64>) -> vector<4xf64>105 llvm.func @_Z22__spirv_ocl_native_expDv8_f64(vector<8xf64>) -> vector<8xf64>106 llvm.func @_Z22__spirv_ocl_native_expDv16_f16(vector<16xf16>) -> vector<16xf16>107 llvm.func @_Z22__spirv_ocl_native_cosDh(f16) -> f16108 llvm.func @_Z23__spirv_ocl_native_exp2f(f32) -> f32109 llvm.func @_Z22__spirv_ocl_native_logDh(f16) -> f16110 llvm.func @_Z23__spirv_ocl_native_log2f(f32) -> f32111 llvm.func @_Z24__spirv_ocl_native_log10Dv8_d(vector<8xf64>) -> vector<8xf64>112 llvm.func @_Z23__spirv_ocl_native_powrDv16_DhS_(vector<16xf16>, vector<16xf16>) -> vector<16xf16>113 llvm.func @_Z24__spirv_ocl_native_rsqrtd(f64) -> f64114 llvm.func @_Z22__spirv_ocl_native_sinDh(f16) -> f16115 llvm.func @_Z23__spirv_ocl_native_sqrtf(f32) -> f32116 llvm.func @_Z22__spirv_ocl_native_tand(f64) -> f64117 llvm.func @_Z25__spirv_ocl_native_divideff(f32, f32) -> f32118 }119}120