283 lines · plain
1// RUN: mlir-opt -split-input-file -convert-memref-to-spirv="bool-num-bits=8" -cse %s -o - | FileCheck %s2// RUN: mlir-opt -split-input-file -convert-memref-to-spirv="bool-num-bits=8 use-64bit-index" -cse %s -o - | FileCheck %s --check-prefix=INDEX643 4// Check that access chain indices are properly adjusted if non-32-bit types are5// emulated via 32-bit types.6// TODO: Test i64 types.7module attributes {8 spirv.target_env = #spirv.target_env<9 #spirv.vce<v1.0, [Shader, Int64], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>10} {11 12// CHECK-LABEL: @load_i113func.func @load_i1(%arg0: memref<i1, #spirv.storage_class<StorageBuffer>>) -> i1 {14 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i3215 // CHECK: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[ZERO]]]16 // CHECK: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %[[PTR]]17 // CHECK: %[[MASK:.+]] = spirv.Constant 255 : i3218 // CHECK: %[[T1:.+]] = spirv.BitwiseAnd %[[LOAD]], %[[MASK]] : i3219 // CHECK: %[[T2:.+]] = spirv.Constant 24 : i3220 // CHECK: %[[T3:.+]] = spirv.ShiftLeftLogical %[[T1]], %[[T2]] : i32, i3221 // CHECK: %[[T4:.+]] = spirv.ShiftRightArithmetic %[[T3]], %[[T2]] : i32, i3222 // Convert to i1 type.23 // CHECK: %[[ONE:.+]] = spirv.Constant 1 : i3224 // CHECK: %[[RES:.+]] = spirv.IEqual %[[T4]], %[[ONE]] : i3225 // CHECK: return %[[RES]]26 %0 = memref.load %arg0[] : memref<i1, #spirv.storage_class<StorageBuffer>>27 return %0 : i128}29 30// CHECK-LABEL: @load_i831// INDEX64-LABEL: @load_i832func.func @load_i8(%arg0: memref<i8, #spirv.storage_class<StorageBuffer>>) -> i8 {33 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i3234 // CHECK: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[ZERO]]]35 // CHECK: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %[[PTR]]36 // CHECK: %[[MASK:.+]] = spirv.Constant 255 : i3237 // CHECK: %[[T1:.+]] = spirv.BitwiseAnd %[[LOAD]], %[[MASK]] : i3238 // CHECK: %[[T2:.+]] = spirv.Constant 24 : i3239 // CHECK: %[[T3:.+]] = spirv.ShiftLeftLogical %[[T1]], %[[T2]] : i32, i3240 // CHECK: %[[SR:.+]] = spirv.ShiftRightArithmetic %[[T3]], %[[T2]] : i32, i3241 // CHECK: builtin.unrealized_conversion_cast %[[SR]]42 43 // INDEX64: %[[ZERO:.+]] = spirv.Constant 0 : i6444 // INDEX64: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[ZERO]]] : {{.+}}, i64, i6445 // INDEX64: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %[[PTR]] : i3246 // INDEX64: %[[MASK:.+]] = spirv.Constant 255 : i3247 // INDEX64: %[[T1:.+]] = spirv.BitwiseAnd %[[LOAD]], %[[MASK]] : i3248 // INDEX64: %[[T2:.+]] = spirv.Constant 24 : i3249 // INDEX64: %[[T3:.+]] = spirv.ShiftLeftLogical %[[T1]], %[[T2]] : i32, i3250 // INDEX64: %[[SR:.+]] = spirv.ShiftRightArithmetic %[[T3]], %[[T2]] : i32, i3251 // INDEX64: builtin.unrealized_conversion_cast %[[SR]]52 %0 = memref.load %arg0[] : memref<i8, #spirv.storage_class<StorageBuffer>>53 return %0 : i854}55 56// CHECK-LABEL: @load_i1657// CHECK: (%[[ARG0:.+]]: {{.*}}, %[[ARG1:.+]]: index)58func.func @load_i16(%arg0: memref<10xi16, #spirv.storage_class<StorageBuffer>>, %index : index) -> i16 {59 // CHECK: %[[ARG1_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG1]] : index to i3260 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i3261 // CHECK: %[[TWO:.+]] = spirv.Constant 2 : i3262 // CHECK: %[[QUOTIENT:.+]] = spirv.SDiv %[[ARG1_CAST]], %[[TWO]] : i3263 // CHECK: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[QUOTIENT]]]64 // CHECK: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %[[PTR]]65 // CHECK: %[[SIXTEEN:.+]] = spirv.Constant 16 : i3266 // CHECK: %[[IDX:.+]] = spirv.UMod %[[ARG1_CAST]], %[[TWO]] : i3267 // CHECK: %[[BITS:.+]] = spirv.IMul %[[IDX]], %[[SIXTEEN]] : i3268 // CHECK: %[[VALUE:.+]] = spirv.ShiftRightArithmetic %[[LOAD]], %[[BITS]] : i32, i3269 // CHECK: %[[MASK:.+]] = spirv.Constant 65535 : i3270 // CHECK: %[[T1:.+]] = spirv.BitwiseAnd %[[VALUE]], %[[MASK]] : i3271 // CHECK: %[[T3:.+]] = spirv.ShiftLeftLogical %[[T1]], %[[SIXTEEN]] : i32, i3272 // CHECK: %[[SR:.+]] = spirv.ShiftRightArithmetic %[[T3]], %[[SIXTEEN]] : i32, i3273 // CHECK: builtin.unrealized_conversion_cast %[[SR]]74 %0 = memref.load %arg0[%index] : memref<10xi16, #spirv.storage_class<StorageBuffer>>75 return %0: i1676}77 78// CHECK-LABEL: @load_f3279func.func @load_f32(%arg0: memref<f32, #spirv.storage_class<StorageBuffer>>) {80 // CHECK-NOT: spirv.SDiv81 // CHECK: spirv.Load82 // CHECK-NOT: spirv.ShiftRightArithmetic83 %0 = memref.load %arg0[] : memref<f32, #spirv.storage_class<StorageBuffer>>84 return85}86 87// CHECK-LABEL: @store_i188// CHECK: (%[[ARG0:.+]]: {{.*}}, %[[ARG1:.+]]: i1)89func.func @store_i1(%arg0: memref<i1, #spirv.storage_class<StorageBuffer>>, %value: i1) {90 // CHECK: %[[ARG0_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG0]]91 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i3292 // CHECK: %[[MASK:.+]] = spirv.Constant -256 : i3293 // CHECK: %[[ONE:.+]] = spirv.Constant 1 : i3294 // CHECK: %[[CASTED_ARG1:.+]] = spirv.Select %[[ARG1]], %[[ONE]], %[[ZERO]] : i1, i3295 // CHECK: %[[PTR:.+]] = spirv.AccessChain %[[ARG0_CAST]][%[[ZERO]], %[[ZERO]]]96 // CHECK: spirv.AtomicAnd <Device> <AcquireRelease> %[[PTR]], %[[MASK]]97 // CHECK: spirv.AtomicOr <Device> <AcquireRelease> %[[PTR]], %[[CASTED_ARG1]]98 memref.store %value, %arg0[] : memref<i1, #spirv.storage_class<StorageBuffer>>99 return100}101 102// CHECK-LABEL: @store_i8103// CHECK: (%[[ARG0:.+]]: {{.*}}, %[[ARG1:.+]]: i8)104// INDEX64-LABEL: @store_i8105// INDEX64: (%[[ARG0:.+]]: {{.*}}, %[[ARG1:.+]]: i8)106func.func @store_i8(%arg0: memref<i8, #spirv.storage_class<StorageBuffer>>, %value: i8) {107 // CHECK-DAG: %[[ARG1_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG1]] : i8 to i32108 // CHECK-DAG: %[[ARG0_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG0]]109 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i32110 // CHECK: %[[MASK1:.+]] = spirv.Constant 255 : i32111 // CHECK: %[[MASK2:.+]] = spirv.Constant -256 : i32112 // CHECK: %[[CLAMPED_VAL:.+]] = spirv.BitwiseAnd %[[ARG1_CAST]], %[[MASK1]] : i32113 // CHECK: %[[PTR:.+]] = spirv.AccessChain %[[ARG0_CAST]][%[[ZERO]], %[[ZERO]]]114 // CHECK: spirv.AtomicAnd <Device> <AcquireRelease> %[[PTR]], %[[MASK2]]115 // CHECK: spirv.AtomicOr <Device> <AcquireRelease> %[[PTR]], %[[CLAMPED_VAL]]116 117 // INDEX64-DAG: %[[ARG1_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG1]] : i8 to i32118 // INDEX64-DAG: %[[ARG0_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG0]]119 // INDEX64: %[[ZERO:.+]] = spirv.Constant 0 : i64120 // INDEX64: %[[MASK1:.+]] = spirv.Constant 255 : i32121 // INDEX64: %[[MASK2:.+]] = spirv.Constant -256 : i32122 // INDEX64: %[[CLAMPED_VAL:.+]] = spirv.BitwiseAnd %[[ARG1_CAST]], %[[MASK1]] : i32123 // INDEX64: %[[PTR:.+]] = spirv.AccessChain %[[ARG0_CAST]][%[[ZERO]], %[[ZERO]]] : {{.+}}, i64, i64124 // INDEX64: spirv.AtomicAnd <Device> <AcquireRelease> %[[PTR]], %[[MASK2]]125 // INDEX64: spirv.AtomicOr <Device> <AcquireRelease> %[[PTR]], %[[CLAMPED_VAL]]126 memref.store %value, %arg0[] : memref<i8, #spirv.storage_class<StorageBuffer>>127 return128}129 130// CHECK-LABEL: @store_i16131// CHECK: (%[[ARG0:.+]]: memref<10xi16, #spirv.storage_class<StorageBuffer>>, %[[ARG1:.+]]: index, %[[ARG2:.+]]: i16)132func.func @store_i16(%arg0: memref<10xi16, #spirv.storage_class<StorageBuffer>>, %index: index, %value: i16) {133 // CHECK-DAG: %[[ARG2_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG2]] : i16 to i32134 // CHECK-DAG: %[[ARG0_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG0]]135 // CHECK-DAG: %[[ARG1_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG1]] : index to i32136 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i32137 // CHECK: %[[TWO:.+]] = spirv.Constant 2 : i32138 // CHECK: %[[SIXTEEN:.+]] = spirv.Constant 16 : i32139 // CHECK: %[[IDX:.+]] = spirv.UMod %[[ARG1_CAST]], %[[TWO]] : i32140 // CHECK: %[[OFFSET:.+]] = spirv.IMul %[[IDX]], %[[SIXTEEN]] : i32141 // CHECK: %[[MASK1:.+]] = spirv.Constant 65535 : i32142 // CHECK: %[[TMP1:.+]] = spirv.ShiftLeftLogical %[[MASK1]], %[[OFFSET]] : i32, i32143 // CHECK: %[[MASK:.+]] = spirv.Not %[[TMP1]] : i32144 // CHECK: %[[CLAMPED_VAL:.+]] = spirv.BitwiseAnd %[[ARG2_CAST]], %[[MASK1]] : i32145 // CHECK: %[[STORE_VAL:.+]] = spirv.ShiftLeftLogical %[[CLAMPED_VAL]], %[[OFFSET]] : i32, i32146 // CHECK: %[[ACCESS_IDX:.+]] = spirv.SDiv %[[ARG1_CAST]], %[[TWO]] : i32147 // CHECK: %[[PTR:.+]] = spirv.AccessChain %[[ARG0_CAST]][%[[ZERO]], %[[ACCESS_IDX]]]148 // CHECK: spirv.AtomicAnd <Device> <AcquireRelease> %[[PTR]], %[[MASK]]149 // CHECK: spirv.AtomicOr <Device> <AcquireRelease> %[[PTR]], %[[STORE_VAL]]150 memref.store %value, %arg0[%index] : memref<10xi16, #spirv.storage_class<StorageBuffer>>151 return152}153 154// CHECK-LABEL: @store_f32155func.func @store_f32(%arg0: memref<f32, #spirv.storage_class<StorageBuffer>>, %value: f32) {156 // CHECK: spirv.Store157 // CHECK-NOT: spirv.AtomicAnd158 // CHECK-NOT: spirv.AtomicOr159 memref.store %value, %arg0[] : memref<f32, #spirv.storage_class<StorageBuffer>>160 return161}162 163} // end module164 165 166// -----167 168// Check that access chain indices are properly adjusted if sub-byte types are169// emulated via 32-bit types.170module attributes {171 spirv.target_env = #spirv.target_env<172 #spirv.vce<v1.0, [Shader, Int64], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>173} {174 175// CHECK-LABEL: @load_i4176func.func @load_i4(%arg0: memref<?xi4, #spirv.storage_class<StorageBuffer>>, %i: index) -> i4 {177 // CHECK: %[[INDEX:.+]] = builtin.unrealized_conversion_cast %{{.+}} : index to i32178 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i32179 // CHECK: %[[EIGHT:.+]] = spirv.Constant 8 : i32180 // CHECK: %[[QUOTIENT:.+]] = spirv.SDiv %[[INDEX]], %[[EIGHT]] : i32181 // CHECK: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[QUOTIENT]]]182 // CHECK: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %[[PTR]] : i32183 // CHECK: %[[FOUR:.+]] = spirv.Constant 4 : i32184 // CHECK: %[[IDX:.+]] = spirv.UMod %[[INDEX]], %[[EIGHT]] : i32185 // CHECK: %[[BITS:.+]] = spirv.IMul %[[IDX]], %[[FOUR]] : i32186 // CHECK: %[[VALUE:.+]] = spirv.ShiftRightArithmetic %[[LOAD]], %[[BITS]] : i32, i32187 // CHECK: %[[MASK:.+]] = spirv.Constant 15 : i32188 // CHECK: %[[AND:.+]] = spirv.BitwiseAnd %[[VALUE]], %[[MASK]] : i32189 // CHECK: %[[C28:.+]] = spirv.Constant 28 : i32190 // CHECK: %[[SL:.+]] = spirv.ShiftLeftLogical %[[AND]], %[[C28]] : i32, i32191 // CHECK: %[[SR:.+]] = spirv.ShiftRightArithmetic %[[SL]], %[[C28]] : i32, i32192 // CHECK: builtin.unrealized_conversion_cast %[[SR]]193 %0 = memref.load %arg0[%i] : memref<?xi4, #spirv.storage_class<StorageBuffer>>194 return %0 : i4195}196 197// CHECK-LABEL: @store_i4198func.func @store_i4(%arg0: memref<?xi4, #spirv.storage_class<StorageBuffer>>, %value: i4, %i: index) {199 // CHECK-DAG: %[[VAL:.+]] = builtin.unrealized_conversion_cast %{{.+}} : i4 to i32200 // CHECK-DAG: %[[INDEX:.+]] = builtin.unrealized_conversion_cast %{{.+}} : index to i32201 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i32202 // CHECK: %[[EIGHT:.+]] = spirv.Constant 8 : i32203 // CHECK: %[[FOUR:.+]] = spirv.Constant 4 : i32204 // CHECK: %[[IDX:.+]] = spirv.UMod %[[INDEX]], %[[EIGHT]] : i32205 // CHECK: %[[BITS:.+]] = spirv.IMul %[[IDX]], %[[FOUR]] : i32206 // CHECK: %[[MASK1:.+]] = spirv.Constant 15 : i32207 // CHECK: %[[SL:.+]] = spirv.ShiftLeftLogical %[[MASK1]], %[[BITS]] : i32, i32208 // CHECK: %[[MASK2:.+]] = spirv.Not %[[SL]] : i32209 // CHECK: %[[CLAMPED_VAL:.+]] = spirv.BitwiseAnd %[[VAL]], %[[MASK1]] : i32210 // CHECK: %[[STORE_VAL:.+]] = spirv.ShiftLeftLogical %[[CLAMPED_VAL]], %[[BITS]] : i32, i32211 // CHECK: %[[ACCESS_INDEX:.+]] = spirv.SDiv %[[INDEX]], %[[EIGHT]] : i32212 // CHECK: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[ACCESS_INDEX]]]213 // CHECK: spirv.AtomicAnd <Device> <AcquireRelease> %[[PTR]], %[[MASK2]]214 // CHECK: spirv.AtomicOr <Device> <AcquireRelease> %[[PTR]], %[[STORE_VAL]]215 memref.store %value, %arg0[%i] : memref<?xi4, #spirv.storage_class<StorageBuffer>>216 return217}218 219} // end module220 221// -----222 223// Check that we can access i8 storage with i8 types available but without224// 8-bit storage capabilities.225module attributes {226 spirv.target_env = #spirv.target_env<227 #spirv.vce<v1.0, [Shader, Int64, Int8], [SPV_KHR_storage_buffer_storage_class]>, #spirv.resource_limits<>>228} {229 230// CHECK-LABEL: @load_i8231// INDEX64-LABEL: @load_i8232func.func @load_i8(%arg0: memref<i8, #spirv.storage_class<StorageBuffer>>) -> i8 {233 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i32234 // CHECK: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[ZERO]]]235 // CHECK: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %[[PTR]]236 // CHECK: %[[MASK:.+]] = spirv.Constant 255 : i32237 // CHECK: %[[T1:.+]] = spirv.BitwiseAnd %[[LOAD]], %[[MASK]] : i32238 // CHECK: %[[T2:.+]] = spirv.Constant 24 : i32239 // CHECK: %[[T3:.+]] = spirv.ShiftLeftLogical %[[T1]], %[[T2]] : i32, i32240 // CHECK: %[[SR:.+]] = spirv.ShiftRightArithmetic %[[T3]], %[[T2]] : i32, i32241 // CHECK: %[[CAST:.+]] = spirv.UConvert %[[SR]] : i32 to i8242 // CHECK: return %[[CAST]] : i8243 244 // INDEX64: %[[ZERO:.+]] = spirv.Constant 0 : i64245 // INDEX64: %[[PTR:.+]] = spirv.AccessChain %{{.+}}[%[[ZERO]], %[[ZERO]]] : {{.+}}, i64, i64246 // INDEX64: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %[[PTR]] : i32247 // INDEX64: %[[MASK:.+]] = spirv.Constant 255 : i32248 // INDEX64: %[[T1:.+]] = spirv.BitwiseAnd %[[LOAD]], %[[MASK]] : i32249 // INDEX64: %[[T2:.+]] = spirv.Constant 24 : i32250 // INDEX64: %[[T3:.+]] = spirv.ShiftLeftLogical %[[T1]], %[[T2]] : i32, i32251 // INDEX64: %[[SR:.+]] = spirv.ShiftRightArithmetic %[[T3]], %[[T2]] : i32, i32252 // INDEX64: %[[CAST:.+]] = spirv.UConvert %[[SR]] : i32 to i8253 // INDEX64: return %[[CAST]] : i8254 %0 = memref.load %arg0[] : memref<i8, #spirv.storage_class<StorageBuffer>>255 return %0 : i8256}257 258// CHECK-LABEL: @store_i8259// CHECK: (%[[ARG0:.+]]: {{.*}}, %[[ARG1:.+]]: i8)260// INDEX64-LABEL: @store_i8261// INDEX64: (%[[ARG0:.+]]: {{.*}}, %[[ARG1:.+]]: i8)262func.func @store_i8(%arg0: memref<i8, #spirv.storage_class<StorageBuffer>>, %value: i8) {263 // CHECK-DAG: %[[ARG0_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG0]]264 // CHECK: %[[ZERO:.+]] = spirv.Constant 0 : i32265 // CHECK: %[[MASK1:.+]] = spirv.Constant -256 : i32266 // CHECK: %[[ARG1_CAST:.+]] = spirv.UConvert %[[ARG1]] : i8 to i32267 // CHECK: %[[PTR:.+]] = spirv.AccessChain %[[ARG0_CAST]][%[[ZERO]], %[[ZERO]]]268 // CHECK: spirv.AtomicAnd <Device> <AcquireRelease> %[[PTR]], %[[MASK1]]269 // CHECK: spirv.AtomicOr <Device> <AcquireRelease> %[[PTR]], %[[ARG1_CAST]]270 271 // INDEX64-DAG: %[[ARG0_CAST:.+]] = builtin.unrealized_conversion_cast %[[ARG0]]272 // INDEX64: %[[ZERO:.+]] = spirv.Constant 0 : i64273 // INDEX64: %[[MASK1:.+]] = spirv.Constant -256 : i32274 // INDEX64: %[[ARG1_CAST:.+]] = spirv.UConvert %[[ARG1]] : i8 to i32275 // INDEX64: %[[PTR:.+]] = spirv.AccessChain %[[ARG0_CAST]][%[[ZERO]], %[[ZERO]]] : {{.+}}, i64, i64276 // INDEX64: spirv.AtomicAnd <Device> <AcquireRelease> %[[PTR]], %[[MASK1]]277 // INDEX64: spirv.AtomicOr <Device> <AcquireRelease> %[[PTR]], %[[ARG1_CAST]]278 memref.store %value, %arg0[] : memref<i8, #spirv.storage_class<StorageBuffer>>279 return280}281 282} // end module283