122 lines · plain
1// RUN: mlir-opt -convert-spirv-to-llvm %s | FileCheck %s2 3//===----------------------------------------------------------------------===//4// spirv.ShiftRightArithmetic5//===----------------------------------------------------------------------===//6 7// CHECK-LABEL: @shift_right_arithmetic_scalar8spirv.func @shift_right_arithmetic_scalar(%arg0: i32, %arg1: si32, %arg2 : i16, %arg3 : ui16) "None" {9 // CHECK: llvm.ashr %{{.*}}, %{{.*}} : i3210 %0 = spirv.ShiftRightArithmetic %arg0, %arg0 : i32, i3211 12 // CHECK: llvm.ashr %{{.*}}, %{{.*}} : i3213 %1 = spirv.ShiftRightArithmetic %arg0, %arg1 : i32, si3214 15 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i3216 // CHECK: llvm.ashr %{{.*}}, %[[SEXT]] : i3217 %2 = spirv.ShiftRightArithmetic %arg0, %arg2 : i32, i1618 19 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i3220 // CHECK: llvm.ashr %{{.*}}, %[[ZEXT]] : i3221 %3 = spirv.ShiftRightArithmetic %arg0, %arg3 : i32, ui1622 spirv.Return23}24 25// CHECK-LABEL: @shift_right_arithmetic_vector26spirv.func @shift_right_arithmetic_vector(%arg0: vector<4xi64>, %arg1: vector<4xui64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" {27 // CHECK: llvm.ashr %{{.*}}, %{{.*}} : vector<4xi64>28 %0 = spirv.ShiftRightArithmetic %arg0, %arg0 : vector<4xi64>, vector<4xi64>29 30 // CHECK: llvm.ashr %{{.*}}, %{{.*}} : vector<4xi64>31 %1 = spirv.ShiftRightArithmetic %arg0, %arg1 : vector<4xi64>, vector<4xui64>32 33 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64>34 // CHECK: llvm.ashr %{{.*}}, %[[SEXT]] : vector<4xi64>35 %2 = spirv.ShiftRightArithmetic %arg0, %arg2 : vector<4xi64>, vector<4xi32>36 37 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64>38 // CHECK: llvm.ashr %{{.*}}, %[[ZEXT]] : vector<4xi64>39 %3 = spirv.ShiftRightArithmetic %arg0, %arg3 : vector<4xi64>, vector<4xui32>40 spirv.Return41}42 43//===----------------------------------------------------------------------===//44// spirv.ShiftRightLogical45//===----------------------------------------------------------------------===//46 47// CHECK-LABEL: @shift_right_logical_scalar48spirv.func @shift_right_logical_scalar(%arg0: i32, %arg1: si32, %arg2 : si16, %arg3 : ui16) "None" {49 // CHECK: llvm.lshr %{{.*}}, %{{.*}} : i3250 %0 = spirv.ShiftRightLogical %arg0, %arg0 : i32, i3251 52 // CHECK: llvm.lshr %{{.*}}, %{{.*}} : i3253 %1 = spirv.ShiftRightLogical %arg0, %arg1 : i32, si3254 55 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i3256 // CHECK: llvm.lshr %{{.*}}, %[[SEXT]] : i3257 %2 = spirv.ShiftRightLogical %arg0, %arg2 : i32, si1658 59 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i3260 // CHECK: llvm.lshr %{{.*}}, %[[ZEXT]] : i3261 %3 = spirv.ShiftRightLogical %arg0, %arg3 : i32, ui1662 spirv.Return63}64 65// CHECK-LABEL: @shift_right_logical_vector66spirv.func @shift_right_logical_vector(%arg0: vector<4xi64>, %arg1: vector<4xsi64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" {67 // CHECK: llvm.lshr %{{.*}}, %{{.*}} : vector<4xi64>68 %0 = spirv.ShiftRightLogical %arg0, %arg0 : vector<4xi64>, vector<4xi64>69 70 // CHECK: llvm.lshr %{{.*}}, %{{.*}} : vector<4xi64>71 %1 = spirv.ShiftRightLogical %arg0, %arg1 : vector<4xi64>, vector<4xsi64>72 73 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64>74 // CHECK: llvm.lshr %{{.*}}, %[[SEXT]] : vector<4xi64>75 %2 = spirv.ShiftRightLogical %arg0, %arg2 : vector<4xi64>, vector<4xi32>76 77 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64>78 // CHECK: llvm.lshr %{{.*}}, %[[ZEXT]] : vector<4xi64>79 %3 = spirv.ShiftRightLogical %arg0, %arg3 : vector<4xi64>, vector<4xui32>80 spirv.Return81}82 83//===----------------------------------------------------------------------===//84// spirv.ShiftLeftLogical85//===----------------------------------------------------------------------===//86 87// CHECK-LABEL: @shift_left_logical_scalar88spirv.func @shift_left_logical_scalar(%arg0: i32, %arg1: si32, %arg2 : i16, %arg3 : ui16) "None" {89 // CHECK: llvm.shl %{{.*}}, %{{.*}} : i3290 %0 = spirv.ShiftLeftLogical %arg0, %arg0 : i32, i3291 92 // CHECK: llvm.shl %{{.*}}, %{{.*}} : i3293 %1 = spirv.ShiftLeftLogical %arg0, %arg1 : i32, si3294 95 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i3296 // CHECK: llvm.shl %{{.*}}, %[[SEXT]] : i3297 %2 = spirv.ShiftLeftLogical %arg0, %arg2 : i32, i1698 99 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : i16 to i32100 // CHECK: llvm.shl %{{.*}}, %[[ZEXT]] : i32101 %3 = spirv.ShiftLeftLogical %arg0, %arg3 : i32, ui16102 spirv.Return103}104 105// CHECK-LABEL: @shift_left_logical_vector106spirv.func @shift_left_logical_vector(%arg0: vector<4xi64>, %arg1: vector<4xsi64>, %arg2: vector<4xi32>, %arg3: vector<4xui32>) "None" {107 // CHECK: llvm.shl %{{.*}}, %{{.*}} : vector<4xi64>108 %0 = spirv.ShiftLeftLogical %arg0, %arg0 : vector<4xi64>, vector<4xi64>109 110 // CHECK: llvm.shl %{{.*}}, %{{.*}} : vector<4xi64>111 %1 = spirv.ShiftLeftLogical %arg0, %arg1 : vector<4xi64>, vector<4xsi64>112 113 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64>114 // CHECK: llvm.shl %{{.*}}, %[[SEXT]] : vector<4xi64>115 %2 = spirv.ShiftLeftLogical %arg0, %arg2 : vector<4xi64>, vector<4xi32>116 117 // CHECK: %[[ZEXT:.*]] = llvm.zext %{{.*}} : vector<4xi32> to vector<4xi64>118 // CHECK: llvm.shl %{{.*}}, %[[ZEXT]] : vector<4xi64>119 %3 = spirv.ShiftLeftLogical %arg0, %arg3 : vector<4xi64>, vector<4xui32>120 spirv.Return121}122