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1// RUN: mlir-opt %s --split-input-file -convert-xegpu-to-xevm -canonicalize | FileCheck %s2 3gpu.module @test {4// CHECK-LABEL: @load_gather_i64_src_value_offset5// CHECK-SAME: %[[ARG0:.*]]: i64, %[[ARG1:.*]]: vector<1xindex>, %[[ARG2:.*]]: memref<1xf16>6// CHECK-SAME: %[[ARG3:.*]]: vector<1xi1>7gpu.func @load_gather_i64_src_value_offset(%src: i64, %offset: vector<1xindex>, %dst: memref<1xf16>, %mask: vector<1xi1>) {8 // CHECK: %[[C0:.*]] = arith.constant 0 : index9 // CHECK: %[[CST_0:.*]] = arith.constant 0.000000e+00 : f1610 // CHECK: %[[C2_I64:.*]] = arith.constant 2 : i6411 // CHECK: %[[VAR2:.*]] = vector.extract %[[ARG3]][0] : i1 from vector<1xi1>12 // CHECK: %[[VAR0:.*]] = vector.extract %[[ARG1]][0] : index from vector<1xindex>13 // CHECK: %[[VAR1:.*]] = arith.index_castui %[[VAR0]] : index to i6414 // CHECK: %[[VAR3:.*]] = arith.muli %[[VAR1]], %[[C2_I64]] : i6415 // CHECK: %[[VAR4:.*]] = arith.addi %[[ARG0]], %[[VAR3]] : i6416 // CHECK: %[[VAR5:.*]] = llvm.inttoptr %[[VAR4]] : i64 to !llvm.ptr<1>17 // CHECK: %[[VAR6:.*]] = scf.if %[[VAR2]] -> (f16) {18 // CHECK: %[[VAR7:.*]] = llvm.load %[[VAR5]] {cache_control = #xevm.load_cache_control<L1c_L2uc_L3uc>} : !llvm.ptr<1> -> f1619 // CHECK: scf.yield %[[VAR7]] : f1620 // CHECK: } else {21 // CHECK: scf.yield %[[CST_0]] : f1622 // CHECK: }23 %0 = xegpu.load %src[%offset], %mask <{l1_hint = #xegpu.cache_hint<cached>, l2_hint = #xegpu.cache_hint<uncached>}>24 : i64, vector<1xindex>, vector<1xi1> -> vector<1xf16>25 %c0 = arith.constant 0 : index26 vector.store %0, %dst[%c0] : memref<1xf16>, vector<1xf16>27 gpu.return28}29}30 31// -----32gpu.module @test {33// CHECK-LABEL: @source_materialize_single_elem_vec34// CHECK-SAME: %[[ARG0:.*]]: i64, %[[ARG1:.*]]: vector<1xindex>, %[[ARG2:.*]]: memref<1xf16>35// CHECK-SAME: %[[ARG3:.*]]: vector<1xi1>36gpu.func @source_materialize_single_elem_vec(%src: i64, %offset: vector<1xindex>, %dst: memref<1xf16>, %mask: vector<1xi1>) {37 %0 = xegpu.load %src[%offset], %mask <{l1_hint = #xegpu.cache_hint<cached>, l2_hint = #xegpu.cache_hint<uncached>}>38 : i64, vector<1xindex>, vector<1xi1> -> vector<1xf16>39 // CHECK: %[[C0:.*]] = arith.constant 0 : index40 // CHECK: %[[VAR_IF:.*]] = scf.if41 // CHECK: %[[VAR_RET:.*]] = vector.broadcast %[[VAR_IF]] : f16 to vector<1xf16>42 // CHECK: vector.store %[[VAR_RET]], %[[ARG2]][%[[C0]]] : memref<1xf16>, vector<1xf16>43 %c0 = arith.constant 0 : index44 vector.store %0, %dst[%c0] : memref<1xf16>, vector<1xf16>45 gpu.return46}47}48 49// -----50 51gpu.module @test {52// CHECK-LABEL: @store_scatter_i64_src_value_offset53// CHECK-SAME: %[[ARG0:.*]]: i64, %[[ARG1:.*]]: vector<1xindex>, %[[ARG2:.*]]: vector<1xi1>54gpu.func @store_scatter_i64_src_value_offset(%src: i64, %offset: vector<1xindex>, %mask: vector<1xi1>) {55 // CHECK: %[[CST_0:.*]] = arith.constant 2.900000e+00 : f3256 // CHECK: %[[C4_I64:.*]] = arith.constant 4 : i6457 // CHECK: %[[VAR2:.*]] = vector.extract %[[ARG2]][0] : i1 from vector<1xi1>58 // CHECK: %[[VAR0:.*]] = vector.extract %[[ARG1]][0] : index from vector<1xindex>59 // CHECK: %[[VAR1:.*]] = arith.index_castui %[[VAR0]] : index to i6460 %0 = arith.constant dense<2.9>: vector<1xf32>61 // CHECK: %[[VAR4:.*]] = arith.muli %[[VAR1]], %[[C4_I64]] : i6462 // CHECK: %[[VAR5:.*]] = arith.addi %[[ARG0]], %[[VAR4]] : i6463 // CHECK: %[[VAR6:.*]] = llvm.inttoptr %[[VAR5]] : i64 to !llvm.ptr<1>64 // CHECK: scf.if %[[VAR2]] {65 // CHECK: llvm.store %[[CST_0]], %[[VAR6]] {cache_control = #xevm.store_cache_control<L1wb_L2uc_L3uc>} : f32, !llvm.ptr<1>66 // CHECK: }67 xegpu.store %0, %src[%offset], %mask <{l1_hint = #xegpu.cache_hint<write_back>, l2_hint = #xegpu.cache_hint<uncached>}>68 : vector<1xf32>, i64, vector<1xindex>, vector<1xi1>69 gpu.return70}71}72// -----73 74gpu.module @test {75// CHECK-LABEL: @prefetch_i64_src_value_offset76// CHECK-SAME: %[[ARG0:.*]]: i64, %[[ARG1:.*]]: vector<1xindex>77gpu.func @prefetch_i64_src_value_offset(%src: i64, %offset: vector<1xindex>) {78 // CHECK: %[[C4_I64:.*]] = arith.constant 4 : i6479 // CHECK: %[[VAR0:.*]] = vector.extract %[[ARG1]][0] : index from vector<1xindex>80 // CHECK: %[[VAR1:.*]] = arith.index_castui %[[VAR0]] : index to i6481 // CHECK: %[[VAR2:.*]] = arith.muli %[[VAR1]], %[[C4_I64]] : i6482 // CHECK: %[[VAR3:.*]] = arith.addi %[[ARG0]], %[[VAR2]] : i6483 // CHECK: %[[VAR4:.*]] = llvm.inttoptr %[[VAR3]] : i64 to !llvm.ptr<1>84 // CHECK: xevm.prefetch %[[VAR4]] <{cache_control = #xevm.load_cache_control<L1c_L2uc_L3uc>}> : (!llvm.ptr<1>)85 xegpu.prefetch %src[%offset] <{offset_align_byte=4, l1_hint = #xegpu.cache_hint<cached>, l2_hint = #xegpu.cache_hint<uncached>}>86 : i64, vector<1xindex>87 gpu.return88}89}90// -----91 92gpu.module @test {93// CHECK-LABEL: @prefetch_memref_src_value_offset94// CHECK-SAME: %[[ARG0:.*]]: memref<256xf32>, %[[ARG1:.*]]: vector<1xindex>95gpu.func @prefetch_memref_src_value_offset(%src: memref<256xf32>, %offset: vector<1xindex>) {96 // CHECK: %[[C4_I64:.*]] = arith.constant 4 : i6497 // CHECK: %[[VAR0:.*]] = vector.extract %[[ARG1]][0] : index from vector<1xindex>98 // CHECK: %[[VAR1:.*]] = arith.index_castui %[[VAR0]] : index to i6499 // CHECK: %[[INTPTR:.*]] = memref.extract_aligned_pointer_as_index %[[ARG0]] : memref<256xf32> -> index100 // CHECK: %[[VAR2:.*]] = arith.index_castui %[[INTPTR]] : index to i64101 // CHECK: %[[VAR3:.*]] = arith.muli %[[VAR1]], %[[C4_I64]] : i64102 // CHECK: %[[VAR4:.*]] = arith.addi %[[VAR2]], %[[VAR3]] : i64103 // CHECK: %[[VAR5:.*]] = llvm.inttoptr %[[VAR4]] : i64 to !llvm.ptr<1>104 // CHECK: xevm.prefetch %[[VAR5]] <{cache_control = #xevm.load_cache_control<L1c_L2uc_L3uc>}> : (!llvm.ptr<1>)105 xegpu.prefetch %src[%offset] <{l1_hint = #xegpu.cache_hint<cached>, l2_hint = #xegpu.cache_hint<uncached>}>106 : memref<256xf32>, vector<1xindex>107 gpu.return108}109}110