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1// RUN: mlir-opt --convert-xevm-to-llvm --split-input-file %s | FileCheck %s2 3// Same below, but using the `ConvertToLLVMPatternInterface` entry point4// and the generic `convert-to-llvm` pass.5// RUN: mlir-opt --convert-to-llvm --split-input-file %s | FileCheck %s6 7// CHECK-LABEL: llvm.func spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt(8// CHECK-SAME: !llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>,9// CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) attributes {no_unwind, will_return}10// CHECK: llvm.func @blockload2d(%[[ARG0:.*]]: !llvm.ptr<1>,11// CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32)12llvm.func @blockload2d(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<8xi16> {13 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32>14 // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i3215 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i3216 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32>17 // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32>18 // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i3219 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i16 : (i32) -> !llvm.ptr20 // CHECK: llvm.call spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt(21 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]])22 // CHECK-SAME: {function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>,23 // CHECK-SAME: linkage = #llvm.linkage<external>, no_unwind, sym_name =24 // CHECK-SAME: "_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt", visibility_ = 0 : i64,25 // CHECK-SAME: will_return} :26 // CHECK-SAME: (!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>,27 // CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) -> ()28 // CHECK: %[[VAR7:.*]] = llvm.load %[[VAR6]] : !llvm.ptr -> vector<8xi16>29 %loaded_a = xevm.blockload2d %a, %base_width_a, %base_height_a, %base_pitch_a, %x, %y30 <{elem_size_in_bits=16 : i32, tile_width=16 : i32, tile_height=8 : i32, v_blocks=1 : i32, transpose=false,31 pack_register=false}> : (!llvm.ptr<1>, i32, i32, i32, i32, i32) -> vector<8xi16>32 llvm.return %loaded_a : vector<8xi16>33}34 35// -----36// CHECK-LABEL: llvm.func spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt(37llvm.func @blockload2d_cache_control(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<8xi16> {38 // CHECK: xevm.DecorationCacheControl =39 // CHECK-SAME: 6442 : i32, 0 : i32, 1 : i32, 0 : i3240 // CHECK-SAME: 6442 : i32, 1 : i32, 1 : i32, 0 : i3241 %loaded_a = xevm.blockload2d %a, %base_width_a, %base_height_a, %base_pitch_a, %x, %y42 <{elem_size_in_bits=16 : i32, tile_width=16 : i32, tile_height=8 : i32, v_blocks=1 : i32, transpose=false,43 pack_register=false, cache_control=#xevm.load_cache_control<L1uc_L2uc_L3uc>}> : (!llvm.ptr<1>, i32, i32, i32, i32, i32) -> vector<8xi16>44 llvm.return %loaded_a : vector<8xi16>45}46 47// -----48// CHECK-LABEL: llvm.func spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x2cPU3AS1viiiDv2_iPt(49// CHECK-SAME: !llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>,50// CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) attributes {no_unwind, will_return}51// CHECK: llvm.func @blockload2d_v_blocks(%[[ARG0:.*]]: !llvm.ptr<1>,52// CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32)53llvm.func @blockload2d_v_blocks(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<16xi16> {54 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32>55 // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i3256 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i3257 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32>58 // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32>59 // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(16 : i32) : i3260 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i16 : (i32) -> !llvm.ptr61 // CHECK: llvm.call spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x2cPU3AS1viiiDv2_iPt(62 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]])63 // CHECK-SAME: {function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>,64 // CHECK-SAME: linkage = #llvm.linkage<external>, no_unwind, sym_name =65 // CHECK-SAME: "_Z41intel_sub_group_2d_block_read_16b_8r16x2cPU3AS1viiiDv2_iPt", visibility_ = 0 : i64,66 // CHECK-SAME: will_return}67 // CHECK-SAME: (!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>,68 // CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) -> ()69 // CHECK: %[[VAR7:.*]] = llvm.load %[[VAR6]] : !llvm.ptr -> vector<16xi16>70 %loaded_a = xevm.blockload2d %a, %base_width_a, %base_height_a, %base_pitch_a, %x, %y71 <{elem_size_in_bits=16 : i32, tile_width=16 : i32, tile_height=8 : i32, v_blocks=2 : i32, transpose=false,72 pack_register=false}> : (!llvm.ptr<1>, i32, i32, i32, i32, i32) -> vector<16xi16>73 llvm.return %loaded_a : vector<16xi16>74}75 76// -----77// CHECK-LABEL: llvm.func spir_funccc @_Z52intel_sub_group_2d_block_read_transform_16b_16r16x1cPU3AS1viiiDv2_iPj(78// CHECK-SAME: !llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>,79// CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) attributes {no_unwind, will_return}80// CHECK: llvm.func @blockload2d_pack_register(%[[ARG0:.*]]: !llvm.ptr<1>,81// CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32)82llvm.func @blockload2d_pack_register(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<8xi32> {83 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32>84 // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i3285 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i3286 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32>87 // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32>88 // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i3289 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i32 : (i32) -> !llvm.ptr90 // CHECK: llvm.call spir_funccc @_Z52intel_sub_group_2d_block_read_transform_16b_16r16x1cPU3AS1viiiDv2_iPj(91 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]])92 // CHECK-SAME: {function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>,93 // CHECK-SAME: linkage = #llvm.linkage<external>, no_unwind, sym_name =94 // CHECK-SAME: "_Z52intel_sub_group_2d_block_read_transform_16b_16r16x1cPU3AS1viiiDv2_iPj", visibility_ = 0 : i64,95 // CHECK-SAME: will_return} :96 // CHECK-SAME: (!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>,97 // CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) -> ()98 // CHECK: %[[VAR7:.*]] = llvm.load %[[VAR6]] : !llvm.ptr -> vector<8xi32>99 %loaded_a = xevm.blockload2d %a, %base_width_a, %base_height_a, %base_pitch_a, %x, %y100 <{elem_size_in_bits=16 : i32, tile_width=16 : i32, tile_height=16 : i32, v_blocks=1 : i32, transpose=false,101 pack_register=true}> : (!llvm.ptr<1>, i32, i32, i32, i32, i32) -> vector<8xi32>102 llvm.return %loaded_a : vector<8xi32>103}104 105// -----106// CHECK-LABEL: llvm.func spir_funccc @_Z51intel_sub_group_2d_block_read_transpose_32b_16r8x1cPU3AS1viiiDv2_iPj(107// CHECK-SAME: !llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>,108// CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) attributes {no_unwind, will_return}109// CHECK: llvm.func @blockload2d_transpose(%[[ARG0:.*]]: !llvm.ptr<1>,110// CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32)111llvm.func @blockload2d_transpose(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<8xi32> {112 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32>113 // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i32114 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i32115 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32>116 // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32>117 // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32118 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i32 : (i32) -> !llvm.ptr119 // CHECK: llvm.call spir_funccc @_Z51intel_sub_group_2d_block_read_transpose_32b_16r8x1cPU3AS1viiiDv2_iPj(120 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]])121 // CHECK-SAME: {function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>,122 // CHECK-SAME: linkage = #llvm.linkage<external>, no_unwind, sym_name =123 // CHECK-SAME: "_Z51intel_sub_group_2d_block_read_transpose_32b_16r8x1cPU3AS1viiiDv2_iPj", visibility_ = 0 : i64,124 // CHECK-SAME: will_return}125 // CHECK-SAME: (!llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>,126 // CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) -> ()127 // CHECK: %[[VAR7:.*]] = llvm.load %[[VAR6]] : !llvm.ptr -> vector<8xi32>128 %loaded_a = xevm.blockload2d %a, %base_width_a, %base_height_a, %base_pitch_a, %x, %y129 <{elem_size_in_bits=32 : i32, tile_width=8 : i32, tile_height=16 : i32, v_blocks=1 : i32, transpose=true,130 pack_register=false}> : (!llvm.ptr<1>, i32, i32, i32, i32, i32) -> vector<8xi32>131 llvm.return %loaded_a : vector<8xi32>132}133 134// -----135// CHECK-LABEL: llvm.func spir_funccc @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj(136// CHECK-SAME: !llvm.ptr<1> {llvm.nonnull, llvm.writeonly}, i32, i32, i32, vector<2xi32>,137// CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.readonly}) attributes {no_unwind, will_return}138// CHECK: llvm.func @blockstore2d(%[[ARG0:.*]]: !llvm.ptr<1>,139// CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32, %[[ARG6:.*]]: vector<8xi32>) {140llvm.func @blockstore2d(%c: !llvm.ptr<1>, %base_width_c: i32, %base_height_c: i32, %base_pitch_c: i32, %x: i32, %y: i32, %c_result_casted: vector<8xi32>) {141 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32>142 // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i32143 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i32144 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32>145 // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32>146 // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32147 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i32 : (i32) -> !llvm.ptr148 // CHECK: llvm.store %[[ARG6]], %[[VAR6]] : vector<8xi32>, !llvm.ptr149 // CHECK: llvm.call spir_funccc @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj(150 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]])151 // CHECK-SAME: {function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>, ptr)>,152 // CHECK-SAME: linkage = #llvm.linkage<external>, no_unwind, sym_name =153 // CHECK-SAME: "_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj", visibility_ = 0 : i64,154 // CHECK-SAME: will_return}155 // CHECK-SAME: : (!llvm.ptr<1> {llvm.nonnull, llvm.writeonly}, i32, i32, i32, vector<2xi32>,156 // CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.readonly}) -> ()157 xevm.blockstore2d %c, %base_width_c, %base_height_c, %base_pitch_c, %x, %y, %c_result_casted158 <{elem_size_in_bits=32 : i32, tile_width=16 : i32, tile_height=8 : i32}>159 : (!llvm.ptr<1>, i32, i32, i32, i32, i32, vector<8xi32>)160 llvm.return161}162 163// -----164// CHECK-LABEL: llvm.func spir_funccc @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj(165llvm.func @blockstore2d_cache_control(%c: !llvm.ptr<1>, %base_width_c: i32, %base_height_c: i32, %base_pitch_c: i32, %x: i32, %y: i32, %c_result_casted: vector<8xi32>) {166 // CHECK: xevm.DecorationCacheControl =167 // CHECK-SAME: 6443 : i32, 0 : i32, 2 : i32, 0 : i32168 // CHECK-SAME: 6443 : i32, 1 : i32, 2 : i32, 0 : i32169 xevm.blockstore2d %c, %base_width_c, %base_height_c, %base_pitch_c, %x, %y, %c_result_casted170 <{elem_size_in_bits=32 : i32, tile_width=16 : i32, tile_height=8 : i32, cache_control = #xevm.store_cache_control<L1wt_L2uc_L3wb>}>171 : (!llvm.ptr<1>, i32, i32, i32, i32, i32, vector<8xi32>)172 llvm.return173}174 175// -----176// CHECK-LABEL: llvm.func spir_funccc @_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i(177// CHECK-SAME: !llvm.ptr<1> {llvm.nonnull}, i32, i32, i32, vector<2xi32>) attributes178// CHECK-SAME: {memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>, no_unwind}179// CHECK: llvm.func @blockprefetch2d(%[[ARG0:.*]]: !llvm.ptr<1>,180// CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32) {181llvm.func @blockprefetch2d(%ptr: !llvm.ptr<1>, %base_width: i32, %base_height: i32, %base_pitch: i32, %x: i32, %y: i32) {182 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32>183 // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i32184 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i32185 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32>186 // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32>187 // CHECK: llvm.call spir_funccc @_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i(188 // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]])189 // CHECK-SAME: {function_type = !llvm.func<void (ptr<1>, i32, i32, i32, vector<2xi32>)>, linkage = #llvm.linkage<external>,190 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>, no_unwind,191 // CHECK-SAME: sym_name = "_Z44intel_sub_group_2d_block_prefetch_8b_8r32x1cPU3AS1viiiDv2_i", visibility_ = 0 : i64192 xevm.blockprefetch2d %ptr, %base_width, %base_height, %base_pitch, %x, %y193 <{elem_size_in_bits=8 : i32, tile_width=32 : i32, tile_height=8 : i32, v_blocks=1 : i32,194 cache_control=#xevm.load_cache_control<L1uc_L2uc_L3uc>}>195 : (!llvm.ptr<1>, i32, i32, i32, i32, i32)196 llvm.return197}198 199// -----200// CHECK-LABEL: llvm.func spir_funccc @_Z38intel_sub_group_f16_f16_matrix_mad_k16Dv8_sDv8_iDv8_f(201// CHECK-SAME: vector<8xi16>, vector<8xi32>, vector<8xf32>) -> vector<8xf32> attributes202// CHECK-SAME: {convergent, memory_effects = #llvm.memory_effects<other = none, argMem = none,203// CHECK-SAME: inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>, no_unwind, will_return}204// CHECK: llvm.func @mma(%[[ARG0:.*]]: vector<8xf32>, %[[ARG1:.*]]: vector<8xi16>, %[[ARG2:.*]]: vector<8xi32>) -> vector<8xf32> {205llvm.func @mma(%loaded_c_casted: vector<8xf32>, %loaded_a: vector<8xi16>, %loaded_b_casted: vector<8xi32>) -> vector<8xf32> {206 // CHECK: %[[VAR0:.*]] = llvm.call spir_funccc @_Z38intel_sub_group_f16_f16_matrix_mad_k16Dv8_sDv8_iDv8_f(207 // CHECK-SAME: %[[ARG1]], %[[ARG2]], %[[ARG0]]) {convergent, function_type =208 // CHECK-SAME: !llvm.func<vector<8xf32> (vector<8xi16>, vector<8xi32>, vector<8xf32>)>, linkage = #llvm.linkage<external>,209 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = none, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>, no_unwind,210 // CHECK-SAME: sym_name = "_Z38intel_sub_group_f16_f16_matrix_mad_k16Dv8_sDv8_iDv8_f", visibility_ = 0 : i64, will_return}211 // CHECK-SAME: : (vector<8xi16>, vector<8xi32>, vector<8xf32>) -> vector<8xf32>212 %c_result = xevm.mma %loaded_a, %loaded_b_casted, %loaded_c_casted213 { shape=<m=8, n=16, k=16>, types=<d=f32, a=f16, b=f16, c=f32> }214 : (vector<8xi16>, vector<8xi32>, vector<8xf32>) -> vector<8xf32>215 llvm.return %c_result : vector<8xf32>216}217 218// -----219// CHECK-LABEL: llvm.func spir_funccc @_Z22atomic_work_item_fenceiii(i32, i32, i32) attributes {no_unwind}220llvm.func @memfence() {221 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(4 : i32) : i32222 // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(1 : i32) : i32223 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(2 : i32) : i32224 // CHECK: llvm.call spir_funccc @_Z22atomic_work_item_fenceiii(%[[VAR2]], %[[VAR0]], %[[VAR1]])225 // CHECK-SAME: {function_type = !llvm.func<void (i32, i32, i32)>, linkage = #llvm.linkage<external>, no_unwind,226 // CHECK-SAME: sym_name = "_Z22atomic_work_item_fenceiii", visibility_ = 0 : i64} : (i32, i32, i32) -> ()227 xevm.memfence <{addrspace=#xevm.addr_space<global>, scope=#xevm.mem_scope<workgroup>}>228 llvm.return229}230 231// -----232// CHECK-LABEL: llvm.func spir_funccc @_Z8prefetchPU3AS1Kcm(!llvm.ptr<1>, i64) attributes233// CHECK-SAME: {memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>, no_unwind}234// CHECK: llvm.func @prefetch(%[[ARG0:.*]]: !llvm.ptr<1>) {235llvm.func @prefetch(%ptr: !llvm.ptr<1>) {236 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(1 : i64) : i64237 // CHECK: llvm.call spir_funccc @_Z8prefetchPU3AS1Kcm(%[[ARG0]], %[[VAR0]])238 // CHECK-SAME: {function_type = !llvm.func<void (ptr<1>, i64)>, linkage = #llvm.linkage<external>,239 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = read, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>,240 // CHECK-SAME: no_unwind, sym_name = "_Z8prefetchPU3AS1Kcm", visibility_ = 0 : i64241 xevm.prefetch %ptr <{cache_control = #xevm.load_cache_control<L1uc_L2uc_L3uc>}> : (!llvm.ptr<1>)242 llvm.return243}244 245// -----246// CHECK-LABEL: llvm.func @llvm.load247llvm.func @llvm.load(%a: !llvm.ptr<1>) -> i32 {248 // CHECK: xevm.DecorationCacheControl =249 // CHECK-SAME: 6442 : i32, 0 : i32, 1 : i32, 0 : i32250 // CHECK-SAME: 6442 : i32, 1 : i32, 1 : i32, 0 : i32251 %val = llvm.load %a {cache_control=#xevm.load_cache_control<L1uc_L2uc_L3uc>} : !llvm.ptr<1> -> i32252 llvm.return %val : i32253}254 255// -----256// CHECK-LABEL: llvm.func @llvm.store257llvm.func @llvm.store(%a: !llvm.ptr<1>, %val: i32) {258 // CHECK: xevm.DecorationCacheControl =259 // CHECK-SAME: 6443 : i32, 0 : i32, 2 : i32, 0 : i32260 // CHECK-SAME: 6443 : i32, 1 : i32, 2 : i32, 0 : i32261 llvm.store %val, %a {cache_control=#xevm.store_cache_control<L1wt_L2uc_L3wb>} : i32, !llvm.ptr<1>262 llvm.return263}264 265// -----266// CHECK-LABEL: llvm.func spir_funccc @_Z30intel_sub_group_block_read_us8PU3AS1t267// CHECK: llvm.func @blockload_as1(%[[ARG0:.*]]: !llvm.ptr<1>)268llvm.func @blockload_as1(%ptr: !llvm.ptr<1>) -> vector<8xi16> {269 // CHECK: %[[VAR0:.*]] = llvm.call spir_funccc @_Z30intel_sub_group_block_read_us8PU3AS1t(%[[ARG0]])270 // CHECK-SAME: {function_type = !llvm.func<vector<8xi16> (ptr<1>)>, linkage = #llvm.linkage<external>,271 // CHECK-SAME: no_unwind, sym_name = "_Z30intel_sub_group_block_read_us8PU3AS1t",272 // CHECK-SAME: visibility_ = 0 : i64, will_return, xevm.DecorationCacheControl =273 // CHECK-SAME: [6442 : i32, 0 : i32, 1 : i32, 0 : i32],274 // CHECK-SAME: [6442 : i32, 1 : i32, 1 : i32, 0 : i32]275 %loaded_a = xevm.blockload %ptr <{cache_control=#xevm.load_cache_control<L1uc_L2uc_L3uc>}> : (!llvm.ptr<1>) -> vector<8xi16>276 llvm.return %loaded_a : vector<8xi16>277}278 279// -----280// CHECK-LABEL: llvm.func spir_funccc @_Z31intel_sub_group_block_read_uc16PU3AS3h(!llvm.ptr<3>)281// CHECK: llvm.func @blockload_as3(%[[ARG0:.*]]: !llvm.ptr<3>)282llvm.func @blockload_as3(%ptr: !llvm.ptr<3>) -> vector<16xi8> {283 // CHECK: %[[VAR0:.*]] = llvm.call spir_funccc @_Z31intel_sub_group_block_read_uc16PU3AS3h(%[[ARG0]])284 // CHECK-SAME: {function_type = !llvm.func<vector<16xi8> (ptr<3>)>, linkage = #llvm.linkage<external>,285 // CHECK-SAME: no_unwind, sym_name = "_Z31intel_sub_group_block_read_uc16PU3AS3h", visibility_ = 0 : i64,286 // CHECK-SAME: will_return, xevm.DecorationCacheControl =287 // CHECK-SAME: [6442 : i32, 0 : i32, 1 : i32, 0 : i32],288 // CHECK-SAME: [6442 : i32, 1 : i32, 1 : i32, 0 : i32]289 %loaded_a = xevm.blockload %ptr <{cache_control=#xevm.load_cache_control<L1uc_L2uc_L3uc>}> : (!llvm.ptr<3>) -> vector<16xi8>290 llvm.return %loaded_a : vector<16xi8>291}292 293// -----294// CHECK-LABEL: llvm.func spir_funccc @_Z29intel_sub_group_block_read_ucPU3AS3h(!llvm.ptr<3>)295// CHECK: llvm.func @blockload_scalar(%[[ARG0:.*]]: !llvm.ptr<3>)296llvm.func @blockload_scalar(%ptr: !llvm.ptr<3>) -> i8 {297 // CHECK: %[[VAR0:.*]] = llvm.call spir_funccc @_Z29intel_sub_group_block_read_ucPU3AS3h(%[[ARG0]])298 // CHECK-SAME: {function_type = !llvm.func<i8 (ptr<3>)>, linkage = #llvm.linkage<external>,299 // CHECK-SAME: no_unwind, sym_name = "_Z29intel_sub_group_block_read_ucPU3AS3h", visibility_ = 0 : i64,300 // CHECK-SAME: will_return, xevm.DecorationCacheControl =301 // CHECK-SAME: [6442 : i32, 0 : i32, 1 : i32, 0 : i32],302 // CHECK-SAME: [6442 : i32, 1 : i32, 1 : i32, 0 : i32]303 %loaded_a = xevm.blockload %ptr <{cache_control=#xevm.load_cache_control<L1uc_L2uc_L3uc>}> : (!llvm.ptr<3>) -> i8304 llvm.return %loaded_a : i8305}306 307// -----308// CHECK-LABEL: llvm.func spir_funccc @_Z31intel_sub_group_block_write_ui8PU3AS1jDv8_j309// CHECK: llvm.func @blockstore_as1(%[[ARG0:.*]]: !llvm.ptr<1>, %[[ARG1:.*]]: vector<8xi32>) {310llvm.func @blockstore_as1(%ptr: !llvm.ptr<1>, %data: vector<8xi32>) {311 // CHECK: llvm.call spir_funccc @_Z31intel_sub_group_block_write_ui8PU3AS1jDv8_j(%[[ARG0]], %[[ARG1]])312 // CHECK-SAME: {function_type = !llvm.func<void (ptr<1>, vector<8xi32>)>, linkage = #llvm.linkage<external>,313 // CHECK-SAME: no_unwind, sym_name = "_Z31intel_sub_group_block_write_ui8PU3AS1jDv8_j", visibility_ = 0 : i64,314 // CHECK-SAME: will_return, xevm.DecorationCacheControl =315 // CHECK-SAME: [6443 : i32, 0 : i32, 2 : i32, 0 : i32],316 // CHECK-SAME: [6443 : i32, 1 : i32, 2 : i32, 0 : i32]317 xevm.blockstore %ptr, %data <{cache_control=#xevm.store_cache_control<L1wt_L2uc_L3wb>}> : (!llvm.ptr<1>, vector<8xi32>)318 llvm.return319}320 321// -----322// CHECK-LABEL: llvm.func spir_funccc @_Z31intel_sub_group_block_write_ul2PU3AS3mDv2_m323// CHECK: llvm.func @blockstore_as3(%[[ARG0:.*]]: !llvm.ptr<3>, %[[ARG1:.*]]: vector<2xi64>) {324llvm.func @blockstore_as3(%ptr: !llvm.ptr<3>, %data: vector<2xi64>) {325 // CHECK: llvm.call spir_funccc @_Z31intel_sub_group_block_write_ul2PU3AS3mDv2_m(%[[ARG0]], %[[ARG1]])326 // CHECK-SAME: {function_type = !llvm.func<void (ptr<3>, vector<2xi64>)>, linkage = #llvm.linkage<external>,327 // CHECK-SAME: no_unwind, sym_name = "_Z31intel_sub_group_block_write_ul2PU3AS3mDv2_m", visibility_ = 0 : i64,328 // CHECK-SAME: will_return, xevm.DecorationCacheControl =329 // CHECK-SAME: [6443 : i32, 0 : i32, 2 : i32, 0 : i32],330 // CHECK-SAME: [6443 : i32, 1 : i32, 2 : i32, 0 : i32]331 xevm.blockstore %ptr, %data <{cache_control=#xevm.store_cache_control<L1wt_L2uc_L3wb>}> : (!llvm.ptr<3>, vector<2xi64>)332 llvm.return333}334 335// -----336// CHECK-LABEL: llvm.func spir_funccc @_Z30intel_sub_group_block_write_ulPU3AS3mm337// CHECK: llvm.func @blockstore_scalar(%[[ARG0:.*]]: !llvm.ptr<3>, %[[ARG1:.*]]: i64) {338llvm.func @blockstore_scalar(%ptr: !llvm.ptr<3>, %data: i64) {339 // CHECK: llvm.call spir_funccc @_Z30intel_sub_group_block_write_ulPU3AS3mm(%[[ARG0]], %[[ARG1]])340 // CHECK-SAME: {function_type = !llvm.func<void (ptr<3>, i64)>, linkage = #llvm.linkage<external>,341 // CHECK-SAME: no_unwind, sym_name = "_Z30intel_sub_group_block_write_ulPU3AS3mm", visibility_ = 0 : i64,342 // CHECK-SAME: will_return, xevm.DecorationCacheControl =343 // CHECK-SAME: [6443 : i32, 0 : i32, 2 : i32, 0 : i32],344 // CHECK-SAME: [6443 : i32, 1 : i32, 2 : i32, 0 : i32]345 xevm.blockstore %ptr, %data <{cache_control=#xevm.store_cache_control<L1wt_L2uc_L3wb>}> : (!llvm.ptr<3>, i64)346 llvm.return347}348 349// -----350// CHECK-LABEL: llvm.func @local_id.x() -> i32 {351llvm.func @local_id.x() -> i32 {352 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(0 : i32) : i32353 // CHECK: %[[VAR1:.*]] = llvm.call spir_funccc @_Z12get_local_idj(%[[VAR0]])354 // CHECK-SAME: {function_type = !llvm.func<i32 (i32)>, linkage = #llvm.linkage<external>,355 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = none, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>,356 // CHECK-SAME: no_unwind, sym_name = "_Z12get_local_idj", visibility_ = 0 : i64, will_return} : (i32) -> i32357 %1 = xevm.local_id.x : i32358 llvm.return %1 : i32359}360 361// -----362// CHECK-LABEL: llvm.func @local_id.y() -> i32 {363llvm.func @local_id.y() -> i32 {364 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(1 : i32) : i32365 %1 = xevm.local_id.y : i32366 llvm.return %1 : i32367}368 369// -----370// CHECK-LABEL: llvm.func @local_id.z() -> i32 {371llvm.func @local_id.z() -> i32 {372 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(2 : i32) : i32373 %1 = xevm.local_id.z : i32374 llvm.return %1 : i32375}376 377// -----378// CHECK-LABEL: llvm.func @local_size.x() -> i32 {379llvm.func @local_size.x() -> i32 {380 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(0 : i32) : i32381 // CHECK: %[[VAR1:.*]] = llvm.call spir_funccc @_Z14get_local_sizej(%[[VAR0]])382 // CHECK-SAME: {function_type = !llvm.func<i32 (i32)>, linkage = #llvm.linkage<external>,383 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = none, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>,384 // CHECK-SAME: no_unwind, sym_name = "_Z14get_local_sizej", visibility_ = 0 : i64, will_return} : (i32) -> i32385 %1 = xevm.local_size.x : i32386 llvm.return %1 : i32387}388 389// -----390// CHECK-LABEL: llvm.func @local_size.y() -> i32 {391llvm.func @local_size.y() -> i32 {392 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(1 : i32) : i32393 %1 = xevm.local_size.y : i32394 llvm.return %1 : i32395}396 397// -----398// CHECK-LABEL: llvm.func @local_size.z() -> i32 {399llvm.func @local_size.z() -> i32 {400 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(2 : i32) : i32401 %1 = xevm.local_size.z : i32402 llvm.return %1 : i32403}404 405// -----406// CHECK-LABEL: llvm.func @group_id.x() -> i32 {407llvm.func @group_id.x() -> i32 {408 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(0 : i32) : i32409 // CHECK: %[[VAR1:.*]] = llvm.call spir_funccc @_Z12get_group_idj(%[[VAR0]])410 // CHECK-SAME: {function_type = !llvm.func<i32 (i32)>, linkage = #llvm.linkage<external>,411 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = none, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>,412 // CHECK-SAME: no_unwind, sym_name = "_Z12get_group_idj", visibility_ = 0 : i64, will_return} : (i32) -> i32413 %1 = xevm.group_id.x : i32414 llvm.return %1 : i32415}416 417// -----418// CHECK-LABEL: llvm.func @group_id.y() -> i32 {419llvm.func @group_id.y() -> i32 {420 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(1 : i32) : i32421 %1 = xevm.group_id.y : i32422 llvm.return %1 : i32423}424 425// -----426// CHECK-LABEL: llvm.func @group_id.z() -> i32 {427llvm.func @group_id.z() -> i32 {428 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(2 : i32) : i32429 %1 = xevm.group_id.z : i32430 llvm.return %1 : i32431}432 433// -----434// CHECK-LABEL: llvm.func @group_count.x() -> i32 {435llvm.func @group_count.x() -> i32 {436 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(0 : i32) : i32437 // CHECK: %[[VAR1:.*]] = llvm.call spir_funccc @_Z14get_num_groupsj(%[[VAR0]])438 // CHECK-SAME: {function_type = !llvm.func<i32 (i32)>, linkage = #llvm.linkage<external>,439 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = none, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>,440 // CHECK-SAME: no_unwind, sym_name = "_Z14get_num_groupsj", visibility_ = 0 : i64, will_return} : (i32) -> i32441 %1 = xevm.group_count.x : i32442 llvm.return %1 : i32443}444 445// -----446// CHECK-LABEL: llvm.func @group_count.y() -> i32 {447llvm.func @group_count.y() -> i32 {448 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(1 : i32) : i32449 %1 = xevm.group_count.y : i32450 llvm.return %1 : i32451}452 453// -----454// CHECK-LABEL: llvm.func @group_count.z() -> i32 {455llvm.func @group_count.z() -> i32 {456 // CHECK: %[[VAR0:.*]] = llvm.mlir.constant(2 : i32) : i32457 %1 = xevm.group_count.z : i32458 llvm.return %1 : i32459}460 461// -----462// CHECK-LABEL: llvm.func spir_funccc @_Z22get_sub_group_local_id() -> i32 attributes {no_unwind, will_return}463llvm.func @lane_id() -> i32 {464 // CHECK: %[[VAR0:.*]] = llvm.call spir_funccc @_Z22get_sub_group_local_id()465 // CHECK-SAME: {function_type = !llvm.func<i32 ()>, linkage = #llvm.linkage<external>,466 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = none, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>,467 // CHECK-SAME: no_unwind, sym_name = "_Z22get_sub_group_local_id", visibility_ = 0 : i64, will_return} : () -> i32468 %1 = xevm.lane_id : i32469 llvm.return %1 : i32470}471 472// -----473// CHECK-LABEL: llvm.func spir_funccc @_Z18get_sub_group_size() -> i32 attributes {no_unwind, will_return}474llvm.func @subgroup_size() -> i32 {475 // CHECK: %[[VAR0:.*]] = llvm.call spir_funccc @_Z18get_sub_group_size()476 // CHECK-SAME: {function_type = !llvm.func<i32 ()>, linkage = #llvm.linkage<external>,477 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = none, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>,478 // CHECK-SAME: no_unwind, sym_name = "_Z18get_sub_group_size", visibility_ = 0 : i64, will_return} : () -> i32479 %1 = xevm.subgroup_size : i32480 llvm.return %1 : i32481}482 483// -----484// CHECK-LABEL: llvm.func spir_funccc @_Z16get_sub_group_id() -> i32 attributes {no_unwind, will_return}485llvm.func @subgroup_id() -> i32 {486 // CHECK: %[[VAR0:.*]] = llvm.call spir_funccc @_Z16get_sub_group_id()487 // CHECK-SAME: {function_type = !llvm.func<i32 ()>, linkage = #llvm.linkage<external>,488 // CHECK-SAME: memory_effects = #llvm.memory_effects<other = none, argMem = none, inaccessibleMem = none, errnoMem = none, targetMem0 = none, targetMem1 = none>,489 // CHECK-SAME: no_unwind, sym_name = "_Z16get_sub_group_id", visibility_ = 0 : i64, will_return} : () -> i32490 %1 = xevm.subgroup_id : i32491 llvm.return %1 : i32492}493