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1// RUN: mlir-opt %s -split-input-file -verify-diagnostics2 3// -----4 5func.func @a_is_2d(%a : vector<2x2xi32>, %b : vector<4x4xi8>) -> vector<2x2xi32> {6 // expected-error@+1 {{operand `a` should be 1-dimensional}}7 %0 = arm_neon.2d.sdot %a, %b, %b : vector<4x4xi8>, vector<4x4xi8> to vector<2x2xi32>8 return %0 : vector<2x2xi32>9}10 11// -----12 13func.func @b_is_3d(%a : vector<4xi32>, %b : vector<1x4x4xi8>) -> vector<4xi32> {14 // expected-error@+1 {{operand `b` should be 2-dimensional}}15 %0 = arm_neon.2d.sdot %a, %b, %b : vector<1x4x4xi8>, vector<1x4x4xi8> to vector<4xi32>16 return %0 : vector<4xi32>17}18 19// -----20 21func.func @b_has_2_columns(%a : vector<4xi32>, %b : vector<4x2xi8>) -> vector<4xi32> {22 // expected-error@+1 {{operand `b` should have 4 columns}}23 %0 = arm_neon.2d.sdot %a, %b, %b : vector<4x2xi8>, vector<4x2xi8> to vector<4xi32>24 return %0 : vector<4xi32>25}26 27// -----28 29func.func @b_has_2_rows_but_a_has_length_4(%a : vector<4xi32>, %b : vector<2x4xi8>) -> vector<4xi32> {30 // expected-error@+1 {{operand `b` should have as many rows as the size of operand `a`}}31 %0 = arm_neon.2d.sdot %a, %b, %b : vector<2x4xi8>, vector<2x4xi8> to vector<4xi32>32 return %0 : vector<4xi32>33}34 35// -----36 37func.func @smmla_invalid_input_types(%a: vector<4xi32>,38 %b: vector<16xi4>,39 %c: vector<16xi4>) -> vector<4xi32> {40 // expected-error@+1 {{op operand #1 must be a vector with length 16 of 8-bit signless integer values, but got 'vector<16xi4>'}}41 %0 = arm_neon.intr.smmla %a, %b, %c : vector<16xi4> to vector<4xi32>42 return %0 : vector<4xi32>43}44 45// -----46 47func.func @smmla_invalid_dimensions(%a: vector<8xi32>,48 %b: vector<32xi8>,49 %c: vector<32xi8>) -> vector<8xi32> {50 // expected-error@+1 {{op operand #0 must be a vector with length 4 of 32-bit signless integer values, but got 'vector<8xi32>'}}51 %0 = arm_neon.intr.smmla %a, %b, %c : vector<32xi8> to vector<8xi32>52 return %0 : vector<8xi32>53}54 55// -----56 57func.func @ummla_invalid_input_types(%a: vector<4xi32>,58 %b: vector<16xi4>,59 %c: vector<16xi4>) -> vector<4xi32> {60 // expected-error@+1 {{op operand #1 must be a vector with length 16 of 8-bit signless integer values, but got 'vector<16xi4>'}}61 %0 = arm_neon.intr.ummla %a, %b, %c : vector<16xi4> to vector<4xi32>62 return %0 : vector<4xi32>63}64 65// -----66 67func.func @ummla_invalid_dimensions(%a: vector<8xi32>,68 %b: vector<32xi8>,69 %c: vector<32xi8>) -> vector<8xi32> {70 // expected-error@+1 {{op operand #0 must be a vector with length 4 of 32-bit signless integer values, but got 'vector<8xi32>'}}71 %0 = arm_neon.intr.ummla %a, %b, %c : vector<32xi8> to vector<8xi32>72 return %0 : vector<8xi32>73}74 75// -----76 77func.func @usmmla_invalid_input_types(%a: vector<4xi32>,78 %b: vector<16xi4>,79 %c: vector<16xi4>) -> vector<4xi32> {80 // expected-error@+1 {{op operand #1 must be a vector with length 16 of 8-bit signless integer values, but got 'vector<16xi4>'}}81 %0 = arm_neon.intr.usmmla %a, %b, %c : vector<16xi4> to vector<4xi32>82 return %0 : vector<4xi32>83}84 85// -----86 87func.func @usmmla_invalid_dimensions(%a: vector<8xi32>,88 %b: vector<32xi8>,89 %c: vector<32xi8>) -> vector<8xi32> {90 // expected-error@+1 {{op operand #0 must be a vector with length 4 of 32-bit signless integer values, but got 'vector<8xi32>'}}91 %0 = arm_neon.intr.usmmla %a, %b, %c : vector<32xi8> to vector<8xi32>92 return %0 : vector<8xi32>93}94 95// -----96 97func.func @bfmmla_invalid_element_type_lhs_rhs(%acc: vector<4xf32>,98 %lhs: vector<8xf16>,99 %rhs: vector<8xf16>) -> vector<4xf32> {100 // expected-error@+1 {{operand #1 must be a vector with length 8 of bfloat16 type values, but got 'vector<8xf16>'}}101 %0 = arm_neon.intr.bfmmla %acc, %lhs, %rhs : vector<8xf16> to vector<4xf32>102 return %0 : vector<4xf32>103}104 105// -----106 107func.func @bfmmla_invalid_dimension_lhs_rhs(%acc: vector<4xf32>,108 %lhs: vector<4xbf16>,109 %rhs: vector<4xbf16>) -> vector<4xf32> {110 // expected-error@+1 {{operand #1 must be a vector with length 8 of bfloat16 type values, but got 'vector<4xbf16>'}}111 %0 = arm_neon.intr.bfmmla %acc, %lhs, %rhs : vector<4xbf16> to vector<4xf32>112 return %0 : vector<4xf32>113}114 115// -----116 117func.func @bfmmla_scalable_dimension_lhs_rhs(%acc: vector<4xf32>,118 %lhs: vector<[8]xbf16>,119 %rhs: vector<[8]xbf16>) -> vector<4xf32> {120 // expected-error@+1 {{operand #1 must be a vector with length 8 of bfloat16 type values, but got 'vector<[8]xbf16>'}}121 %0 = arm_neon.intr.bfmmla %acc, %lhs, %rhs : vector<[8]xbf16> to vector<4xf32>122 return %0 : vector<4xf32>123}124 125// -----126 127func.func @bfmmla_invalid_element_type_acc(%acc: vector<4xi32>,128 %lhs: vector<8xbf16>,129 %rhs: vector<8xbf16>) -> vector<4xi32> {130 // expected-error@+1 {{op operand #0 must be a vector with length 4 of 32-bit float values, but got 'vector<4xi32>'}}131 %0 = arm_neon.intr.bfmmla %acc, %lhs, %rhs : vector<8xbf16> to vector<4xi32>132 return %0 : vector<4xi32>133}134 135// -----136 137func.func @bfmmla_invalid_dimension_acc(%acc: vector<8xf32>,138 %lhs: vector<8xbf16>,139 %rhs: vector<8xbf16>) -> vector<8xf32> {140 // expected-error@+1 {{op operand #0 must be a vector with length 4 of 32-bit float values, but got 'vector<8xf32>'}}141 %0 = arm_neon.intr.bfmmla %acc, %lhs, %rhs : vector<8xbf16> to vector<8xf32>142 return %0 : vector<8xf32>143}144 145// -----146 147func.func @bfmmla_scalable_dimension_acc(%acc: vector<[4]xf32>,148 %lhs: vector<8xbf16>,149 %rhs: vector<8xbf16>) -> vector<[4]xf32> {150 // expected-error@+1 {{op operand #0 must be a vector with length 4 of 32-bit float values, but got 'vector<[4]xf32>'}}151 %0 = arm_neon.intr.bfmmla %acc, %lhs, %rhs : vector<8xbf16> to vector<[4]xf32>152 return %0 : vector<[4]xf32>153}154