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1// RUN: mlir-opt -convert-vector-to-llvm="enable-arm-sve" -convert-func-to-llvm -convert-arith-to-llvm -cse -reconcile-unrealized-casts -split-input-file %s | FileCheck %s2 3func.func @arm_sve_sdot(%a: vector<[16]xi8>,4 %b: vector<[16]xi8>,5 %c: vector<[4]xi32>)6 -> vector<[4]xi32> {7 // CHECK: arm_sve.intr.sdot8 %0 = arm_sve.sdot %c, %a, %b :9 vector<[16]xi8> to vector<[4]xi32>10 return %0 : vector<[4]xi32>11}12 13// -----14 15func.func @arm_sve_smmla(%a: vector<[16]xi8>,16 %b: vector<[16]xi8>,17 %c: vector<[4]xi32>)18 -> vector<[4]xi32> {19 // CHECK: arm_sve.intr.smmla20 %0 = arm_sve.smmla %c, %a, %b :21 vector<[16]xi8> to vector<[4]xi32>22 return %0 : vector<[4]xi32>23}24 25// -----26 27func.func @arm_sve_udot(%a: vector<[16]xi8>,28 %b: vector<[16]xi8>,29 %c: vector<[4]xi32>)30 -> vector<[4]xi32> {31 // CHECK: arm_sve.intr.udot32 %0 = arm_sve.udot %c, %a, %b :33 vector<[16]xi8> to vector<[4]xi32>34 return %0 : vector<[4]xi32>35}36 37// -----38 39func.func @arm_sve_ummla(%a: vector<[16]xi8>,40 %b: vector<[16]xi8>,41 %c: vector<[4]xi32>)42 -> vector<[4]xi32> {43 // CHECK: arm_sve.intr.ummla44 %0 = arm_sve.ummla %c, %a, %b :45 vector<[16]xi8> to vector<[4]xi32>46 return %0 : vector<[4]xi32>47}48 49// -----50 51func.func @arm_sve_usmmla(%a: vector<[16]xi8>,52 %b: vector<[16]xi8>,53 %c: vector<[4]xi32>)54 -> vector<[4]xi32> {55 // CHECK: arm_sve.intr.usmmla56 %0 = arm_sve.usmmla %c, %a, %b :57 vector<[16]xi8> to vector<[4]xi32>58 return %0 : vector<[4]xi32>59}60 61// -----62 63func.func @arm_sve_arithi_masked(%a: vector<[4]xi32>,64 %b: vector<[4]xi32>,65 %c: vector<[4]xi32>,66 %d: vector<[4]xi32>,67 %e: vector<[4]xi32>,68 %mask: vector<[4]xi1>69 ) -> vector<[4]xi32> {70 // CHECK: arm_sve.intr.add{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>71 %0 = arm_sve.masked.addi %mask, %a, %b : vector<[4]xi1>,72 vector<[4]xi32>73 // CHECK: arm_sve.intr.sub{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>74 %1 = arm_sve.masked.subi %mask, %0, %c : vector<[4]xi1>,75 vector<[4]xi32>76 // CHECK: arm_sve.intr.mul{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>77 %2 = arm_sve.masked.muli %mask, %1, %d : vector<[4]xi1>,78 vector<[4]xi32>79 // CHECK: arm_sve.intr.sdiv{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>80 %3 = arm_sve.masked.divi_signed %mask, %2, %e : vector<[4]xi1>,81 vector<[4]xi32>82 // CHECK: arm_sve.intr.udiv{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>83 %4 = arm_sve.masked.divi_unsigned %mask, %3, %e : vector<[4]xi1>,84 vector<[4]xi32>85 return %4 : vector<[4]xi32>86}87 88// -----89 90func.func @arm_sve_arithf_masked(%a: vector<[4]xf32>,91 %b: vector<[4]xf32>,92 %c: vector<[4]xf32>,93 %d: vector<[4]xf32>,94 %e: vector<[4]xf32>,95 %mask: vector<[4]xi1>96 ) -> vector<[4]xf32> {97 // CHECK: arm_sve.intr.fadd{{.*}}: (vector<[4]xi1>, vector<[4]xf32>, vector<[4]xf32>) -> vector<[4]xf32>98 %0 = arm_sve.masked.addf %mask, %a, %b : vector<[4]xi1>,99 vector<[4]xf32>100 // CHECK: arm_sve.intr.fsub{{.*}}: (vector<[4]xi1>, vector<[4]xf32>, vector<[4]xf32>) -> vector<[4]xf32>101 %1 = arm_sve.masked.subf %mask, %0, %c : vector<[4]xi1>,102 vector<[4]xf32>103 // CHECK: arm_sve.intr.fmul{{.*}}: (vector<[4]xi1>, vector<[4]xf32>, vector<[4]xf32>) -> vector<[4]xf32>104 %2 = arm_sve.masked.mulf %mask, %1, %d : vector<[4]xi1>,105 vector<[4]xf32>106 // CHECK: arm_sve.intr.fdiv{{.*}}: (vector<[4]xi1>, vector<[4]xf32>, vector<[4]xf32>) -> vector<[4]xf32>107 %3 = arm_sve.masked.divf %mask, %2, %e : vector<[4]xi1>,108 vector<[4]xf32>109 return %3 : vector<[4]xf32>110}111 112// -----113 114func.func @arm_sve_abs_diff(%a: vector<[4]xi32>,115 %b: vector<[4]xi32>)116 -> vector<[4]xi32> {117 // CHECK: llvm.mlir.constant(dense<0> : vector<[4]xi32>) : vector<[4]xi32>118 %z = arith.subi %a, %a : vector<[4]xi32>119 // CHECK: llvm.icmp "sge" {{.*}}: vector<[4]xi32>120 %agb = arith.cmpi sge, %a, %b : vector<[4]xi32>121 // CHECK: llvm.icmp "slt" {{.*}}: vector<[4]xi32>122 %bga = arith.cmpi slt, %a, %b : vector<[4]xi32>123 // CHECK: "arm_sve.intr.sub"{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>124 %0 = arm_sve.masked.subi %agb, %a, %b : vector<[4]xi1>,125 vector<[4]xi32>126 // CHECK: "arm_sve.intr.sub"{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>127 %1 = arm_sve.masked.subi %bga, %b, %a : vector<[4]xi1>,128 vector<[4]xi32>129 // CHECK: "arm_sve.intr.add"{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>130 %2 = arm_sve.masked.addi %agb, %z, %0 : vector<[4]xi1>,131 vector<[4]xi32>132 // CHECK: "arm_sve.intr.add"{{.*}}: (vector<[4]xi1>, vector<[4]xi32>, vector<[4]xi32>) -> vector<[4]xi32>133 %3 = arm_sve.masked.addi %bga, %2, %1 : vector<[4]xi1>,134 vector<[4]xi32>135 return %3 : vector<[4]xi32>136}137 138// -----139 140func.func @get_vector_scale() -> index {141 // CHECK: llvm.intr.vscale142 %0 = vector.vscale143 return %0 : index144}145 146// -----147 148func.func @convert_1d_mask_to_svbool(%mask: vector<[4]xi1>) -> vector<[16]xi1>149{150 // CHECK: "arm_sve.intr.convert.to.svbool"(%{{.*}}) : (vector<[4]xi1>) -> vector<[16]xi1>151 %svbool = arm_sve.convert_to_svbool %mask : vector<[4]xi1>152 return %svbool : vector<[16]xi1>153}154 155// -----156 157func.func @convert_1d_mask_from_svbool(%svbool: vector<[16]xi1>) -> vector<[2]xi1>158{159 // CHECK: "arm_sve.intr.convert.from.svbool"(%{{.*}}) : (vector<[16]xi1>) -> vector<[2]xi1>160 %mask = arm_sve.convert_from_svbool %svbool : vector<[2]xi1>161 return %mask : vector<[2]xi1>162}163 164// -----165 166// CHECK-LABEL: @convert_2d_mask_to_svbool(167// CHECK-SAME: %[[MASK:.*]]: !llvm.array<2 x vector<[8]xi1>>)168func.func @convert_2d_mask_to_svbool(%mask: vector<2x[8]xi1>) -> vector<2x[16]xi1>169{170 // CHECK-NEXT: %[[RES0:.*]] = llvm.mlir.constant(dense<false> : vector<2x[16]xi1>) : !llvm.array<2 x vector<[16]xi1>>171 // CHECK-NEXT: %[[MASK0:.*]] = llvm.extractvalue %[[MASK]][0] : !llvm.array<2 x vector<[8]xi1>>172 // CHECK-NEXT: %[[SVBOOL0:.*]] = "arm_sve.intr.convert.to.svbool"(%[[MASK0]]) : (vector<[8]xi1>) -> vector<[16]xi1>173 // CHECK-NEXT: %[[RES1:.*]] = llvm.insertvalue %[[SVBOOL0]], %[[RES0]][0] : !llvm.array<2 x vector<[16]xi1>>174 // CHECK-NEXT: %[[MASK1:.*]] = llvm.extractvalue %[[MASK]][1] : !llvm.array<2 x vector<[8]xi1>>175 // CHECK-NEXT: %[[SVBOOL1:.*]] = "arm_sve.intr.convert.to.svbool"(%[[MASK1]]) : (vector<[8]xi1>) -> vector<[16]xi1>176 // CHECK-NEXT: %[[SVBOOL:.*]] = llvm.insertvalue %[[SVBOOL1]], %[[RES1]][1] : !llvm.array<2 x vector<[16]xi1>>177 %svbool = arm_sve.convert_to_svbool %mask : vector<2x[8]xi1>178 // CHECK-NEXT: llvm.return %[[SVBOOL]] : !llvm.array<2 x vector<[16]xi1>>179 return %svbool : vector<2x[16]xi1>180}181 182// -----183 184// CHECK-LABEL: @convert_2d_mask_from_svbool(185// CHECK-SAME: %[[SVBOOL:.*]]: !llvm.array<3 x vector<[16]xi1>>)186func.func @convert_2d_mask_from_svbool(%svbool: vector<3x[16]xi1>) -> vector<3x[1]xi1>187{188 // CHECK-NEXT: %[[RES0:.*]] = llvm.mlir.constant(dense<false> : vector<3x[1]xi1>) : !llvm.array<3 x vector<[1]xi1>>189 // CHECK-NEXT: %[[SVBOOL0:.*]] = llvm.extractvalue %[[SVBOOL]][0] : !llvm.array<3 x vector<[16]xi1>>190 // CHECK-NEXT: %[[MASK0:.*]] = "arm_sve.intr.convert.from.svbool"(%[[SVBOOL0]]) : (vector<[16]xi1>) -> vector<[1]xi1>191 // CHECK-NEXT: %[[RES1:.*]] = llvm.insertvalue %[[MASK0]], %[[RES0]][0] : !llvm.array<3 x vector<[1]xi1>>192 // CHECK-NEXT: %[[SVBOOL1:.*]] = llvm.extractvalue %[[SVBOOL]][1] : !llvm.array<3 x vector<[16]xi1>>193 // CHECK-NEXT: %[[MASK1:.*]] = "arm_sve.intr.convert.from.svbool"(%[[SVBOOL1]]) : (vector<[16]xi1>) -> vector<[1]xi1>194 // CHECK-NEXT: %[[RES2:.*]] = llvm.insertvalue %[[MASK1]], %[[RES1]][1] : !llvm.array<3 x vector<[1]xi1>>195 // CHECK-NEXT: %[[SVBOOL2:.*]] = llvm.extractvalue %[[SVBOOL]][2] : !llvm.array<3 x vector<[16]xi1>>196 // CHECK-NEXT: %[[MASK2:.*]] = "arm_sve.intr.convert.from.svbool"(%[[SVBOOL2]]) : (vector<[16]xi1>) -> vector<[1]xi1>197 // CHECK-NEXT: %[[MASK:.*]] = llvm.insertvalue %[[MASK2]], %[[RES2]][2] : !llvm.array<3 x vector<[1]xi1>>198 %mask = arm_sve.convert_from_svbool %svbool : vector<3x[1]xi1>199 // CHECK-NEXT: llvm.return %[[MASK]] : !llvm.array<3 x vector<[1]xi1>>200 return %mask : vector<3x[1]xi1>201}202 203// -----204 205func.func @arm_sve_zip_x2(%a: vector<[8]xi16>, %b: vector<[8]xi16>)206 -> (vector<[8]xi16>, vector<[8]xi16>)207{208 // CHECK: arm_sve.intr.zip.x2209 %0, %1 = arm_sve.zip.x2 %a, %b : vector<[8]xi16>210 return %0, %1 : vector<[8]xi16>, vector<[8]xi16>211}212 213// -----214 215func.func @arm_sve_zip_x4(216 %a: vector<[16]xi8>,217 %b: vector<[16]xi8>,218 %c: vector<[16]xi8>,219 %d: vector<[16]xi8>220) -> (vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>)221{222 // CHECK: arm_sve.intr.zip.x4223 %0, %1, %2, %3 = arm_sve.zip.x4 %a, %b, %c, %d : vector<[16]xi8>224 return %0, %1, %2, %3 : vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>225}226 227// -----228 229// CHECK-LABEL: @arm_sve_predicate_sized_create_masks(230// CHECK-SAME: %[[INDEX:.*]]: i64231func.func @arm_sve_predicate_sized_create_masks(%index: index) -> (vector<[2]xi1>, vector<[4]xi1>, vector<[8]xi1>, vector<[16]xi1>) {232 // CHECK: %[[ZERO:.*]] = llvm.mlir.zero : i64233 // CHECK: %[[P2:.*]] = "arm_sve.intr.whilelt"(%[[ZERO]], %[[INDEX]]) : (i64, i64) -> vector<[2]xi1>234 %0 = vector.create_mask %index : vector<[2]xi1>235 // CHECK: %[[P4:.*]] = "arm_sve.intr.whilelt"(%[[ZERO]], %[[INDEX]]) : (i64, i64) -> vector<[4]xi1>236 %1 = vector.create_mask %index : vector<[4]xi1>237 // CHECK: %[[P8:.*]] = "arm_sve.intr.whilelt"(%[[ZERO]], %[[INDEX]]) : (i64, i64) -> vector<[8]xi1>238 %2 = vector.create_mask %index : vector<[8]xi1>239 // CHECK: %[[P16:.*]] = "arm_sve.intr.whilelt"(%[[ZERO]], %[[INDEX]]) : (i64, i64) -> vector<[16]xi1>240 %3 = vector.create_mask %index : vector<[16]xi1>241 return %0, %1, %2, %3 : vector<[2]xi1>, vector<[4]xi1>, vector<[8]xi1>, vector<[16]xi1>242}243 244// -----245 246// CHECK-LABEL: @arm_sve_unsupported_create_masks247func.func @arm_sve_unsupported_create_masks(%index: index) -> (vector<[1]xi1>, vector<[7]xi1>, vector<[32]xi1>) {248 // CHECK-NOT: arm_sve.intr.whilelt249 %0 = vector.create_mask %index : vector<[1]xi1>250 %1 = vector.create_mask %index : vector<[7]xi1>251 %2 = vector.create_mask %index : vector<[32]xi1>252 return %0, %1, %2 : vector<[1]xi1>, vector<[7]xi1>, vector<[32]xi1>253}254 255// -----256 257// CHECK-LABEL: @arm_sve_psel_matching_predicate_types(258// CHECK-SAME: %[[P0:[a-z0-9]+]]: vector<[4]xi1>,259// CHECK-SAME: %[[P1:[a-z0-9]+]]: vector<[4]xi1>,260// CHECK-SAME: %[[INDEX:[a-z0-9]+]]: i64261func.func @arm_sve_psel_matching_predicate_types(%p0: vector<[4]xi1>, %p1: vector<[4]xi1>, %index: index) -> vector<[4]xi1>262{263 // CHECK-DAG: %[[INDEX_I32:.*]] = llvm.trunc %[[INDEX]] : i64 to i32264 // CHECK-DAG: %[[P0_IN:.*]] = "arm_sve.intr.convert.to.svbool"(%[[P0]]) : (vector<[4]xi1>) -> vector<[16]xi1>265 // CHECK-NEXT: %[[PSEL:.*]] = "arm_sve.intr.psel"(%[[P0_IN]], %[[P1]], %[[INDEX_I32]]) : (vector<[16]xi1>, vector<[4]xi1>, i32) -> vector<[16]xi1>266 // CHECK-NEXT: %[[RES:.*]] = "arm_sve.intr.convert.from.svbool"(%[[PSEL]]) : (vector<[16]xi1>) -> vector<[4]xi1>267 %0 = arm_sve.psel %p0, %p1[%index] : vector<[4]xi1>, vector<[4]xi1>268 return %0 : vector<[4]xi1>269}270 271// -----272 273// CHECK-LABEL: @arm_sve_psel_mixed_predicate_types(274// CHECK-SAME: %[[P0:[a-z0-9]+]]: vector<[8]xi1>,275// CHECK-SAME: %[[P1:[a-z0-9]+]]: vector<[16]xi1>,276// CHECK-SAME: %[[INDEX:[a-z0-9]+]]: i64277func.func @arm_sve_psel_mixed_predicate_types(%p0: vector<[8]xi1>, %p1: vector<[16]xi1>, %index: index) -> vector<[8]xi1>278{279 // CHECK-DAG: %[[INDEX_I32:.*]] = llvm.trunc %[[INDEX]] : i64 to i32280 // CHECK-DAG: %[[P0_IN:.*]] = "arm_sve.intr.convert.to.svbool"(%[[P0]]) : (vector<[8]xi1>) -> vector<[16]xi1>281 // CHECK-NEXT: %[[PSEL:.*]] = "arm_sve.intr.psel"(%[[P0_IN]], %[[P1]], %[[INDEX_I32]]) : (vector<[16]xi1>, vector<[16]xi1>, i32) -> vector<[16]xi1>282 // CHECK-NEXT: %[[RES:.*]] = "arm_sve.intr.convert.from.svbool"(%[[PSEL]]) : (vector<[16]xi1>) -> vector<[8]xi1>283 %0 = arm_sve.psel %p0, %p1[%index] : vector<[8]xi1>, vector<[16]xi1>284 return %0 : vector<[8]xi1>285}286 287// -----288 289// CHECK-LABEL: @arm_sve_dupq_lane(290// CHECK-SAME: %[[A0:[a-z0-9]+]]: vector<[16]xi8>291// CHECK-SAME: %[[A1:[a-z0-9]+]]: vector<[8]xi16>292// CHECK-SAME: %[[A2:[a-z0-9]+]]: vector<[8]xf16>293// CHECK-SAME: %[[A3:[a-z0-9]+]]: vector<[8]xbf16>294// CHECK-SAME: %[[A4:[a-z0-9]+]]: vector<[4]xi32>295// CHECK-SAME: %[[A5:[a-z0-9]+]]: vector<[4]xf32>296// CHECK-SAME: %[[A6:[a-z0-9]+]]: vector<[2]xi64>297// CHECK-SAME: %[[A7:[a-z0-9]+]]: vector<[2]xf64>298// CHECK-SAME: -> !llvm.struct<(vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>, vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>)> {299func.func @arm_sve_dupq_lane(300 %v16i8: vector<[16]xi8>, %v8i16: vector<[8]xi16>,301 %v8f16: vector<[8]xf16>, %v8bf16: vector<[8]xbf16>,302 %v4i32: vector<[4]xi32>, %v4f32: vector<[4]xf32>,303 %v2i64: vector<[2]xi64>, %v2f64: vector<[2]xf64>)304 -> (vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>,305 vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>) {306// CHECK: "arm_sve.intr.dupq_lane"(%[[A0]]) <{lane = 0 : i64}> : (vector<[16]xi8>) -> vector<[16]xi8>307 %0 = arm_sve.dupq_lane %v16i8[0] : vector<[16]xi8>308// CHECK: "arm_sve.intr.dupq_lane"(%[[A1]]) <{lane = 1 : i64}> : (vector<[8]xi16>) -> vector<[8]xi16>309 %1 = arm_sve.dupq_lane %v8i16[1] : vector<[8]xi16>310// CHECK: "arm_sve.intr.dupq_lane"(%[[A2]]) <{lane = 2 : i64}> : (vector<[8]xf16>) -> vector<[8]xf16>311 %2 = arm_sve.dupq_lane %v8f16[2] : vector<[8]xf16>312// CHECK: "arm_sve.intr.dupq_lane"(%[[A3]]) <{lane = 3 : i64}> : (vector<[8]xbf16>) -> vector<[8]xbf16>313 %3 = arm_sve.dupq_lane %v8bf16[3] : vector<[8]xbf16>314// CHECK: "arm_sve.intr.dupq_lane"(%[[A4]]) <{lane = 4 : i64}> : (vector<[4]xi32>) -> vector<[4]xi32>315 %4 = arm_sve.dupq_lane %v4i32[4] : vector<[4]xi32>316// CHECK: "arm_sve.intr.dupq_lane"(%[[A5]]) <{lane = 5 : i64}> : (vector<[4]xf32>) -> vector<[4]xf32>317 %5 = arm_sve.dupq_lane %v4f32[5] : vector<[4]xf32>318// CHECK: "arm_sve.intr.dupq_lane"(%[[A6]]) <{lane = 6 : i64}> : (vector<[2]xi64>) -> vector<[2]xi64>319 %6 = arm_sve.dupq_lane %v2i64[6] : vector<[2]xi64>320// CHECK: "arm_sve.intr.dupq_lane"(%[[A7]]) <{lane = 7 : i64}> : (vector<[2]xf64>) -> vector<[2]xf64>321 %7 = arm_sve.dupq_lane %v2f64[7] : vector<[2]xf64>322 323 return %0, %1, %2, %3, %4, %5, %6, %7324 : vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>,325 vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>326}327