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1// RUN: mlir-opt %s -split-input-file -verify-diagnostics2 3// -----4func.func @create_nd_tdesc_1(%src: memref<24xf32>) {5 // expected-error@+1 {{Expecting the TensorDesc rank is not greater than the ranks of shape, strides, offsets or the memref source}}6 %1 = xegpu.create_nd_tdesc %src[0] : memref<24xf32> -> !xegpu.tensor_desc<8x16xf32>7 return8}9 10// -----11 12func.func @create_nd_tdesc_2(%src: memref<24x32xf32>) {13 // expected-error@+1 {{TensorDesc should have the same element type with the source if it is a memref}}14 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<8x16xf16>15 return16}17 18// -----19func.func @create_nd_tdesc_3(%src: memref<2x24x32xf32, 3>) {20 // expected-error@+1 {{SLM is only supported for 1D block tensor}}21 %1 = xegpu.create_nd_tdesc %src[0, 0, 0] : memref<2x24x32xf32, 3> -> !xegpu.tensor_desc<8x16xf32, #xegpu.block_tdesc_attr<memory_space = slm>>22 return23}24 25// -----26func.func @create_nd_tdesc_4(%src: memref<2x24x32xf32, 3>) {27 // expected-error@+1 {{Memory space mismatch}}28 %1 = xegpu.create_nd_tdesc %src[0, 0, 0] : memref<2x24x32xf32, 3> -> !xegpu.tensor_desc<16xf32>29 return30}31 32// -----33func.func @create_nd_tdesc_5(%src: memref<128x128xf32>) {34 // expected-error@+1 {{cannot distribute [128, 128] using #xegpu.layout<sg_layout = [4, 2], sg_data = [24, 48]>}}35 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [24, 48]>>36 return37}38 39// -----40func.func @create_nd_tdesc_6(%src: memref<128x128xf32>) {41 // expected-error@+1 {{cannot distribute [128, 128] using #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64], inst_data = [24, 48]>}}42 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64], inst_data = [24, 48]>>43 return44}45 46// -----47func.func @create_nd_tdesc_7(%src: memref<128x128xf32>) {48 // expected-error@+1 {{cannot distribute [128, 128] using #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64], inst_data = [64, 32]>}}49 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<128x128xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout<sg_layout = [4, 2], sg_data = [32, 64], inst_data = [64, 32]>>50 return51}52 53// -----54func.func @create_nd_tdesc_8(%src: ui64) {55 // expected-error@+1 {{'xegpu.create_nd_tdesc' op expecting strides and shape to be present for integer source}}56 %1 = xegpu.create_nd_tdesc %src : ui64-> !xegpu.tensor_desc<128x128xf32>57 return58}59 60// -----61func.func @create_nd_tdesc_9(%src: ui64) {62 // expected-error@+1 {{expecting strides and shape to be present for integer source}}63 %1 = xegpu.create_nd_tdesc %src[0, 0] : ui64-> !xegpu.tensor_desc<128x128xf32>64 return65}66 67 68// -----69func.func @prefetch_nd_vc_1(%src: memref<24x32xf16>) {70 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf16> -> !xegpu.tensor_desc<8x16xf16>71 // expected-error@+1 {{invalid l1_hint: #xegpu.cache_hint<write_back>}}72 xegpu.prefetch_nd %1 <{l1_hint = #xegpu.cache_hint<write_back>}>: !xegpu.tensor_desc<8x16xf16>73 return74}75 76// -----77func.func @prefetch_nd_vc_2(%src: memref<24xf16>) {78 %0 = arith.constant dense<[0, 1, 2, 3, 4, 5, 6, 7]> : vector<8xindex>79 %1 = xegpu.create_tdesc %src, %0 : memref<24xf16>, vector<8xindex>80 -> !xegpu.tensor_desc<8xf16, #xegpu.scatter_tdesc_attr<>>81 // expected-error@+1 {{Expects a non-scattered TensorDesc}}82 xegpu.prefetch_nd %1 <{l1_hint = #xegpu.cache_hint<cached>}>83 : !xegpu.tensor_desc<8xf16, #xegpu.scatter_tdesc_attr<>>84 return85}86 87// -----88func.func @load_nd_vc_1(%src: memref<8x16xf16>) {89 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<8x16xf16> -> !xegpu.tensor_desc<8x16xf16>90 // expected-error@+1 {{invalid l1_hint: #xegpu.cache_hint<write_back>}}91 %2 = xegpu.load_nd %1 <{l1_hint = #xegpu.cache_hint<write_back>}>92 : !xegpu.tensor_desc<8x16xf16> -> vector<4x16x2xf16>93 return94}95 96// -----97func.func @load_nd_vc_2(%src: memref<16xf16>) {98 %0 = arith.constant dense<[0, 2, 4, 6, 8, 10, 12, 14]> : vector<8xindex>99 %1 = xegpu.create_tdesc %src, %0 : memref<16xf16>, vector<8xindex>100 -> !xegpu.tensor_desc<8x2xf16, #xegpu.scatter_tdesc_attr<chunk_size = 2>>101 // expected-error@+1 {{Expects a non-scattered TensorDesc.}}102 %2 = xegpu.load_nd %1 <{l1_hint = #xegpu.cache_hint<cached>}>103 : !xegpu.tensor_desc<8x2xf16, #xegpu.scatter_tdesc_attr<chunk_size = 2>> -> vector<8x2xf16>104 return105}106 107// -----108func.func @load_nd_vc_3(%src: memref<8x16xf16>) {109 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<8x16xf16> -> !xegpu.tensor_desc<16xf16>110 // expected-warning@+1 {{Invalid Packed Attr.}}111 %2 = xegpu.load_nd %1 <{packed, l1_hint = #xegpu.cache_hint<cached>, l2_hint = #xegpu.cache_hint<uncached>}>112 : !xegpu.tensor_desc<16xf16> -> vector<16xf16>113 return114}115 116// -----117func.func @load_nd_vc_4(%src: memref<24x32xf32>) {118 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->119 !xegpu.tensor_desc<8x16xf32>120 // expected-error@+1 {{Result shape [8, 1] is not consistent with tensor descriptor}}121 %2 = xegpu.load_nd %1 <{l1_hint = #xegpu.cache_hint<cached>,122 l2_hint = #xegpu.cache_hint<uncached>}>123 : !xegpu.tensor_desc<8x16xf32> -> vector<8x1xf32>124 return125}126 127// -----128func.func @subgroup_load_nd_9(%src: memref<4x8x16xf16>) {129 %1 = xegpu.create_nd_tdesc %src[0, 0, 0] : memref<4x8x16xf16> -> !xegpu.tensor_desc<4x8x16xf16>130 // expected-error@+1 {{Expects a 1D or 2D TensorDesc}}131 %2 = xegpu.load_nd %1 <{l1_hint = #xegpu.cache_hint<cached>, l2_hint = #xegpu.cache_hint<uncached>}> : !xegpu.tensor_desc<4x8x16xf16> -> vector<4x8x16xf16>132 return133}134 135// -----136func.func @subgroup_load_nd_offset_1(%src: memref<4x8x16xf16>, %x : index) {137 %1 = xegpu.create_nd_tdesc %src: memref<4x8x16xf16> -> !xegpu.tensor_desc<16xf16>138// expected-error@+1 {{Mismatched ranks between offsets and tensor descriptor}}139 %2 = xegpu.load_nd %1[0, 0] : !xegpu.tensor_desc<16xf16> -> vector<16xf16>140 return141}142 143// -----144func.func @subgroup_load_nd_offset_2(%src: memref<4x8x16xf16>, %x : index) {145 %3 = xegpu.create_nd_tdesc %src: memref<4x8x16xf16> -> !xegpu.tensor_desc<8x16xf16>146 // expected-error@+1 {{Mismatched ranks between offsets and tensor descriptor}}147 xegpu.prefetch_nd %3[0] : !xegpu.tensor_desc<8x16xf16>148 return149}150 151// -----152func.func @subgroup_load_nd_offset_3(%src: memref<4x8x16xf16>, %x : index) {153 %3 = xegpu.create_nd_tdesc %src: memref<4x8x16xf16> -> !xegpu.tensor_desc<8x16xf16>154 %5 = xegpu.load_nd %3[0, 0] : !xegpu.tensor_desc<8x16xf16> -> vector<8x16xf16>155 // expected-error@+1 {{Mismatched ranks between offsets and tensor descriptor}}156 xegpu.store_nd %5, %3[%x] : vector<8x16xf16>, !xegpu.tensor_desc<8x16xf16>157 return158}159 160// -----161func.func @load_nd_layout(%src: memref<24x32xf32>) {162 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<16xf32>163 // expected-error@+1 {{Result shape [3] is not a valid distribution for tensor descriptor}}164 %2 = xegpu.load_nd %1 <{l1_hint = #xegpu.cache_hint<cached>,165 l2_hint = #xegpu.cache_hint<uncached>}> : !xegpu.tensor_desc<16xf32> -> vector<3xf32>166 return167}168 169// -----170func.func @load_nd_simt(%src: memref<24x32xf32>) {171 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<8x16xf32, #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>>172 // expected-error@+1 {{TensorDesc doesn't need LayoutAttr for SIMT code}}173 %2 = xegpu.load_nd %1 : !xegpu.tensor_desc<8x16xf32, #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>> -> vector<8xf32>174 return175}176 177// -----178func.func @store_nd_vc_1(%dst: memref<24x32xf16>) {179 %1 = arith.constant dense<1.0>: vector<24x32xf16>180 %2 = xegpu.create_nd_tdesc %dst[0, 0] : memref<24x32xf16> -> !xegpu.tensor_desc<24x32xf16>181 // expected-error@+1 {{invalid l1_hint: #xegpu.cache_hint<streaming>}}182 xegpu.store_nd %1, %2 <{l1_hint = #xegpu.cache_hint<streaming>}>: vector<24x32xf16>, !xegpu.tensor_desc<24x32xf16>183 return184}185 186// -----187func.func @store_nd_vc_2(%dst: memref<16xf16>) {188 %0 = arith.constant dense<[0, 2, 4, 6, 8, 10, 12, 14]> : vector<8xindex>189 %1 = arith.constant dense<1.0>: vector<8x2xf16>190 %2 = xegpu.create_tdesc %dst, %0 : memref<16xf16>, vector<8xindex>191 -> !xegpu.tensor_desc<8x2xf16, #xegpu.scatter_tdesc_attr<chunk_size = 2>>192 // expected-error@+1 {{Expects a non-scattered TensorDesc}}193 xegpu.store_nd %1, %2 <{l1_hint = #xegpu.cache_hint<streaming>}>194 : vector<8x2xf16>, !xegpu.tensor_desc<8x2xf16, #xegpu.scatter_tdesc_attr<chunk_size = 2>>195 return196}197 198// -----199func.func @store_nd_vc_3(%dst: memref<24x32xf16>) {200 %1 = arith.constant dense<1.0>: vector<2x24x32xf16>201 %2 = xegpu.create_nd_tdesc %dst[0, 0] : memref<24x32xf16> -> !xegpu.tensor_desc<24x32xf16, #xegpu.block_tdesc_attr<array_length = 2>>202 // expected-error@+1 {{array length is not supported by store_nd}}203 xegpu.store_nd %1, %2: vector<2x24x32xf16>, !xegpu.tensor_desc<24x32xf16, #xegpu.block_tdesc_attr<array_length = 2>>204 return205}206 207// -----208func.func @store_nd_vc_4(%dst: memref<8x24x32xf16>) {209 %1 = arith.constant dense<1.0>: vector<8x24x32xf16>210 %2 = xegpu.create_nd_tdesc %dst[0, 0, 0] : memref<8x24x32xf16> -> !xegpu.tensor_desc<8x24x32xf16>211 // expected-error@+1 {{Expects a 1D or 2D TensorDesc}}212 xegpu.store_nd %1, %2 <{l1_hint = #xegpu.cache_hint<write_back>, l2_hint = #xegpu.cache_hint<uncached>}>: vector<8x24x32xf16>, !xegpu.tensor_desc<8x24x32xf16>213 return214}215 216// -----217func.func @store_nd_simt(%dst: memref<24x32xf32>, %data: vector<3xf32>) {218 %1 = xegpu.create_nd_tdesc %dst[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<16xf32>219 // expected-error@+1 {{Value shape [3] is not a valid distribution for tensor descriptor}}220 xegpu.store_nd %data, %1 : vector<3xf32>, !xegpu.tensor_desc<16xf32>221 return222}223 224// -----225func.func @store_nd_simt(%src: memref<24x32xf32>, %data: vector<8xf32>) {226 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<8x16xf32, #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>>227 // expected-error@+1 {{TensorDesc doesn't need LayoutAttr for SIMT code}}228 xegpu.store_nd %data, %1 : vector<8xf32>, !xegpu.tensor_desc<8x16xf32, #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>>229 return230}231 232// -----233func.func @store_nd_vc_5(%dst: memref<24x32xf32>, %data: vector<8x1xf32>) {234 %1 = xegpu.create_nd_tdesc %dst[0, 0] : memref<24x32xf32> ->235 !xegpu.tensor_desc<8x16xf32>236 // expected-error@+1 {{Value shape [8, 1] is not consistent with tensor descriptor}}237 xegpu.store_nd %data, %1 : vector<8x1xf32>, !xegpu.tensor_desc<8x16xf32>238 return239}240 241// -----242func.func @update_nd_offset_1(%dst: memref<16xf16>) {243 %0 = arith.constant dense<[0, 2, 4, 6, 8, 10, 12, 14]> : vector<8xindex>244 %1 = xegpu.create_tdesc %dst, %0 : memref<16xf16>, vector<8xindex>245 -> !xegpu.tensor_desc<8x2xf16, #xegpu.scatter_tdesc_attr<chunk_size = 2>>246 // expected-error@+1 {{Expects a non-scattered TensorDesc}}247 xegpu.update_nd_offset %1, [0, 2] : !xegpu.tensor_desc<8x2xf16, #xegpu.scatter_tdesc_attr<chunk_size = 2>>248 return249}250 251// -----252func.func @create_tdesc_vc_1(%src: ui64) {253 %0 = arith.constant dense<[0, 2, 4, 6, 8, 10, 12, 14]> : vector<8xindex>254 // expected-error@+1 {{Expects a scattered TensorDesc}}255 %1 = xegpu.create_tdesc %src, %0 : ui64, vector<8xindex> -> !xegpu.tensor_desc<8xf16>256 return257}258 259// -----260func.func @create_tdesc_vc_2(%src: memref<?xf32>) {261 %0 = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>262 %1 = xegpu.create_tdesc %src, %0 : memref<?xf32>, vector<4xindex>263 // expected-error@+1 {{invalid chunk size}}264 -> !xegpu.tensor_desc<4xf32, #xegpu.scatter_tdesc_attr<chunk_size = 0>>265 return266}267 268// -----269func.func @create_tdesc_vc_3(%src: memref<?xf32>) {270 %0 = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>271 // expected-error@+1 {{Memory space mismatch}}272 %1 = xegpu.create_tdesc %src, %0 : memref<?xf32>, vector<4xindex>273 -> !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<memory_space = slm, chunk_size = 2>>274 return275}276 277// -----278func.func @create_tdesc_vc_4(%src: memref<?xf32>) {279 %0 = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>280 %1 = xegpu.create_tdesc %src, %0 : memref<?xf32>, vector<4xindex>281 // expected-error@+1 {{expected last dim of tensor to match chunk size}}282 -> !xegpu.tensor_desc<4x5xf32, #xegpu.scatter_tdesc_attr<chunk_size = 4>>283 return284}285 286// -----287func.func @create_tdesc_vc_5(%src: memref<?xf16>) {288 %0 = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>289 %1 = xegpu.create_tdesc %src, %0 : memref<?xf16>, vector<4xindex>290 // expected-error@+1 {{last dim of tensor to be a multiple of 2}}291 -> !xegpu.tensor_desc<4x3xf16, #xegpu.scatter_tdesc_attr<chunk_size = 3>>292 return293}294 295 296// -----297func.func @prefetch_vc_1(%src: memref<24x32xf16>) {298 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf16> -> !xegpu.tensor_desc<24x32xf16>299 // expected-error@+1 {{Expects a scattered TensorDesc}}300 xegpu.prefetch %1 <{l1_hint = #xegpu.cache_hint<write_back>}>: !xegpu.tensor_desc<24x32xf16>301 return302}303 304// -----305func.func @prefetch_vc_2(%src: ui64) {306 %0 = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>307 %1 = xegpu.create_tdesc %src, %0 : ui64, vector<4xindex>308 -> !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>309 // expected-error@+1 {{invalid l1_hint: #xegpu.cache_hint<write_back>}}310 xegpu.prefetch %1 <{l1_hint = #xegpu.cache_hint<write_back>}>: !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>311 return312}313 314// -----315func.func @create_tdesc_layout_1(%src: ui64) {316 %cst = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>317 // expected-error@+1 {{expected layout rank to match tensor rank}}318 %1 = xegpu.create_tdesc %src, %cst : ui64, vector<4xindex> -> !xegpu.tensor_desc<4xf32, #xegpu.scatter_tdesc_attr<>, #xegpu.layout<lane_layout = [4, 1], lane_data = [1, 1]>>319 return320}321 322// -----323func.func @create_tdesc_layout_2(%src: ui64) {324 %cst = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>325 // expected-error@+1 {{expected last dim of lane_data to be a multiple of: 2}}326 %1 = xegpu.create_tdesc %src, %cst : ui64, vector<4xindex> -> !xegpu.tensor_desc<4x4xf16, #xegpu.scatter_tdesc_attr<chunk_size = 4>, #xegpu.layout<lane_layout = [4, 1], lane_data = [1, 1]>>327 return328}329 330// -----331func.func @load_gather_simt_1(%src: ui64) {332 %0 = arith.constant dense<1>: vector<4xi1>333 %cst = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>334 %1 = xegpu.create_tdesc %src, %cst : ui64, vector<4xindex> -> !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>335 // expected-error@+1 {{Value shape [6] is neither a valid distribution for SIMT nor consistent with the tensor descriptor for SIMD}}336 %2 = xegpu.load %1, %0 <{l1_hint = #xegpu.cache_hint<cached>}> : !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>, vector<4xi1> -> vector<6xf32>337 return338}339 340// -----341func.func @store_scatter_simt_1(%src: ui64) {342 %0 = arith.constant dense<1>: vector<4xi1>343 %cst = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>344 %val = arith.constant dense<2.9>: vector<6xf32>345 %1 = xegpu.create_tdesc %src, %cst : ui64, vector<4xindex> -> !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>346 // expected-error@+1 {{Value shape [6] is neither a valid distribution for SIMT nor consistent with the tensor descriptor for SIMD}}347 xegpu.store %val, %1, %0 <{l1_hint = #xegpu.cache_hint<cached>}> : vector<6xf32>, !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>, vector<4xi1>348 return349}350 351// -----352func.func @load_gather_vc_1(%src: memref<24x32xf16>) {353 %0 = arith.constant dense<1>: vector<4xi1>354 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf16> -> !xegpu.tensor_desc<4x2xf16>355 // expected-error@+1 {{Expects a scattered TensorDesc}}356 %2 = xegpu.load %1, %0 <{l1_hint = #xegpu.cache_hint<cached>}>357 : !xegpu.tensor_desc<4x2xf16>, vector<4xi1> -> vector<4x2xf16>358 return359}360 361// -----362func.func @load_gather_vc_2(%src: ui64) {363 %cst = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>364 %0 = arith.constant dense<1>: vector<4xi1>365 %1 = xegpu.create_tdesc %src, %cst : ui64, vector<4xindex>366 -> !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>367 // expected-error@+1 {{invalid l1_hint: #xegpu.cache_hint<write_back>}}368 %2 = xegpu.load %1, %0 <{l1_hint = #xegpu.cache_hint<write_back>}>369 : !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>, vector<4xi1>370 -> vector<4x2xf32>371 return372}373 374// -----375func.func @load_gather_vc_3(%src: ui64) {376 %cst = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>377 %0 = arith.constant dense<1>: vector<8xi1>378 %1 = xegpu.create_tdesc %src, %cst : ui64, vector<4xindex>379 -> !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>380 // expected-error@+1 {{Mask should match TensorDesc except the chunk size dim}}381 %2 = xegpu.load %1, %0382 : !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>, vector<8xi1>383 -> vector<4x2xf32>384 return385}386 387// -----388func.func @prefetch_offset_wi_1(%src: memref<4x4xf32>) {389 %offsets = arith.constant dense<[0]> : vector<1xindex>390 // expected-error@+1 {{op operand #0 must be TensorDesc describing regions of interested data}}391 xegpu.prefetch %src[%offsets]: memref<4x4xf32>, vector<1xindex>392 return393}394 395// -----396func.func @prefetch_offset_wi_2(%src: memref<16xf32>) {397 %offsets = arith.constant dense<[0]> : vector<1xindex>398 %1 = xegpu.create_tdesc %src, %offsets : memref<16xf32>, vector<1xindex>399 -> !xegpu.tensor_desc<1x3xf32, #xegpu.scatter_tdesc_attr<chunk_size = 3>>400 // expected-error@+1 {{offsets not allowed}}401 xegpu.prefetch %1[%offsets]: !xegpu.tensor_desc<1x3xf32, #xegpu.scatter_tdesc_attr<chunk_size = 3>>, vector<1xindex>402 return403}404 405// -----406func.func @prefetch_offset_wi_3(%src: memref<16xf32>) {407 // expected-error@+1 {{Expects offsets}}408 xegpu.prefetch %src: memref<16xf32>409 return410}411 412// -----413func.func @prefetch_offset_wi_4(%src: memref<16xf32>) {414 %offsets = arith.constant dense<[0]> : vector<1xindex>415 // expected-error@+1 {{offset_align_byte only allowed with integer source.}}416 xegpu.prefetch %src[%offsets] <{offset_align_byte = 4}>: memref<16xf32>, vector<1xindex>417 return418}419 420// -----421func.func @prefetch_offset_wi_5(%src: i64) {422 %offsets = arith.constant dense<[0]> : vector<1xindex>423 // expected-error@+1 {{offset_align_byte is required with integer source.}}424 xegpu.prefetch %src[%offsets] : i64, vector<1xindex>425 return426}427 428// -----429func.func @load_gather_offset_sg(%src: memref<?xf16>) {430 %offsets = arith.constant dense<[0, 8, 16, 24]> : vector<4xindex>431 %mask = arith.constant dense<1>: vector<8xi1>432 // expected-error@+1 {{Mask should match value except the chunk size dim}}433 %2 = xegpu.load %src[%offsets], %mask434 : memref<?xf16>, vector<4xindex>, vector<8xi1>435 -> vector<4x2xf16>436 return437}438 439// -----440func.func @load_gather_offset_wi(%src: ui64) {441 %mask = arith.constant dense<1>: vector<1xi1>442 %offsets = arith.constant dense<[0]> : vector<1xindex>443 // expected-error@+1 {{value elements must match chunk size}}444 %2 = xegpu.load %src[%offsets], %mask <{chunk_size = 2}> : ui64, vector<1xindex>, vector<1xi1> -> vector<3xf32>445 return446}447 448// -----449func.func @store_scatter_offset_wi_1(%src: memref<?xf16>) {450 %val = arith.constant dense<2.9>: vector<4xf16>451 %offsets = arith.constant dense<[0]> : vector<1xindex>452 %mask = arith.constant dense<1>: vector<1xi1>453 // expected-error@+1 {{Mask should match value except the chunk size dim}}454 xegpu.store %val, %src[%offsets], %mask455 : vector<4xf16>, memref<?xf16>, vector<1xindex>, vector<1xi1>456 return457}458 459// -----460func.func @store_scatter_offset_wi_2(%src: memref<4x4xf16>) {461 %val = arith.constant dense<2.9>: vector<4xf16>462 %offsets = arith.constant dense<[0]> : vector<1xindex>463 %mask = arith.constant dense<1>: vector<1xi1>464 // expected-error@+1 {{op operand #1 must be TensorDesc describing regions of interested data}}465 xegpu.store %val, %src[%offsets], %mask466 : vector<4xf16>, memref<4x4xf16>, vector<1xindex>, vector<1xi1>467 return468}469 470// -----471func.func @store_scatter_offset_wi_3(%src: memref<16xf16>) {472 %val = arith.constant dense<2.9>: vector<1xf16>473 %mask = arith.constant dense<1>: vector<1xi1>474 // expected-error@+1 {{Expects offsets}}475 xegpu.store %val, %src, %mask476 : vector<1xf16>, memref<16xf16>, vector<1xi1>477 return478}479 480// -----481func.func @store_scatter_offset_wi_4(%src: !xegpu.tensor_desc<1x1xf32, #xegpu.scatter_tdesc_attr<>>) {482 %val = arith.constant dense<2.9>: vector<1xf16>483 %offsets = arith.constant dense<[0]> : vector<1xindex>484 %mask = arith.constant dense<1>: vector<1xi1>485 // expected-error@+1 {{offsets not allowed}}486 xegpu.store %val, %src[%offsets], %mask487 : vector<1xf16>, !xegpu.tensor_desc<1x1xf32, #xegpu.scatter_tdesc_attr<>>, vector<1xindex>, vector<1xi1>488 return489}490 491// -----492func.func @load_gather_offset_wi_4(%src: !xegpu.tensor_desc<1x2xf16, #xegpu.scatter_tdesc_attr<>>) {493 %mask = arith.constant dense<1>: vector<1xi1>494 %offsets = arith.constant dense<[0]> : vector<1xindex>495 // expected-error@+1 {{offsets not allowed}}496 %2 = xegpu.load %src[%offsets], %mask <{chunk_size = 2}> : !xegpu.tensor_desc<1x2xf16, #xegpu.scatter_tdesc_attr<>>, vector<1xindex>, vector<1xi1> -> vector<2xf16>497 return498}499 500// -----501func.func @load_gather_offset_wi_3(%src: ui64) {502 %mask = arith.constant dense<1>: vector<1xi1>503 // expected-error@+1 {{Expects offsets}}504 %2 = xegpu.load %src, %mask <{chunk_size = 2}> : ui64, vector<1xi1> -> vector<2xf16>505 return506}507 508// -----509func.func @load_gather_offset_wi_2(%src: ui64) {510 %mask = arith.constant dense<1>: vector<1xi1>511 %offsets = arith.constant dense<[0]> : vector<1xindex>512 // expected-error@+1 {{value elements must match chunk size}}513 %2 = xegpu.load %src[%offsets], %mask <{chunk_size = 2}> : ui64, vector<1xindex>, vector<1xi1> -> vector<3xf16>514 return515}516 517// -----518func.func @load_gather_offset_wi_1(%src: memref<4x4xf32>) {519 %mask = arith.constant dense<1>: vector<1xi1>520 %offsets = arith.constant dense<[0]> : vector<1xindex>521 // expected-error@+1 {{op operand #0 must be TensorDesc describing regions of interested data}}522 %2 = xegpu.load %src[%offsets], %mask <{chunk_size = 2}> : memref<4x4xf32>, vector<1xindex>, vector<1xi1> -> vector<2xf32>523 return524}525 526// -----527func.func @store_scatter_vc_1(%src: memref<24x32xf32>) {528 %0 = arith.constant dense<1>: vector<4xi1>529 %1 = arith.constant dense<2.9>: vector<4x2xf32>530 %2 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<4x2xf32>531 // expected-error@+1 {{Expects a scattered TensorDesc}}532 xegpu.store %1, %2, %0 <{l1_hint = #xegpu.cache_hint<cached>}>533 : vector<4x2xf32>, !xegpu.tensor_desc<4x2xf32>, vector<4xi1>534 return535}536 537// -----538func.func @store_scatter_vc_2(%src: ui64) {539 %cst = arith.constant dense<[0, 8, 16, 24]>: vector<4xindex>540 %0 = arith.constant dense<1>: vector<4xi1>541 %1 = arith.constant dense<2.9>: vector<4x2xf32>542 %2 = xegpu.create_tdesc %src, %cst : ui64, vector<4xindex>543 -> !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>544 // expected-error@+1 {{invalid l1_hint: #xegpu.cache_hint<streaming>}}545 xegpu.store %1, %2, %0 <{l1_hint = #xegpu.cache_hint<streaming>}> : vector<4x2xf32>,546 !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>, vector<4xi1>547 return548}549 550// -----551func.func @store_scatter_vc_3(%src: ui64) {552 %cst = arith.constant dense<[0, 8, 16, 24]>: vector<4xindex>553 %0 = arith.constant dense<1>: vector<8xi1>554 %1 = arith.constant dense<2.9>: vector<4x2xf32>555 %2 = xegpu.create_tdesc %src, %cst : ui64, vector<4xindex>556 -> !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>557 // expected-error@+1 {{Mask should match TensorDesc except the chunk size dim}}558 xegpu.store %1, %2, %0 : vector<4x2xf32>,559 !xegpu.tensor_desc<4x2xf32, #xegpu.scatter_tdesc_attr<chunk_size = 2>>, vector<8xi1>560 return561}562 563// -----564func.func @dpas_vc_1(%a : vector<8x8xf16>, %b: vector<8x16x2xf16>) {565 // expected-error@+1 {{K-dimension mismatch}}566 %1 = xegpu.dpas %a, %b : vector<8x8xf16>, vector<8x16x2xf16> -> vector<8x16xf32>567 return568}569 570// -----571func.func @dpas_vc_2(%a : vector<8x8x2xf16>, %b: vector<8x16x2xf16>) {572 // expected-error@+1 {{expecting lhs and result to be a 2D vector, and rhs to be either 2D or 3D (packed) vector}}573 %1 = xegpu.dpas %a, %b : vector<8x8x2xf16>, vector<8x16x2xf16> -> vector<8x16xf32>574 return575}576 577// -----578func.func @dpas_3(%a : vector<8x8xf16>, %b: vector<8x16x2xf16>) {579 // expected-error@+1 {{K-dimension mismatch}}580 %1 = xegpu.dpas %a, %b : vector<8x8xf16>, vector<8x16x2xf16> -> vector<8x16xf32>581 return582}583 584// -----585func.func @dpas_4(%a : vector<16x16xf16>, %b: vector<8x16x2xf16>) {586 // expected-error@+1 {{M-dimension mismatch}}587 %1 = xegpu.dpas %a, %b : vector<16x16xf16>, vector<8x16x2xf16> -> vector<8x16xf32>588 return589}590 591// -----592func.func @dpas_5(%a : vector<8x16xf16>, %b: vector<8x8x2xf16>) {593 // expected-error@+1 {{N-dimension mismatch}}594 %1 = xegpu.dpas %a, %b : vector<8x16xf16>, vector<8x8x2xf16> -> vector<8x16xf32>595 return596}597 598// -----599func.func @dpas_simt_1(%a : vector<8xf16>, %b: vector<15xf16>) {600 // expected-error@+1 {{Expecting B operand to be a multiple of 32 bits}}601 %1 = xegpu.dpas %a, %b : vector<8xf16>, vector<15xf16> -> vector<8xf32>602 return603}604 605// -----606func.func @atomic_rmw(%src: ui64, %value : vector<16x4xf32>, %mask : vector<16xi1>) {607 %0 = arith.constant dense<[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]> : vector<16xindex>608 %1 = xegpu.create_tdesc %src, %0 : ui64, vector<16xindex> -> !xegpu.tensor_desc<16x8xf32, #xegpu.scatter_tdesc_attr<chunk_size = 8>>609 // expected-error@+1 {{failed to verify that all of {tensorDesc, value, result} have same shape}}610 xegpu.atomic_rmw addf %1, %mask, %value: !xegpu.tensor_desc<16x8xf32, #xegpu.scatter_tdesc_attr<chunk_size = 8>>, vector<16xi1>, vector<16x4xf32> -> vector<16x8xf32>611 return612}613 614// -----615func.func @tensor_desc_invalid_rank_1(%src: memref<24x32xf32>) {616 %0 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->617 // expected-error@+1 {{expected non-zero rank tensor}}618 !xegpu.tensor_desc<f32>619 return620}621 622// -----623func.func @tensor_desc_1D_invalid_map_layout(%src: memref<24x32xf32>) {624 %0 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->625 // expected-error@+1 {{expected layout rank to match tensor rank}}626 !xegpu.tensor_desc<16xf32, #xegpu.layout<lane_layout = [2, 16], lane_data = [1, 1]>>627 return628}629 630// -----631func.func @tensor_desc_1D_invalid_map_data(%src: memref<24x32xf32>) {632 %0 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->633 // expected-error@+1 {{expected layout rank to match tensor rank}}634 !xegpu.tensor_desc<16xf32, #xegpu.layout<lane_layout = [1, 16], lane_data = [2, 1]>>635 return636}637 638// -----639func.func @tensor_desc_invalid_map_layout(%src: memref<24x32xf32>) {640 %0 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->641 // expected-error@+1 {{cannot distribute [4, 8] using #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>}}642 !xegpu.tensor_desc<4x8xf32, #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>>643 return644}645 646// -----647func.func @tensor_desc_invalid_map_layout_1(%src: memref<24x32xf32>) {648 %0 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->649 // expected-error@+1 {{cannot distribute [4, 8] using #xegpu.layout<lane_layout = [8, 2], lane_data = [1, 1]>}}650 !xegpu.tensor_desc<4x8xf32, #xegpu.layout<lane_layout = [8, 2], lane_data = [1, 1]>>651 return652}653 654// -----655func.func @tensor_desc_invalid_map_data(%src: memref<24x32xf32>) {656 %0 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->657 // expected-error@+1 {{cannot distribute [4, 8] using #xegpu.layout<lane_layout = [2, 8], lane_data = [4, 1]>}}658 !xegpu.tensor_desc<4x8xf32, #xegpu.layout<lane_layout = [2, 8], lane_data = [4, 1]>>659 return660}661 662// -----663func.func @tensor_desc_invalid_map_data_1(%src: memref<24x32xf32>) {664 %0 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->665 // expected-error@+1 {{cannot distribute [4, 8] using #xegpu.layout<lane_layout = [8, 2], lane_data = [1, 2]>}}666 !xegpu.tensor_desc<4x8xf32, #xegpu.layout<lane_layout = [8, 2], lane_data = [1, 2]>>667 return668}669 670// -----671func.func @tensor_desc_scatter_invalid_chunk_size_1D(%src: ui64, %offsets: vector<16xindex>) {672 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->673 // expected-error@+1 {{expected non-contiguous elements for 1D tensor}}674 !xegpu.tensor_desc<16xf32,675 #xegpu.scatter_tdesc_attr<chunk_size = 2>,676 #xegpu.layout<lane_layout = [1, 8], lane_data = [1, 2]>>677 return678}679 680// -----681func.func @tensor_desc_scatter_invalid_chunk_size_2D(%src: ui64, %offsets: vector<16xindex>) {682 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->683 // expected-error@+1 {{expected last dim of tensor to match chunk size}}684 !xegpu.tensor_desc<16x2xf32,685 #xegpu.scatter_tdesc_attr<chunk_size = 4>,686 #xegpu.layout<lane_layout = [8, 1], lane_data = [1, 2]>>687 return688}689 690// -----691func.func @convert_layout_unmatch(%a: vector<32x64xf16>) {692 // expected-error@+1 {{expected input layout and target layout be WgLayout or SgLayout at the same time}}693 %2 = xegpu.convert_layout %a <{input_layout = #xegpu.layout<sg_layout = [2, 4], sg_data = [16, 16], lane_layout = [1, 16], lane_data = [1, 1]>,694 target_layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>}> : vector<32x64xf16>695 gpu.return696}697 698// -----699func.func @tensor_desc_invalid_layout_attr(%src: ui64, %offsets: vector<16xindex>) {700 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->701 !xegpu.tensor_desc<16x2xf32,702 #xegpu.scatter_tdesc_attr<chunk_size = 2>,703 // expected-error@+1 {{expected at least one of sg_layout, inst_data or lane_layout}}704 #xegpu.layout<sg_data = [16, 2], lane_data = [1, 2]>>705 return706}707 708// -----709func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {710 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->711 !xegpu.tensor_desc<16x2xf32,712 #xegpu.scatter_tdesc_attr<chunk_size = 2>,713 // expected-error@+1 {{expected sg_layout and lane_layout to have the same rank}}714 #xegpu.layout<sg_layout = [1, 1, 1], sg_data = [16, 2, 1], lane_layout = [8, 1], lane_data = [1, 2]>>715 return716}717 718// -----719func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {720 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->721 !xegpu.tensor_desc<16x2xf32,722 #xegpu.scatter_tdesc_attr<chunk_size = 2>,723 // expected-error@+1 {{expected sg_layout and inst_data to have the same rank}}724 #xegpu.layout<sg_layout = [1, 1, 1], sg_data = [16, 2, 1], inst_data = [16, 2]>>725 return726}727 728// -----729func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {730 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->731 !xegpu.tensor_desc<16x2xf32,732 #xegpu.scatter_tdesc_attr<chunk_size = 2>,733 // expected-error@+1 {{expected inst_data and lane_layout to have the same rank}}734 #xegpu.layout<inst_data = [16, 2, 1], lane_layout = [8, 1], lane_data = [1, 2]>>735 return736}737 738// -----739func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {740 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->741 !xegpu.tensor_desc<16x2xf32,742 #xegpu.scatter_tdesc_attr<chunk_size = 2>,743 // expected-error@+1 {{expected lane_data and lane_layout to have the same rank}}744 #xegpu.layout<inst_data = [16, 2], lane_layout = [8, 1], lane_data = [1, 2, 1]>>745 return746}747 748// -----749func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {750 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->751 !xegpu.tensor_desc<16x2xf32,752 #xegpu.scatter_tdesc_attr<chunk_size = 2>,753 // expected-error@+1 {{expected sg_data and sg_layout to have the same rank}}754 #xegpu.layout<sg_layout = [1, 1], sg_data = [16, 2, 1], inst_data = [16, 2]>>755 return756}757 758// -----759func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {760 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->761 // expected-error@+1 {{expected layout rank to match tensor rank}}762 !xegpu.tensor_desc<16x2xf32,763 #xegpu.scatter_tdesc_attr<chunk_size = 2>,764 #xegpu.layout<sg_layout = [1], sg_data = [32], inst_data = [16]>>765 return766}767 768// -----769func.func @tensor_desc_invalid_sg_data(%src: ui64, %offsets: vector<16xindex>) {770 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->771 !xegpu.tensor_desc<16x2xf32,772 #xegpu.scatter_tdesc_attr<chunk_size = 2>,773 // expected-error@+1 {{expected sg_layout being used with sg_data}}774 #xegpu.layout<sg_data = [16, 2], lane_layout = [8, 1], lane_data = [1, 2]>>775 return776}777 778// -----779func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {780 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->781 !xegpu.tensor_desc<16x2xf32,782 #xegpu.scatter_tdesc_attr<chunk_size = 2>,783 // expected-error@+1 {{expected lane_layout being used with lane_data}}784 #xegpu.layout<inst_data = [16, 2], lane_data = [1, 2]>>785 return786}787 788// -----789func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {790 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->791 !xegpu.tensor_desc<16x2xf32,792 #xegpu.scatter_tdesc_attr<chunk_size = 2>,793 // expected-error@+1 {{expected sg_layout/lane_layout being used with order}}794 #xegpu.layout<inst_data = [16, 2], order = [0, 1]>>795 return796}797 798// -----799func.func @tensor_desc_rank_mismatch(%src: ui64, %offsets: vector<16xindex>) {800 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->801 !xegpu.tensor_desc<16x2xf32,802 #xegpu.scatter_tdesc_attr<chunk_size = 2>,803 // expected-error@+1 {{expected order and sg_layout to have the same rank}}804 #xegpu.layout<sg_layout = [1, 1], sg_data = [16, 2], order = [0, 1, 2]>>805 return806}807 808// -----809func.func @tensor_desc_invalid_sg_data(%src: ui64, %offsets: vector<16xindex>) {810 %1 = xegpu.create_tdesc %src, %offsets : ui64, vector<16xindex> ->811 !xegpu.tensor_desc<16x2xf32,812 #xegpu.scatter_tdesc_attr<chunk_size = 2>,813 // expected-error@+1 {{expected order and lane_layout to have the same rank}}814 #xegpu.layout<lane_layout = [8, 1], lane_data = [1, 2], order = [0, 1, 2]>>815 return816}817 818// -----819#l = #xegpu.layout<sg_layout = [16, 1, 1], sg_data = [1, 8, 2]>820// expected-error@+1 {{repeated dim (2) in slice attribute}}821#s = #xegpu.slice<#l, dims = [2, 2]>822func.func @slice_attr_repeat_dim() {823 %offsets = arith.constant {layout_result_0 = #s} dense<0.8> : vector<16x8xindex>824 return825}826 827// -----828#l = #xegpu.layout<sg_layout = [16, 1, 1], sg_data = [1, 8, 2]>829// expected-error@+1 {{invalid dim (3) in slice attribute}}830#s = #xegpu.slice<#l, dims = [3]>831func.func @slice_attr_repeat_dim() {832 %offsets = arith.constant {layout_result_0 = #s} dense<0.8> : vector<16x8xindex>833 return834}835 836// -----837func.func @create_mem_desc_non_slm() {838 %m = memref.alloca() {alignment = 1024} : memref<2048xi8, 1>839 // expected-error@+1 {{operand #0 must be reside in share memory and statically 1d shaped memref }}840 %mem_desc = xegpu.create_mem_desc %m : memref<2048xi8, 1> -> !xegpu.mem_desc<16x64xf16>841 return842}843 844// -----845func.func @create_mem_desc_mismatch_sizes() {846 %m = memref.alloca() {alignment = 1024} : memref<2048xi8, 3>847 // expected-error@+1 {{failed to verify that all of {source, mem_desc} have same size in bits}}848 %mem_desc = xegpu.create_mem_desc %m : memref<2048xi8, 3> -> !xegpu.mem_desc<16x32xf16>849 return850}851 852// -----853func.func @load_mem_desc_mismatch_element_type(%arg0: !xegpu.mem_desc<16x64xf16>) {854 // expected-error@+1 {{failed to verify that all of {mem_desc, res} have same element type}}855 %data = xegpu.load_matrix %arg0[8, 8]: !xegpu.mem_desc<16x64xf16> -> vector<8x16xf32>856 return857}858 859// -----860func.func @load_mem_desc_invalid_result_size(%arg0: !xegpu.mem_desc<16x64xf16>) {861 // expected-error@+1 {{data shape must not exceed mem_desc shape}}862 %data = xegpu.load_matrix %arg0[8, 8]: !xegpu.mem_desc<16x64xf16> -> vector<32x16xf16>863 return864}865 866// -----867func.func @load_mem_desc_invalid_rank(%arg0: !xegpu.mem_desc<64xf16>) {868 // expected-error@+1 {{mem_desc must be 2D}}869 %data = xegpu.load_matrix %arg0[16]: !xegpu.mem_desc<64xf16> -> vector<16xf16>870 return871}872 873// -----874func.func @store_mem_desc_mismatch_element_type(%arg0: !xegpu.mem_desc<16x64xf16>, %arg1: vector<16x16xf32>) {875 // expected-error@+1 {{failed to verify that all of {mem_desc, data} have same element type}}876 xegpu.store_matrix %arg1, %arg0[8, 8] : vector<16x16xf32>, !xegpu.mem_desc<16x64xf16>877 return878}879 880// -----881func.func @store_mem_desc_invalid_data_size(%arg0: !xegpu.mem_desc<16x64xf16>, %arg1: vector<32x32xf16>) {882 // expected-error@+1 {{data shape must not exceed mem_desc shape}}883 xegpu.store_matrix %arg1, %arg0[8, 8] : vector<32x32xf16>, !xegpu.mem_desc<16x64xf16>884 return885}886 887// -----888func.func @store_mem_desc_invalid_rank(%arg0: !xegpu.mem_desc<64xf16>, %arg1: vector<32xf16>) {889 // expected-error@+1 {{mem_desc must be 2D.}}890 xegpu.store_matrix %arg1, %arg0[32] : vector<32xf16>, !xegpu.mem_desc<64xf16>891 return892}893 894// -----895func.func @simt_store_matrix_vector_nonlinear(%arg0: !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [32, 1]>>, %arg1: vector<2x16xf32>) {896 // expected-error@+1 {{With subgroup_block_io, accessed data must be contiguous and coalesced}}897 xegpu.store_matrix %arg1, %arg0[0, 0] {subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [2, 1]>} :898 vector<2x16xf32>, !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [32, 1]>>899 return900}901 902// -----903func.func @simt_store_matrix_vector_noncoalesced(%arg0: !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [1, 32], block = [1, 16]>>, %arg1: vector<16x2xf32>) {904 // expected-error@+1 {{With subgroup_block_io, the distributed dimensions must be contiguous}}905 xegpu.store_matrix %arg1, %arg0[0, 0] {subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 2]>} :906 vector<16x2xf32>, !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [1, 32], block = [1, 16]>>907 return908}909 910// -----911func.func @simt_store_matrix_vector_noncoalesced(%arg0: !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [32, 1], block = [1, 17]>>, %arg1: vector<16x2xf32>) {912 // expected-error@+1 {{With subgroup_block_io, the block shape must match the lane layout}}913 xegpu.store_matrix %arg1, %arg0[0, 0] {subgroup_block_io, layout = #xegpu.layout<lane_layout = [1, 16], lane_data = [1, 1]>} :914 vector<16x2xf32>, !xegpu.mem_desc<32x32xf32, #xegpu.mem_layout<stride = [32, 1], block = [1, 17]>>915 return916}917