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1// RUN: mlir-opt --test-xegpu-layout-interface --cse -split-input-file %s | FileCheck %s2 3gpu.module @test {4 gpu.func @slice_attr() -> vector<128xindex> {5 // CHECK-DAG: %[[SGID:.*]] = gpu.subgroup_id : index6 // CHECK-DAG: %[[DIVU:.*]] = index.divu %[[SGID]], %[[C8:.*]]7 // CHECK-DAG: %[[REMU:.*]] = index.remu %[[DIVU]], %[[C4:.*]]8 // CHECK-DAG: %[[MUL:.*]] = index.mul %[[REMU]], %[[C32:.*]]9 // CHECK-DAG: %[[MOD:.*]] = index.remu %[[MUL]], %[[C128:.*]]10 // CHECK-DAG: %[[BASE:.*]] = vector.step : vector<32xindex>11 // CHECK-DAG: %[[CAST:.*]] = vector.broadcast %[[MOD]] : index to vector<32xindex>12 // CHECK-DAG: %[[ADD:.*]] = arith.addi %[[BASE]], %[[CAST]] : vector<32xindex>13 %step = vector.step {layout_result_0 = #xegpu.slice<#xegpu.layout<sg_layout = [4, 8], sg_data = [32, 32]>, dims = [1]>}: vector<128xindex>14 gpu.return %step : vector<128xindex>15 }16 17 gpu.func @nested_slice_attr() -> vector<128xindex> {18 // CHECK-DAG: %[[SGID:.*]] = gpu.subgroup_id : index19 // CHECK-DAG: %[[DIVU1:.*]] = index.divu %[[SGID]], %[[C1:.*]]20 // CHECK-DAG: %[[DIVU2:.*]] = index.divu %[[DIVU1]], %[[C8:.*]]21 // CHECK-DAG: %[[REMU:.*]] = index.remu %[[DIVU2]], %[[C4:.*]]22 // CHECK-DAG: %[[MUL:.*]] = index.mul %[[REMU]], %[[C32:.*]]23 // CHECK-DAG: %[[MOD:.*]] = index.remu %[[MUL]], %[[C128:.*]]24 // CHECK-DAG: %[[BASE:.*]] = vector.step : vector<32xindex>25 // CHECK-DAG: %[[CAST:.*]] = vector.broadcast %[[MOD]] : index to vector<32xindex>26 // CHECK-DAG: %[[ADD:.*]] = arith.addi %[[BASE]], %[[CAST]] : vector<32xindex>27 %0 = vector.step {layout_result_0 = #xegpu.slice<#xegpu.slice<#xegpu.layout<sg_layout = [4, 8, 1], sg_data = [32, 32, 1]>, dims = [2]>, dims = [1]>} : vector<128xindex>28 gpu.return %0 : vector<128xindex>29 }30 31}32 33