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1; RUN: mlir-translate -import-llvm -split-input-file %s | FileCheck %s2 3; Verify the import works if the blocks are not topologically sorted.4; CHECK-LABEL: @dominance_order5; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]6define i64 @dominance_order(i64 %arg1) {7 ; CHECK: llvm.br ^[[BB2:.+]]8 br label %bb29bb1:10 ; CHECK: ^[[BB1:[a-zA-Z0-9]+]]:11 ; CHECK: llvm.return %[[VAL1:.+]] : i6412 ret i64 %113bb2:14 ; CHECK: ^[[BB2]]:15 ; CHECK: %[[VAL1]] = llvm.add %[[ARG1]]16 %1 = add i64 %arg1, 317 ; CHECK: llvm.br ^[[BB1]]18 br label %bb119}20 21; // -----22 23; CHECK-LABEL: @block_argument24; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]25; CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]26define i64 @block_argument(i1 %arg1, i64 %arg2) {27entry:28 ; CHECK: llvm.cond_br %[[ARG1]]29 ; CHECK-SAME: ^[[BB1:.+]](%[[ARG2]] : i64)30 ; CHECK-SAME: ^[[BB2:.+]]31 br i1 %arg1, label %bb1, label %bb232bb1:33 ; CHECK: ^[[BB1]](%[[BA1:.+]]: i64):34 ; CHECK: llvm.return %[[BA1]] : i6435 %0 = phi i64 [ %arg2, %entry ], [ %1, %bb2 ]36 ret i64 %037bb2:38 ; CHECK: ^[[BB2]]:39 ; CHECK: %[[VAL1:.+]] = llvm.add %[[ARG2]]40 ; CHECK: llvm.br ^[[BB1]](%[[VAL1]]41 %1 = add i64 %arg2, 342 br label %bb143}44 45; // -----46 47; CHECK-LABEL: @simple_switch(48; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]49define i64 @simple_switch(i64 %arg1) {50 ; CHECK: %[[VAL1:.+]] = llvm.add51 ; CHECK: %[[VAL2:.+]] = llvm.sub52 ; CHECK: %[[VAL3:.+]] = llvm.mul53 %1 = add i64 %arg1, 4254 %2 = sub i64 %arg1, 4255 %3 = mul i64 %arg1, 4256 ; CHECK: llvm.switch %[[ARG1]] : i64, ^[[BBD:.+]] [57 ; CHECK: 0: ^[[BB1:.+]],58 ; CHECK: 9: ^[[BB2:.+]]59 ; CHECK: ]60 switch i64 %arg1, label %bbd [61 i64 0, label %bb162 i64 9, label %bb263 ]64bb1:65 ; CHECK: ^[[BB1]]:66 ; CHECK: llvm.return %[[VAL1]]67 ret i64 %168bb2:69 ; CHECK: ^[[BB2]]:70 ; CHECK: llvm.return %[[VAL2]]71 ret i64 %272bbd:73 ; CHECK: ^[[BBD]]:74 ; CHECK: llvm.return %[[VAL3]]75 ret i64 %376}77 78; // -----79 80; CHECK-LABEL: @switch_args81; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]82define i32 @switch_args(i32 %arg1) {83entry:84 ; CHECK: %[[VAL1:.+]] = llvm.add85 ; CHECK: %[[VAL2:.+]] = llvm.sub86 ; CHECK: %[[VAL3:.+]] = llvm.mul87 %0 = add i32 %arg1, 4288 %1 = sub i32 %arg1, 4289 %2 = mul i32 %arg1, 4290 ; CHECK: llvm.switch %[[ARG1]] : i32, ^[[BBD:.+]](%[[VAL3]] : i32) [91 ; CHECK: 0: ^[[BB1:.+]](%[[VAL1]], %[[VAL2]] : i32, i32)92 ; CHECK: ]93 switch i32 %arg1, label %bbd [94 i32 0, label %bb195 ]96bb1:97 ; CHECK: ^[[BB1]](%[[BA1:.+]]: i32, %[[BA2:.+]]: i32):98 ; CHECK: %[[VAL1:.*]] = llvm.add %[[BA1]], %[[BA2]] : i3299 %3 = phi i32 [%0, %entry]100 %4 = phi i32 [%1, %entry]101 %5 = add i32 %3, %4102 ; CHECK: llvm.br ^[[BBD]](%[[VAL1]]103 br label %bbd104bbd:105 ; CHECK: ^[[BBD]](%[[BA3:.+]]: i32):106 ; CHECK: llvm.return %[[BA3]]107 %6 = phi i32 [%2, %entry], [%5, %bb1]108 ret i32 %6109}110