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1// RUN: mlir-translate --mlir-to-llvmir %s | FileCheck %s2 3// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_sdot4llvm.func @arm_sve_sdot(%arg0: vector<[16]xi8>,5 %arg1: vector<[16]xi8>,6 %arg2: vector<[4]xi32>)7 -> vector<[4]xi32> {8 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.nxv4i32(<vscale x 49 %0 = "arm_sve.intr.sdot"(%arg2, %arg0, %arg1) :10 (vector<[4]xi32>, vector<[16]xi8>, vector<[16]xi8>)11 -> vector<[4]xi32>12 llvm.return %0 : vector<[4]xi32>13}14 15// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_smmla16llvm.func @arm_sve_smmla(%arg0: vector<[16]xi8>,17 %arg1: vector<[16]xi8>,18 %arg2: vector<[4]xi32>)19 -> vector<[4]xi32> {20 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 421 %0 = "arm_sve.intr.smmla"(%arg2, %arg0, %arg1) :22 (vector<[4]xi32>, vector<[16]xi8>, vector<[16]xi8>)23 -> vector<[4]xi32>24 llvm.return %0 : vector<[4]xi32>25}26 27// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_udot28llvm.func @arm_sve_udot(%arg0: vector<[16]xi8>,29 %arg1: vector<[16]xi8>,30 %arg2: vector<[4]xi32>)31 -> vector<[4]xi32> {32 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.udot.nxv4i32(<vscale x 433 %0 = "arm_sve.intr.udot"(%arg2, %arg0, %arg1) :34 (vector<[4]xi32>, vector<[16]xi8>, vector<[16]xi8>)35 -> vector<[4]xi32>36 llvm.return %0 : vector<[4]xi32>37}38 39// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_ummla40llvm.func @arm_sve_ummla(%arg0: vector<[16]xi8>,41 %arg1: vector<[16]xi8>,42 %arg2: vector<[4]xi32>)43 -> vector<[4]xi32> {44 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 445 %0 = "arm_sve.intr.ummla"(%arg2, %arg0, %arg1) :46 (vector<[4]xi32>, vector<[16]xi8>, vector<[16]xi8>)47 -> vector<[4]xi32>48 llvm.return %0 : vector<[4]xi32>49}50 51// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_usmmla52llvm.func @arm_sve_usmmla(%arg0: vector<[16]xi8>,53 %arg1: vector<[16]xi8>,54 %arg2: vector<[4]xi32>)55 -> vector<[4]xi32> {56 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 457 %0 = "arm_sve.intr.usmmla"(%arg2, %arg0, %arg1) :58 (vector<[4]xi32>, vector<[16]xi8>, vector<[16]xi8>)59 -> vector<[4]xi32>60 llvm.return %0 : vector<[4]xi32>61}62 63// CHECK-LABEL: define <vscale x 4 x float> @arm_sve_bfmmla64llvm.func @arm_sve_bfmmla(%arg0: vector<[8]xbf16>,65 %arg1: vector<[8]xbf16>,66 %arg2: vector<[4]xf32>)67 -> vector<[4]xf32> {68 // CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.bfmmla(<vscale x 4 x float>69 %0 = "arm_sve.intr.bfmmla"(%arg2, %arg0, %arg1) :70 (vector<[4]xf32>, vector<[8]xbf16>, vector<[8]xbf16>)71 -> vector<[4]xf32>72 llvm.return %0 : vector<[4]xf32>73}74 75// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_arithi76llvm.func @arm_sve_arithi(%arg0: vector<[4]xi32>,77 %arg1: vector<[4]xi32>,78 %arg2: vector<[4]xi32>)79 -> vector<[4]xi32> {80 // CHECK: mul <vscale x 4 x i32>81 %0 = llvm.mul %arg0, %arg1 : vector<[4]xi32>82 // CHECK: add <vscale x 4 x i32>83 %1 = llvm.add %0, %arg2 : vector<[4]xi32>84 llvm.return %1 : vector<[4]xi32>85}86 87// CHECK-LABEL: define <vscale x 4 x float> @arm_sve_arithf88llvm.func @arm_sve_arithf(%arg0: vector<[4]xf32>,89 %arg1: vector<[4]xf32>,90 %arg2: vector<[4]xf32>)91 -> vector<[4]xf32> {92 // CHECK: fmul <vscale x 4 x float>93 %0 = llvm.fmul %arg0, %arg1 : vector<[4]xf32>94 // CHECK: fadd <vscale x 4 x float>95 %1 = llvm.fadd %0, %arg2 : vector<[4]xf32>96 llvm.return %1 : vector<[4]xf32>97}98 99// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_arithi_masked100llvm.func @arm_sve_arithi_masked(%arg0: vector<[4]xi32>,101 %arg1: vector<[4]xi32>,102 %arg2: vector<[4]xi32>,103 %arg3: vector<[4]xi32>,104 %arg4: vector<[4]xi32>,105 %arg5: vector<[4]xi1>)106 -> vector<[4]xi32> {107 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32108 %0 = "arm_sve.intr.add"(%arg5, %arg0, %arg1) : (vector<[4]xi1>,109 vector<[4]xi32>,110 vector<[4]xi32>)111 -> vector<[4]xi32>112 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32113 %1 = "arm_sve.intr.sub"(%arg5, %0, %arg1) : (vector<[4]xi1>,114 vector<[4]xi32>,115 vector<[4]xi32>)116 -> vector<[4]xi32>117 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32118 %2 = "arm_sve.intr.mul"(%arg5, %1, %arg3) : (vector<[4]xi1>,119 vector<[4]xi32>,120 vector<[4]xi32>)121 -> vector<[4]xi32>122 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32123 %3 = "arm_sve.intr.sdiv"(%arg5, %2, %arg4) : (vector<[4]xi1>,124 vector<[4]xi32>,125 vector<[4]xi32>)126 -> vector<[4]xi32>127 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32128 %4 = "arm_sve.intr.udiv"(%arg5, %3, %arg4) : (vector<[4]xi1>,129 vector<[4]xi32>,130 vector<[4]xi32>)131 -> vector<[4]xi32>132 llvm.return %4 : vector<[4]xi32>133}134 135// CHECK-LABEL: define <vscale x 4 x float> @arm_sve_arithf_masked136llvm.func @arm_sve_arithf_masked(%arg0: vector<[4]xf32>,137 %arg1: vector<[4]xf32>,138 %arg2: vector<[4]xf32>,139 %arg3: vector<[4]xf32>,140 %arg4: vector<[4]xf32>,141 %arg5: vector<[4]xi1>)142 -> vector<[4]xf32> {143 // CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32144 %0 = "arm_sve.intr.fadd"(%arg5, %arg0, %arg1) : (vector<[4]xi1>,145 vector<[4]xf32>,146 vector<[4]xf32>)147 -> vector<[4]xf32>148 // CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32149 %1 = "arm_sve.intr.fsub"(%arg5, %0, %arg2) : (vector<[4]xi1>,150 vector<[4]xf32>,151 vector<[4]xf32>)152 -> vector<[4]xf32>153 // CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32154 %2 = "arm_sve.intr.fmul"(%arg5, %1, %arg3) : (vector<[4]xi1>,155 vector<[4]xf32>,156 vector<[4]xf32>)157 -> vector<[4]xf32>158 // CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32159 %3 = "arm_sve.intr.fdiv"(%arg5, %2, %arg4) : (vector<[4]xi1>,160 vector<[4]xf32>,161 vector<[4]xf32>)162 -> vector<[4]xf32>163 llvm.return %3 : vector<[4]xf32>164}165 166// CHECK-LABEL: define <vscale x 4 x i1> @arm_sve_mask_genf167llvm.func @arm_sve_mask_genf(%arg0: vector<[4]xf32>,168 %arg1: vector<[4]xf32>)169 -> vector<[4]xi1> {170 // CHECK: fcmp oeq <vscale x 4 x float>171 %0 = llvm.fcmp "oeq" %arg0, %arg1 : vector<[4]xf32>172 llvm.return %0 : vector<[4]xi1>173}174 175// CHECK-LABEL: define <vscale x 4 x i1> @arm_sve_mask_geni176llvm.func @arm_sve_mask_geni(%arg0: vector<[4]xi32>,177 %arg1: vector<[4]xi32>)178 -> vector<[4]xi1> {179 // CHECK: icmp uge <vscale x 4 x i32>180 %0 = llvm.icmp "uge" %arg0, %arg1 : vector<[4]xi32>181 llvm.return %0 : vector<[4]xi1>182}183 184// CHECK-LABEL: define <vscale x 4 x i32> @arm_sve_abs_diff185llvm.func @arm_sve_abs_diff(%arg0: vector<[4]xi32>,186 %arg1: vector<[4]xi32>)187 -> vector<[4]xi32> {188 // CHECK: sub <vscale x 4 x i32>189 %0 = llvm.sub %arg0, %arg0 : vector<[4]xi32>190 // CHECK: icmp sge <vscale x 4 x i32>191 %1 = llvm.icmp "sge" %arg0, %arg1 : vector<[4]xi32>192 // CHECK: icmp slt <vscale x 4 x i32>193 %2 = llvm.icmp "slt" %arg0, %arg1 : vector<[4]xi32>194 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32195 %3 = "arm_sve.intr.sub"(%1, %arg0, %arg1) : (vector<[4]xi1>,196 vector<[4]xi32>,197 vector<[4]xi32>)198 -> vector<[4]xi32>199 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32200 %4 = "arm_sve.intr.sub"(%2, %arg1, %arg0) : (vector<[4]xi1>,201 vector<[4]xi32>,202 vector<[4]xi32>)203 -> vector<[4]xi32>204 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32205 %5 = "arm_sve.intr.add"(%1, %0, %3) : (vector<[4]xi1>,206 vector<[4]xi32>,207 vector<[4]xi32>)208 -> vector<[4]xi32>209 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32210 %6 = "arm_sve.intr.add"(%2, %5, %4) : (vector<[4]xi1>,211 vector<[4]xi32>,212 vector<[4]xi32>)213 -> vector<[4]xi32>214 llvm.return %6 : vector<[4]xi32>215}216 217// CHECK-LABEL: define void @memcopy218llvm.func @memcopy(%arg0: !llvm.ptr, %arg1: !llvm.ptr,219 %arg2: i64, %arg3: i64, %arg4: i64,220 %arg5: !llvm.ptr, %arg6: !llvm.ptr,221 %arg7: i64, %arg8: i64, %arg9: i64,222 %arg10: i64) {223 %0 = llvm.mlir.undef : !llvm.struct<(ptr, ptr, i64,224 array<1 x i64>, array<1 x i64>)>225 %1 = llvm.insertvalue %arg0, %0[0] : !llvm.struct<(ptr, ptr, i64,226 array<1 x i64>,227 array<1 x i64>)>228 %2 = llvm.insertvalue %arg1, %1[1] : !llvm.struct<(ptr, ptr, i64,229 array<1 x i64>,230 array<1 x i64>)>231 %3 = llvm.insertvalue %arg2, %2[2] : !llvm.struct<(ptr, ptr, i64,232 array<1 x i64>,233 array<1 x i64>)>234 %4 = llvm.insertvalue %arg3, %3[3, 0] : !llvm.struct<(ptr, ptr, i64,235 array<1 x i64>,236 array<1 x i64>)>237 %5 = llvm.insertvalue %arg4, %4[4, 0] : !llvm.struct<(ptr, ptr, i64,238 array<1 x i64>,239 array<1 x i64>)>240 %6 = llvm.mlir.undef : !llvm.struct<(ptr, ptr, i64,241 array<1 x i64>,242 array<1 x i64>)>243 %7 = llvm.insertvalue %arg5, %6[0] : !llvm.struct<(ptr, ptr, i64,244 array<1 x i64>,245 array<1 x i64>)>246 %8 = llvm.insertvalue %arg6, %7[1] : !llvm.struct<(ptr, ptr, i64,247 array<1 x i64>,248 array<1 x i64>)>249 %9 = llvm.insertvalue %arg7, %8[2] : !llvm.struct<(ptr, ptr, i64,250 array<1 x i64>,251 array<1 x i64>)>252 %10 = llvm.insertvalue %arg8, %9[3, 0] : !llvm.struct<(ptr, ptr, i64,253 array<1 x i64>,254 array<1 x i64>)>255 %11 = llvm.insertvalue %arg9, %10[4, 0] : !llvm.struct<(ptr, ptr, i64,256 array<1 x i64>,257 array<1 x i64>)>258 %12 = llvm.mlir.constant(0 : index) : i64259 %13 = llvm.mlir.constant(4 : index) : i64260 // CHECK: [[VL:%[0-9]+]] = call i64 @llvm.vscale.i64()261 %14 = "llvm.intr.vscale"() : () -> i64262 // CHECK: mul i64 [[VL]], 4263 %15 = llvm.mul %14, %13 : i64264 llvm.br ^bb1(%12 : i64)265^bb1(%16: i64):266 %17 = llvm.icmp "slt" %16, %arg10 : i64267 llvm.cond_br %17, ^bb2, ^bb3268^bb2:269 // CHECK: extractvalue { ptr, ptr, i64, [1 x i64], [1 x i64] }270 %18 = llvm.extractvalue %5[1] : !llvm.struct<(ptr, ptr, i64,271 array<1 x i64>,272 array<1 x i64>)>273 // CHECK: getelementptr float, ptr274 %19 = llvm.getelementptr %18[%16] : (!llvm.ptr, i64) -> !llvm.ptr, f32275 // CHECK: load <vscale x 4 x float>, ptr276 %21 = llvm.load %19 : !llvm.ptr -> vector<[4]xf32>277 // CHECK: extractvalue { ptr, ptr, i64, [1 x i64], [1 x i64] }278 %22 = llvm.extractvalue %11[1] : !llvm.struct<(ptr, ptr, i64,279 array<1 x i64>,280 array<1 x i64>)>281 // CHECK: getelementptr float, ptr282 %23 = llvm.getelementptr %22[%16] : (!llvm.ptr, i64) -> !llvm.ptr, f32283 // CHECK: store <vscale x 4 x float> %{{[0-9]+}}, ptr %{{[0-9]+}}284 llvm.store %21, %23 : vector<[4]xf32>, !llvm.ptr285 %25 = llvm.add %16, %15 : i64286 llvm.br ^bb1(%25 : i64)287^bb3:288 llvm.return289}290 291// CHECK-LABEL: define i64 @get_vector_scale()292llvm.func @get_vector_scale() -> i64 {293 // CHECK: call i64 @llvm.vscale.i64()294 %0 = "llvm.intr.vscale"() : () -> i64295 llvm.return %0 : i64296}297 298// CHECK-LABEL: @arm_sve_convert_from_svbool(299// CHECK-SAME: <vscale x 16 x i1> %[[SVBOOL:[0-9]+]])300llvm.func @arm_sve_convert_from_svbool(%nxv16i1 : vector<[16]xi1>) {301 // CHECK: %[[RES0:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %[[SVBOOL]])302 %res0 = "arm_sve.intr.convert.from.svbool"(%nxv16i1)303 : (vector<[16]xi1>) -> vector<[8]xi1>304 // CHECK: %[[RES1:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %[[SVBOOL]])305 %res1 = "arm_sve.intr.convert.from.svbool"(%nxv16i1)306 : (vector<[16]xi1>) -> vector<[4]xi1>307 // CHECK: %[[RES2:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %[[SVBOOL]])308 %res2 = "arm_sve.intr.convert.from.svbool"(%nxv16i1)309 : (vector<[16]xi1>) -> vector<[2]xi1>310 // CHECK: %[[RES3:.*]] = call <vscale x 1 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv1i1(<vscale x 16 x i1> %[[SVBOOL]])311 %res3 = "arm_sve.intr.convert.from.svbool"(%nxv16i1)312 : (vector<[16]xi1>) -> vector<[1]xi1>313 llvm.return314}315 316// CHECK-LABEL: arm_sve_convert_to_svbool(317// CHECK-SAME: <vscale x 8 x i1> %[[P8:[0-9]+]],318// CHECK-SAME: <vscale x 4 x i1> %[[P4:[0-9]+]],319// CHECK-SAME: <vscale x 2 x i1> %[[P2:[0-9]+]],320// CHECK-SAME: <vscale x 1 x i1> %[[P1:[0-9]+]])321llvm.func @arm_sve_convert_to_svbool(322 %nxv8i1 : vector<[8]xi1>,323 %nxv4i1 : vector<[4]xi1>,324 %nxv2i1 : vector<[2]xi1>,325 %nxv1i1 : vector<[1]xi1>326) {327 // CHECK-NEXT: %[[RES0:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[P8]])328 %res0 = "arm_sve.intr.convert.to.svbool"(%nxv8i1)329 : (vector<[8]xi1>) -> vector<[16]xi1>330 // CHECK-NEXT: %[[RES1:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[P4]])331 %res1 = "arm_sve.intr.convert.to.svbool"(%nxv4i1)332 : (vector<[4]xi1>) -> vector<[16]xi1>333 // CHECK-NEXT: %[[RES2:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[P2]])334 %res2 = "arm_sve.intr.convert.to.svbool"(%nxv2i1)335 : (vector<[2]xi1>) -> vector<[16]xi1>336 // CHECK-NEXT: %[[RES3:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv1i1(<vscale x 1 x i1> %[[P1]])337 %res3 = "arm_sve.intr.convert.to.svbool"(%nxv1i1)338 : (vector<[1]xi1>) -> vector<[16]xi1>339 llvm.return340}341 342// CHECK-LABEL: arm_sve_zip_x2(343// CHECK-SAME: <vscale x 16 x i8> %[[V1:[0-9]+]],344// CHECK-SAME: <vscale x 8 x i16> %[[V2:[0-9]+]],345// CHECK-SAME: <vscale x 4 x i32> %[[V3:[0-9]+]],346// CHECK-SAME: <vscale x 2 x i64> %[[V4:[0-9]+]])347llvm.func @arm_sve_zip_x2(%nxv16i8: vector<[16]xi8>, %nxv8i16: vector<[8]xi16>, %nxv4i32: vector<[4]xi32>, %nxv2i64: vector<[2]xi64>) {348 // CHECK: call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x2.nxv16i8(<vscale x 16 x i8> %[[V1]], <vscale x 16 x i8> %[[V1]])349 %0 = "arm_sve.intr.zip.x2"(%nxv16i8, %nxv16i8) : (vector<[16]xi8>, vector<[16]xi8>)350 -> !llvm.struct<(vector<[16]xi8>, vector<[16]xi8>)>351 // CHECK: call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x2.nxv8i16(<vscale x 8 x i16> %[[V2]], <vscale x 8 x i16> %[[V2]])352 %1 = "arm_sve.intr.zip.x2"(%nxv8i16, %nxv8i16) : (vector<[8]xi16>, vector<[8]xi16>)353 -> !llvm.struct<(vector<[8]xi16>, vector<[8]xi16>)>354 // CHECK: call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.zip.x2.nxv4i32(<vscale x 4 x i32> %[[V3]], <vscale x 4 x i32> %[[V3]])355 %2 = "arm_sve.intr.zip.x2"(%nxv4i32, %nxv4i32) : (vector<[4]xi32>, vector<[4]xi32>)356 -> !llvm.struct<(vector<[4]xi32>, vector<[4]xi32>)>357 // CHECK: call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.zip.x2.nxv2i64(<vscale x 2 x i64> %[[V4]], <vscale x 2 x i64> %[[V4]])358 %3 = "arm_sve.intr.zip.x2"(%nxv2i64, %nxv2i64) : (vector<[2]xi64>, vector<[2]xi64>)359 -> !llvm.struct<(vector<[2]xi64>, vector<[2]xi64>)>360 llvm.return361}362 363// CHECK-LABEL: arm_sve_zip_x4(364// CHECK-SAME: <vscale x 16 x i8> %[[V1:[0-9]+]],365// CHECK-SAME: <vscale x 8 x i16> %[[V2:[0-9]+]],366// CHECK-SAME: <vscale x 4 x i32> %[[V3:[0-9]+]],367// CHECK-SAME: <vscale x 2 x i64> %[[V4:[0-9]+]])368llvm.func @arm_sve_zip_x4(%nxv16i8: vector<[16]xi8>, %nxv8i16: vector<[8]xi16>, %nxv4i32: vector<[4]xi32>, %nxv2i64: vector<[2]xi64>) {369 // CHECK: call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.zip.x4.nxv16i8(<vscale x 16 x i8> %[[V1]], <vscale x 16 x i8> %[[V1]], <vscale x 16 x i8> %[[V1]], <vscale x 16 x i8> %[[V1]])370 %0 = "arm_sve.intr.zip.x4"(%nxv16i8, %nxv16i8, %nxv16i8, %nxv16i8) : (vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>)371 -> !llvm.struct<(vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>, vector<[16]xi8>)>372 // CHECK: call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.zip.x4.nxv8i16(<vscale x 8 x i16> %[[V2]], <vscale x 8 x i16> %[[V2]], <vscale x 8 x i16> %[[V2]], <vscale x 8 x i16> %[[V2]])373 %1 = "arm_sve.intr.zip.x4"(%nxv8i16, %nxv8i16, %nxv8i16, %nxv8i16) : (vector<[8]xi16>, vector<[8]xi16>, vector<[8]xi16>, vector<[8]xi16>)374 -> !llvm.struct<(vector<[8]xi16>, vector<[8]xi16>, vector<[8]xi16>, vector<[8]xi16>)>375 // CHECK: call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.zip.x4.nxv4i32(<vscale x 4 x i32> %[[V3]], <vscale x 4 x i32> %[[V3]], <vscale x 4 x i32> %[[V3]], <vscale x 4 x i32> %[[V3]])376 %2 = "arm_sve.intr.zip.x4"(%nxv4i32, %nxv4i32, %nxv4i32, %nxv4i32) : (vector<[4]xi32>, vector<[4]xi32>, vector<[4]xi32>, vector<[4]xi32>)377 -> !llvm.struct<(vector<[4]xi32>, vector<[4]xi32>, vector<[4]xi32>, vector<[4]xi32>)>378 // CHECK: call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.zip.x4.nxv2i64(<vscale x 2 x i64> %[[V4]], <vscale x 2 x i64> %[[V4]], <vscale x 2 x i64> %[[V4]], <vscale x 2 x i64> %[[V4]])379 %3 = "arm_sve.intr.zip.x4"(%nxv2i64, %nxv2i64, %nxv2i64, %nxv2i64) : (vector<[2]xi64>, vector<[2]xi64>, vector<[2]xi64>, vector<[2]xi64>)380 -> !llvm.struct<(vector<[2]xi64>, vector<[2]xi64>, vector<[2]xi64>, vector<[2]xi64>)>381 llvm.return382}383 384// CHECK-LABEL: arm_sve_whilelt(385// CHECK-SAME: i64 %[[BASE:[0-9]+]],386// CHECK-SAME: i64 %[[N:[0-9]+]]387llvm.func @arm_sve_whilelt(%base: i64, %n: i64) {388 // call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %[[BASE]], i64 %[[N]])389 %1 = "arm_sve.intr.whilelt"(%base, %n) : (i64, i64) -> vector<[2]xi1>390 // call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %[[BASE]], i64 %[[N]])391 %2 = "arm_sve.intr.whilelt"(%base, %n) : (i64, i64) -> vector<[4]xi1>392 // call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %[[BASE]], i64 %[[N]])393 %3 = "arm_sve.intr.whilelt"(%base, %n) : (i64, i64) -> vector<[8]xi1>394 // call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %[[BASE]], i64 %[[N]])395 %4 = "arm_sve.intr.whilelt"(%base, %n) : (i64, i64) -> vector<[16]xi1>396 llvm.return397}398 399// CHECK-LABEL: arm_sve_psel(400// CHECK-SAME: <vscale x 16 x i1> %[[PN:[0-9]+]],401// CHECK-SAME: <vscale x 2 x i1> %[[P1:[0-9]+]],402// CHECK-SAME: <vscale x 4 x i1> %[[P2:[0-9]+]],403// CHECK-SAME: <vscale x 8 x i1> %[[P3:[0-9]+]],404// CHECK-SAME: <vscale x 16 x i1> %[[P4:[0-9]+]],405// CHECK-SAME: i32 %[[INDEX:[0-9]+]])406llvm.func @arm_sve_psel(%pn: vector<[16]xi1>, %p1: vector<[2]xi1>, %p2: vector<[4]xi1>, %p3: vector<[8]xi1>, %p4: vector<[16]xi1>, %index: i32) {407 // CHECK: call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> %[[PN]], <vscale x 2 x i1> %[[P1]], i32 %[[INDEX]])408 "arm_sve.intr.psel"(%pn, %p1, %index) : (vector<[16]xi1>, vector<[2]xi1>, i32) -> vector<[16]xi1>409 // CHECK: call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> %[[PN]], <vscale x 4 x i1> %[[P2]], i32 %[[INDEX]])410 "arm_sve.intr.psel"(%pn, %p2, %index) : (vector<[16]xi1>, vector<[4]xi1>, i32) -> vector<[16]xi1>411 // CHECK: call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> %[[PN]], <vscale x 8 x i1> %[[P3]], i32 %[[INDEX]])412 "arm_sve.intr.psel"(%pn, %p3, %index) : (vector<[16]xi1>, vector<[8]xi1>, i32) -> vector<[16]xi1>413 // CHECK: call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> %[[PN]], <vscale x 16 x i1> %[[P4]], i32 %[[INDEX]])414 "arm_sve.intr.psel"(%pn, %p4, %index) : (vector<[16]xi1>, vector<[16]xi1>, i32) -> vector<[16]xi1>415 llvm.return416}417 418// CHECK-LABEL: @arm_sve_dupq_lane419// CHECK-SAME: <vscale x 16 x i8> %[[V0:[0-9]+]]420// CHECK-SAME: <vscale x 8 x i16> %[[V1:[0-9]+]]421// CHECK-SAME: <vscale x 8 x half> %[[V2:[0-9]+]]422// CHECK-SAME: <vscale x 8 x bfloat> %[[V3:[0-9]+]]423// CHECK-SAME: <vscale x 4 x i32> %[[V4:[0-9]+]]424// CHECK-SAME: <vscale x 4 x float> %[[V5:[0-9]+]]425// CHECK-SAME: <vscale x 2 x i64> %[[V6:[0-9]+]]426// CHECK-SAME: <vscale x 2 x double> %[[V7:[0-9]+]]427llvm.func @arm_sve_dupq_lane(%nxv16i8: vector<[16]xi8>, %nxv8i16: vector<[8]xi16>,428 %nxv8f16: vector<[8]xf16>, %nxv8bf16: vector<[8]xbf16>,429 %nxv4i32: vector<[4]xi32>, %nxv4f32: vector<[4]xf32>,430 %nxv2i64: vector<[2]xi64>, %nxv2f64: vector<[2]xf64>) {431 // CHECK: call <vscale x 16 x i8> @llvm.aarch64.sve.dupq.lane.nxv16i8(<vscale x 16 x i8> %[[V0]], i64 0)432 %0 = "arm_sve.intr.dupq_lane"(%nxv16i8) <{lane = 0 : i64}> : (vector<[16]xi8>) -> vector<[16]xi8>433 // CHECK: call <vscale x 8 x i16> @llvm.aarch64.sve.dupq.lane.nxv8i16(<vscale x 8 x i16> %[[V1]], i64 1)434 %1 = "arm_sve.intr.dupq_lane"(%nxv8i16) <{lane = 1 : i64}> : (vector<[8]xi16>) -> vector<[8]xi16>435 // CHECK: call <vscale x 8 x half> @llvm.aarch64.sve.dupq.lane.nxv8f16(<vscale x 8 x half> %[[V2]], i64 2)436 %2 = "arm_sve.intr.dupq_lane"(%nxv8f16) <{lane = 2 : i64}> : (vector<[8]xf16>) -> vector<[8]xf16>437 // CHECK: call <vscale x 8 x bfloat> @llvm.aarch64.sve.dupq.lane.nxv8bf16(<vscale x 8 x bfloat> %[[V3]], i64 3)438 %3 = "arm_sve.intr.dupq_lane"(%nxv8bf16) <{lane = 3 : i64}> : (vector<[8]xbf16>) -> vector<[8]xbf16>439 // CHECK: call <vscale x 4 x i32> @llvm.aarch64.sve.dupq.lane.nxv4i32(<vscale x 4 x i32> %[[V4]], i64 4)440 %4 = "arm_sve.intr.dupq_lane"(%nxv4i32) <{lane = 4 : i64}> : (vector<[4]xi32>) -> vector<[4]xi32>441 // CHECK: call <vscale x 4 x float> @llvm.aarch64.sve.dupq.lane.nxv4f32(<vscale x 4 x float> %[[V5]], i64 5)442 %5 = "arm_sve.intr.dupq_lane"(%nxv4f32) <{lane = 5 : i64}> : (vector<[4]xf32>) -> vector<[4]xf32>443 // CHECK: call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %[[V6]], i64 6)444 %6 = "arm_sve.intr.dupq_lane"(%nxv2i64) <{lane = 6 : i64}> : (vector<[2]xi64>) -> vector<[2]xi64>445 // CHECK: call <vscale x 2 x double> @llvm.aarch64.sve.dupq.lane.nxv2f64(<vscale x 2 x double> %[[V7]], i64 7)446 %7 = "arm_sve.intr.dupq_lane"(%nxv2f64) <{lane = 7 : i64}> : (vector<[2]xf64>) -> vector<[2]xf64>447 llvm.return448}449