119 lines · plain
1// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s2 3// -----4 5// Test valid architectures work6 7// Valid case on sm_100a8gpu.module @valid_f16x2_rs_sm_100a [#nvvm.target<chip = "sm_100a">] {9 func.func @convert_rs() {10 %f1 = llvm.mlir.constant(1.0 : f32) : f3211 %f2 = llvm.mlir.constant(2.0 : f32) : f3212 %rbits = llvm.mlir.constant(0x12345678 : i32) : i3213 %res = nvvm.convert.f32x2.to.f16x2 %f1, %f2, %rbits {rnd = #nvvm.fp_rnd_mode<rs>} : vector<2xf16>14 return15 }16}17 18// Valid case on sm_103a19gpu.module @valid_bf16x2_rs_sm_103a [#nvvm.target<chip = "sm_103a">] {20 func.func @convert_rs() {21 %f1 = llvm.mlir.constant(1.0 : f32) : f3222 %f2 = llvm.mlir.constant(2.0 : f32) : f3223 %rbits = llvm.mlir.constant(0 : i32) : i3224 %res = nvvm.convert.f32x2.to.bf16x2 %f1, %f2, %rbits {rnd = #nvvm.fp_rnd_mode<rs>} : vector<2xbf16>25 return26 }27}28 29// -----30 31// Test F32x4 -> F8x4 (E4M3) with stochastic rounding (.rs)32 33// CHECK-LABEL: @convert_f32x4_to_f8x4_e4m3_rs34llvm.func @convert_f32x4_to_f8x4_e4m3_rs(%src : vector<4xf32>, %rbits : i32) -> vector<4xi8> {35 // CHECK: %{{.*}} = call <4 x i8> @llvm.nvvm.f32x4.to.e4m3x4.rs.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})36 %res = nvvm.convert.f32x4.to.f8x4 %src, %rbits : vector<4xf32> -> vector<4xi8> (f8E4M3FN)37 llvm.return %res : vector<4xi8>38}39 40// CHECK-LABEL: @convert_f32x4_to_f8x4_e4m3_rs_relu41llvm.func @convert_f32x4_to_f8x4_e4m3_rs_relu(%src : vector<4xf32>, %rbits : i32) -> vector<4xi8> {42 // CHECK: %{{.*}} = call <4 x i8> @llvm.nvvm.f32x4.to.e4m3x4.rs.relu.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})43 %res = nvvm.convert.f32x4.to.f8x4 %src, %rbits {relu = true} : vector<4xf32> -> vector<4xi8> (f8E4M3FN)44 llvm.return %res : vector<4xi8>45}46 47// -----48 49// Test F32x4 -> F8x4 (E5M2) with stochastic rounding (.rs)50 51// CHECK-LABEL: @convert_f32x4_to_f8x4_e5m2_rs52llvm.func @convert_f32x4_to_f8x4_e5m2_rs(%src : vector<4xf32>, %rbits : i32) -> vector<4xi8> {53 // CHECK: %{{.*}} = call <4 x i8> @llvm.nvvm.f32x4.to.e5m2x4.rs.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})54 %res = nvvm.convert.f32x4.to.f8x4 %src, %rbits : vector<4xf32> -> vector<4xi8> (f8E5M2)55 llvm.return %res : vector<4xi8>56}57 58// CHECK-LABEL: @convert_f32x4_to_f8x4_e5m2_rs_relu59llvm.func @convert_f32x4_to_f8x4_e5m2_rs_relu(%src : vector<4xf32>, %rbits : i32) -> vector<4xi8> {60 // CHECK: %{{.*}} = call <4 x i8> @llvm.nvvm.f32x4.to.e5m2x4.rs.relu.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})61 %res = nvvm.convert.f32x4.to.f8x4 %src, %rbits {relu = true} : vector<4xf32> -> vector<4xi8> (f8E5M2)62 llvm.return %res : vector<4xi8>63}64 65// -----66 67// Test F32x4 -> F6x4 (E2M3) with stochastic rounding (.rs)68 69// CHECK-LABEL: @convert_f32x4_to_f6x4_e2m3_rs70llvm.func @convert_f32x4_to_f6x4_e2m3_rs(%src : vector<4xf32>, %rbits : i32) -> vector<4xi8> {71 // CHECK: %{{.*}} = call <4 x i8> @llvm.nvvm.f32x4.to.e2m3x4.rs.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})72 %res = nvvm.convert.f32x4.to.f6x4 %src, %rbits : vector<4xf32> -> vector<4xi8> (f6E2M3FN)73 llvm.return %res : vector<4xi8>74}75 76// CHECK-LABEL: @convert_f32x4_to_f6x4_e2m3_rs_relu77llvm.func @convert_f32x4_to_f6x4_e2m3_rs_relu(%src : vector<4xf32>, %rbits : i32) -> vector<4xi8> {78 // CHECK: %{{.*}} = call <4 x i8> @llvm.nvvm.f32x4.to.e2m3x4.rs.relu.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})79 %res = nvvm.convert.f32x4.to.f6x4 %src, %rbits {relu = true} : vector<4xf32> -> vector<4xi8> (f6E2M3FN)80 llvm.return %res : vector<4xi8>81}82 83// -----84 85// Test F32x4 -> F6x4 (E3M2) with stochastic rounding (.rs)86 87// CHECK-LABEL: @convert_f32x4_to_f6x4_e3m2_rs88llvm.func @convert_f32x4_to_f6x4_e3m2_rs(%src : vector<4xf32>, %rbits : i32) -> vector<4xi8> {89 // CHECK: %{{.*}} = call <4 x i8> @llvm.nvvm.f32x4.to.e3m2x4.rs.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})90 %res = nvvm.convert.f32x4.to.f6x4 %src, %rbits : vector<4xf32> -> vector<4xi8> (f6E3M2FN)91 llvm.return %res : vector<4xi8>92}93 94// CHECK-LABEL: @convert_f32x4_to_f6x4_e3m2_rs_relu95llvm.func @convert_f32x4_to_f6x4_e3m2_rs_relu(%src : vector<4xf32>, %rbits : i32) -> vector<4xi8> {96 // CHECK: %{{.*}} = call <4 x i8> @llvm.nvvm.f32x4.to.e3m2x4.rs.relu.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})97 %res = nvvm.convert.f32x4.to.f6x4 %src, %rbits {relu = true} : vector<4xf32> -> vector<4xi8> (f6E3M2FN)98 llvm.return %res : vector<4xi8>99}100 101// -----102 103// Test F32x4 -> F4x4 (E2M1) with stochastic rounding (.rs)104 105// CHECK-LABEL: @convert_f32x4_to_f4x4_e2m1_rs106llvm.func @convert_f32x4_to_f4x4_e2m1_rs(%src : vector<4xf32>, %rbits : i32) -> i16 {107 // CHECK: %{{.*}} = call i16 @llvm.nvvm.f32x4.to.e2m1x4.rs.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})108 %res = nvvm.convert.f32x4.to.f4x4 %src, %rbits : vector<4xf32> -> i16 (f4E2M1FN)109 llvm.return %res : i16110}111 112// CHECK-LABEL: @convert_f32x4_to_f4x4_e2m1_rs_relu113llvm.func @convert_f32x4_to_f4x4_e2m1_rs_relu(%src : vector<4xf32>, %rbits : i32) -> i16 {114 // CHECK: %{{.*}} = call i16 @llvm.nvvm.f32x4.to.e2m1x4.rs.relu.satfinite(<4 x float> %{{.*}}, i32 %{{.*}})115 %res = nvvm.convert.f32x4.to.f4x4 %src, %rbits {relu = true} : vector<4xf32> -> i16 (f4E2M1FN)116 llvm.return %res : i16117}118 119