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1// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s2 3llvm.func @_QPfoo(%arg0: !llvm.ptr {fir.bindc_name = "array", llvm.nocapture}, %arg1: !llvm.ptr {fir.bindc_name = "t", llvm.nocapture}) {4 %0 = llvm.mlir.constant(0 : i64) : i325 %1 = llvm.mlir.constant(1 : i32) : i326 %2 = llvm.mlir.constant(10 : i64) : i647 %3 = llvm.mlir.constant(1 : i64) : i648 %4 = llvm.alloca %3 x i32 {bindc_name = "i", pinned} : (i64) -> !llvm.ptr9 %5 = llvm.load %arg1 : !llvm.ptr -> i3210 %6 = llvm.icmp "ne" %5, %0 : i3211 %7 = llvm.trunc %2 : i64 to i3212 omp.wsloop {13 omp.simd if(%6) {14 omp.loop_nest (%arg2) : i32 = (%1) to (%7) inclusive step (%1) {15 llvm.store %arg2, %4 : i32, !llvm.ptr16 %8 = llvm.load %4 : !llvm.ptr -> i3217 %9 = llvm.sext %8 : i32 to i6418 %10 = llvm.getelementptr %arg0[%9] : (!llvm.ptr, i64) -> !llvm.ptr, i3219 llvm.store %8, %10 : i32, !llvm.ptr20 omp.yield21 }22 } {omp.composite}23 } {omp.composite}24 llvm.return25}26 27// CHECK-LABEL: @_QPfoo28// ...29// CHECK: omp_loop.preheader: ; preds =30// CHECK: store i32 0, ptr %[[LB_ADDR:.*]], align 431// CHECK: store i32 9, ptr %[[UB_ADDR:.*]], align 432// CHECK: store i32 1, ptr %[[STEP_ADDR:.*]], align 433// CHECK: %[[VAL_15:.*]] = call i32 @__kmpc_global_thread_num(ptr @1)34// CHECK: call void @__kmpc_for_static_init_4u(ptr @1, i32 %[[VAL_15]], i32 34, ptr %{{.*}}, ptr %[[LB_ADDR]], ptr %[[UB_ADDR]], ptr %[[STEP_ADDR]], i32 1, i32 0)35// CHECK: %[[LB:.*]] = load i32, ptr %[[LB_ADDR]], align 436// CHECK: %[[UB:.*]] = load i32, ptr %[[UB_ADDR]], align 437// CHECK: %[[VAL_18:.*]] = sub i32 %[[UB]], %[[LB]]38// CHECK: %[[COUNT:.*]] = add i32 %[[VAL_18]], 139// CHECK: br label %[[OMP_LOOP_HEADER:.*]]40// CHECK: omp_loop.header: ; preds = %[[OMP_LOOP_INC:.*]], %[[OMP_LOOP_PREHEADER:.*]]41// CHECK: %[[IV:.*]] = phi i32 [ 0, %[[OMP_LOOP_PREHEADER]] ], [ %[[NEW_IV:.*]], %[[OMP_LOOP_INC]] ]42// CHECK: br label %[[OMP_LOOP_COND:.*]]43// CHECK: omp_loop.cond: ; preds = %[[OMP_LOOP_HEADER]]44// CHECK: %[[VAL_25:.*]] = icmp ult i32 %[[IV]], %[[COUNT]]45// CHECK: br i1 %[[VAL_25]], label %[[OMP_LOOP_BODY:.*]], label %[[OMP_LOOP_EXIT:.*]]46// CHECK: omp_loop.body: ; preds = %[[OMP_LOOP_COND]]47// CHECK: %[[VAL_28:.*]] = add i32 %[[IV]], %[[LB]]48// This is the IF clause:49// CHECK: br i1 %{{.*}}, label %[[SIMD_IF_THEN:.*]], label %[[SIMD_IF_ELSE:.*]]50 51// CHECK: simd.if.then: ; preds = %[[OMP_LOOP_BODY]]52// CHECK: %[[VAL_29:.*]] = mul i32 %[[VAL_28]], 153// CHECK: %[[VAL_30:.*]] = add i32 %[[VAL_29]], 154// CHECK: br label %[[VAL_33:.*]]55// CHECK: omp.loop_nest.region: ; preds = %[[SIMD_IF_THEN]]56// This version contains !llvm.access.group metadata for SIMD57// CHECK: store i32 %[[VAL_30]], ptr %{{.*}}, align 4, !llvm.access.group !158// CHECK: %[[VAL_34:.*]] = load i32, ptr %{{.*}}, align 4, !llvm.access.group !159// CHECK: %[[VAL_35:.*]] = sext i32 %[[VAL_34]] to i6460// CHECK: %[[VAL_36:.*]] = getelementptr i32, ptr %[[VAL_37:.*]], i64 %[[VAL_35]]61// CHECK: store i32 %[[VAL_34]], ptr %[[VAL_36]], align 4, !llvm.access.group !162// CHECK: br label %[[OMP_REGION_CONT3:.*]]63// CHECK: omp.region.cont3: ; preds = %[[VAL_33]]64// CHECK: br label %[[SIMD_PRE_LATCH:.*]]65 66// CHECK: simd.pre_latch: ; preds = %[[OMP_REGION_CONT3]], %[[OMP_REGION_CONT35:.*]]67// CHECK: br label %[[OMP_LOOP_INC]]68// CHECK: omp_loop.inc: ; preds = %[[SIMD_PRE_LATCH]]69// CHECK: %[[NEW_IV]] = add nuw i32 %[[IV]], 170// CHECK: br label %[[OMP_LOOP_HEADER]], !llvm.loop !271 72// CHECK: simd.if.else: ; preds = %[[OMP_LOOP_BODY]]73// CHECK: br label %[[SIMD_IF_ELSE2:.*]]74// CHECK: simd.if.else5:75// CHECK: %[[MUL:.*]] = mul i32 %[[VAL_28]], 176// CHECK: %[[ADD:.*]] = add i32 %[[MUL]], 177// CHECK: br label %[[LOOP_NEST_REGION:.*]]78// CHECK: omp.loop_nest.region6: ; preds = %[[SIMD_IF_ELSE2]]79// No llvm.access.group metadata for else clause80// CHECK: store i32 %[[ADD]], ptr %{{.*}}, align 481// CHECK: %[[VAL_42:.*]] = load i32, ptr %{{.*}}, align 482// CHECK: %[[VAL_43:.*]] = sext i32 %[[VAL_42]] to i6483// CHECK: %[[VAL_44:.*]] = getelementptr i32, ptr %[[VAL_37]], i64 %[[VAL_43]]84// CHECK: store i32 %[[VAL_42]], ptr %[[VAL_44]], align 485// CHECK: br label %[[OMP_REGION_CONT35]]86// CHECK: omp.region.cont37: ; preds = %[[LOOP_NEST_REGION]]87// CHECK: br label %[[SIMD_PRE_LATCH]]88 89// CHECK: omp_loop.exit: ; preds = %[[OMP_LOOP_COND]]90// CHECK: call void @__kmpc_for_static_fini(ptr @1, i32 %[[VAL_15]])91// CHECK: %[[VAL_45:.*]] = call i32 @__kmpc_global_thread_num(ptr @1)92// CHECK: call void @__kmpc_barrier(ptr @2, i32 %[[VAL_45]])93 94// CHECK: !1 = distinct !{}95// CHECK: !2 = distinct !{!2, !3}96// CHECK: !3 = !{!"llvm.loop.parallel_accesses", !1}97// CHECK-NOT: llvm.loop.vectorize98