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1// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s2 3// Check that omp.simd as a leaf of a composite construct still generates4// the appropriate loop vectorization attribute.5 6// CHECK-LABEL: define internal void @test_parallel_do_simd..omp_par7// CHECK: omp.par.entry:8// CHECK: omp.par.region:9// CHECK: omp_loop.header:10// CHECK: omp_loop.inc:11// CHECK-NEXT: %omp_loop.next = add nuw i32 %omp_loop.iv, 112// CHECK-NEXT: br label %omp_loop.header, !llvm.loop ![[LOOP_ATTR:.*]]13// CHECK: ![[LOOP_ATTR]] = distinct !{![[LOOP_ATTR]], ![[LPAR:.*]], ![[LVEC:.*]]}14// CHECK: ![[LPAR]] = !{!"llvm.loop.parallel_accesses", ![[PAR_ACC:.*]]}15// CHECK: ![[LVEC]] = !{!"llvm.loop.vectorize.enable", i1 true}16 17llvm.func @test_parallel_do_simd() {18 %0 = llvm.mlir.constant(1 : i64) : i6419 %1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr20 %2 = llvm.mlir.constant(1000 : i32) : i3221 %3 = llvm.mlir.constant(1 : i32) : i3222 %4 = llvm.mlir.constant(1 : i64) : i6423 omp.parallel {24 %5 = llvm.mlir.constant(1 : i64) : i6425 %6 = llvm.alloca %5 x i32 {bindc_name = "i", pinned} : (i64) -> !llvm.ptr26 %7 = llvm.mlir.constant(1 : i64) : i6427 omp.wsloop {28 omp.simd {29 omp.loop_nest (%arg0) : i32 = (%3) to (%2) inclusive step (%3) {30 llvm.store %arg0, %6 : i32, !llvm.ptr31 omp.yield32 }33 } {omp.composite}34 } {omp.composite}35 omp.terminator36 }37 llvm.return38}39