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1; RUN: opt %loadNPMPolly -polly-stmt-granularity=bb -polly-optree-normalize-phi=true '-passes=polly-custom<optree>' -polly-print-optree -disable-output < %s | FileCheck %s -match-full-lines2 3target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"4 5define internal fastcc void @kernel_atax(ptr nocapture readonly %A, ptr nocapture readonly %x, ptr nocapture %y, ptr nocapture %tmp) unnamed_addr {6entry:7  br label %entry.split8 9entry.split:                                      ; preds = %entry10  call void @llvm.memset.p0.i64(ptr %y, i8 0, i64 16800, i32 8, i1 false)11  br label %for.body312 13for.body3:                                        ; preds = %for.inc40, %entry.split14  %indvars.iv8 = phi i64 [ 0, %entry.split ], [ %indvars.iv.next9, %for.inc40 ]15  %arrayidx5 = getelementptr inbounds double, ptr %tmp, i64 %indvars.iv816  store double 0.000000e+00, ptr %arrayidx5, align 8, !tbaa !617  br label %for.body818 19for.body8:                                        ; preds = %for.body8, %for.body320  %0 = phi double [ 0.000000e+00, %for.body3 ], [ %add, %for.body8 ]21  %indvars.iv = phi i64 [ 0, %for.body3 ], [ %indvars.iv.next, %for.body8 ]22  %arrayidx14 = getelementptr inbounds [2100 x double], ptr %A, i64 %indvars.iv8, i64 %indvars.iv23  %1 = load double, ptr %arrayidx14, align 8, !tbaa !624  %arrayidx16 = getelementptr inbounds double, ptr %x, i64 %indvars.iv25  %2 = load double, ptr %arrayidx16, align 8, !tbaa !626  %mul = fmul double %1, %227  %add = fadd double %0, %mul28  store double %add, ptr %arrayidx5, align 8, !tbaa !629  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 130  %exitcond = icmp eq i64 %indvars.iv.next, 231  br i1 %exitcond, label %for.end21, label %for.body832 33for.end21:                                        ; preds = %for.body834  br label %for.body2435 36for.body24:                                       ; preds = %for.body24.for.body24_crit_edge, %for.end2137  %3 = phi double [ %add, %for.end21 ], [ %.pre, %for.body24.for.body24_crit_edge ]38  %indvars.iv5 = phi i64 [ 0, %for.end21 ], [ %indvars.iv.next6, %for.body24.for.body24_crit_edge ]39  %arrayidx26 = getelementptr inbounds double, ptr %y, i64 %indvars.iv540  %4 = load double, ptr %arrayidx26, align 8, !tbaa !641  %arrayidx30 = getelementptr inbounds [2100 x double], ptr %A, i64 %indvars.iv8, i64 %indvars.iv542  %5 = load double, ptr %arrayidx30, align 8, !tbaa !643  %mul33 = fmul double %5, %344  %add34 = fadd double %4, %mul3345  store double %add34, ptr %arrayidx26, align 8, !tbaa !646  %indvars.iv.next6 = add nuw nsw i64 %indvars.iv5, 147  %exitcond7 = icmp eq i64 %indvars.iv.next6, 248  br i1 %exitcond7, label %for.inc40, label %for.body24.for.body24_crit_edge49 50for.body24.for.body24_crit_edge:                  ; preds = %for.body2451  %.pre = load double, ptr %arrayidx5, align 8, !tbaa !652  br label %for.body2453 54for.inc40:                                        ; preds = %for.body2455  %indvars.iv.next9 = add nuw nsw i64 %indvars.iv8, 156  %exitcond10 = icmp eq i64 %indvars.iv.next9, 257  br i1 %exitcond10, label %for.end42, label %for.body358 59for.end42:                                        ; preds = %for.inc4060  ret void61}62 63; Function Attrs: argmemonly nounwind64declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i32, i1)65 66!llvm.module.flags = !{!0}67!llvm.ident = !{!1}68 69!0 = !{i32 1, !"wchar_size", i32 4}70!1 = !{!"clang version 6.0.0 (trunk 312565) (llvm/trunk 312564)"}71!2 = !{!3, !3, i64 0}72!3 = !{!"any pointer", !4, i64 0}73!4 = !{!"omnipotent char", !5, i64 0}74!5 = !{!"Simple C/C++ TBAA"}75!6 = !{!7, !7, i64 0}76!7 = !{!"double", !4, i64 0}77 78; CHECK: Statistics {79; CHECK:     Operand trees forwarded: 280; CHECK:     Statements with forwarded operand trees: 281; CHECK: }82 83; CHECK-NEXT: After statements {84; CHECK-NEXT:     Stmt_for_body385; CHECK-NEXT:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 0]86; CHECK-NEXT:                 { Stmt_for_body3[i0] -> MemRef_tmp[i0] };87; CHECK-NEXT:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]88; CHECK-NEXT:                 { Stmt_for_body3[i0] -> MemRef1__phi[] };89; CHECK-NEXT:             Instructions {90; CHECK-NEXT:                   store double 0.000000e+00, ptr %arrayidx5, align 8, !tbaa !291; CHECK-NEXT:             }92; CHECK-NEXT:     Stmt_for_body893; CHECK-NEXT:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]94; CHECK-NEXT:                 { Stmt_for_body8[i0, i1] -> MemRef1__phi[] };95; CHECK-NEXT:             ReadAccess :=       [Reduction Type: NONE] [Scalar: 1]96; CHECK-NEXT:                 { Stmt_for_body8[i0, i1] -> MemRef1__phi[] };97; CHECK-NEXT:            new: { Stmt_for_body8[i0, i1] -> MemRef_tmp[i0] };98; CHECK-NEXT:             ReadAccess :=       [Reduction Type: NONE] [Scalar: 0]99; CHECK-NEXT:                 { Stmt_for_body8[i0, i1] -> MemRef_A[i0, i1] };100; CHECK-NEXT:             ReadAccess :=       [Reduction Type: NONE] [Scalar: 0]101; CHECK-NEXT:                 { Stmt_for_body8[i0, i1] -> MemRef_x[i1] };102; CHECK-NEXT:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 0]103; CHECK-NEXT:                 { Stmt_for_body8[i0, i1] -> MemRef_tmp[i0] };104; CHECK-NEXT:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]105; CHECK-NEXT:                 { Stmt_for_body8[i0, i1] -> MemRef_add[] };106; CHECK-NEXT:             Instructions {107; CHECK-NEXT:                   %0 = phi double [ 0.000000e+00, %for.body3 ], [ %add, %for.body8 ]108; CHECK-NEXT:                   %1 = load double, ptr %arrayidx14, align 8, !tbaa !2109; CHECK-NEXT:                   %2 = load double, ptr %arrayidx16, align 8, !tbaa !2110; CHECK-NEXT:                   %mul = fmul double %1, %2111; CHECK-NEXT:                   %add = fadd double %0, %mul112; CHECK-NEXT:                   store double %add, ptr %arrayidx5, align 8, !tbaa !2113; CHECK-NEXT:                   %exitcond = icmp eq i64 %indvars.iv.next, 2114; CHECK-NEXT:             }115; CHECK-NEXT:     Stmt_for_end21116; CHECK-NEXT:             ReadAccess :=       [Reduction Type: NONE] [Scalar: 1]117; CHECK-NEXT:                 { Stmt_for_end21[i0] -> MemRef_add[] };118; CHECK-NEXT:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]119; CHECK-NEXT:                 { Stmt_for_end21[i0] -> MemRef5__phi[] };120; CHECK-NEXT:             Instructions {121; CHECK-NEXT:             }122; CHECK-NEXT:     Stmt_for_body24123; CHECK-NEXT:             ReadAccess :=       [Reduction Type: NONE] [Scalar: 1]124; CHECK-NEXT:                 { Stmt_for_body24[i0, i1] -> MemRef5__phi[] };125; CHECK-NEXT:            new: { Stmt_for_body24[i0, i1] -> MemRef_tmp[i0] };126; CHECK-NEXT:             ReadAccess :=       [Reduction Type: NONE] [Scalar: 0]127; CHECK-NEXT:                 { Stmt_for_body24[i0, i1] -> MemRef_y[i1] };128; CHECK-NEXT:             ReadAccess :=       [Reduction Type: NONE] [Scalar: 0]129; CHECK-NEXT:                 { Stmt_for_body24[i0, i1] -> MemRef_A[i0, i1] };130; CHECK-NEXT:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 0]131; CHECK-NEXT:                 { Stmt_for_body24[i0, i1] -> MemRef_y[i1] };132; CHECK-NEXT:             Instructions {133; CHECK-NEXT:                   %3 = phi double [ %add, %for.end21 ], [ %.pre, %for.body24.for.body24_crit_edge ]134; CHECK-NEXT:                   %4 = load double, ptr %arrayidx26, align 8, !tbaa !2135; CHECK-NEXT:                   %5 = load double, ptr %arrayidx30, align 8, !tbaa !2136; CHECK-NEXT:                   %mul33 = fmul double %5, %3137; CHECK-NEXT:                   %add34 = fadd double %4, %mul33138; CHECK-NEXT:                   store double %add34, ptr %arrayidx26, align 8, !tbaa !2139; CHECK-NEXT:                   %exitcond7 = icmp eq i64 %indvars.iv.next6, 2140; CHECK-NEXT:             }141; CHECK-NEXT:     Stmt_for_body24_for_body24_crit_edge142; CHECK-NEXT:             MustWriteAccess :=  [Reduction Type: NONE] [Scalar: 1]143; CHECK-NEXT:                 { Stmt_for_body24_for_body24_crit_edge[i0, i1] -> MemRef5__phi[] };144; CHECK-NEXT:             ReadAccess :=       [Reduction Type: NONE] [Scalar: 0]145; CHECK-NEXT:                 { Stmt_for_body24_for_body24_crit_edge[i0, i1] -> MemRef_tmp[i0] };146; CHECK-NEXT:             Instructions {147; CHECK-NEXT:                   %.pre = load double, ptr %arrayidx5, align 8, !tbaa !2148; CHECK-NEXT:             }149; CHECK-NEXT: }150