168 lines · plain
1; RUN: opt %loadNPMPolly -polly-pattern-matching-based-opts=true -polly-target-throughput-vector-fma=1 -polly-target-latency-vector-fma=8 -polly-target-1st-cache-level-associativity=8 -polly-target-2nd-cache-level-associativity=8 -polly-target-1st-cache-level-size=32768 -polly-target-vector-register-bitwidth=256 -polly-target-2nd-cache-level-size=262144 '-passes=polly-custom<opt-isl;ast>' -polly-print-ast -disable-output < %s | FileCheck %s2;3; opt %loadNPMPolly -passes=polly-opt-isl -polly-pattern-matching-based-opts=true \4; -polly-target-throughput-vector-fma=1 \5; -polly-target-latency-vector-fma=8 \6; -passes=polly-codegen -polly-target-1st-cache-level-associativity=8 \7; -polly-target-2nd-cache-level-associativity=8 \8; -polly-target-1st-cache-level-size=32768 \9; -polly-target-vector-register-bitwidth=256 \10; -polly-target-2nd-cache-level-size=262144 -gvn -licm -slp-vectorizer \11; -mcpu=corei7 -stats -S < %s 2>&1 | FileCheck %s \12; --check-prefix=AUTO-VECTORIZATION13;14;15; /* We isolate a set of partial tile prefixes, which contains only partial16; tile prefixes that have exactly Mr x Nr iterations of the two innermost17; loops produced by the optimization of the matrix multiplication. Mr and18; Nr are parameters of the micro-kernel (see getMicroKernelParams and19; getMacroKernelParams from lib/Transform/ScheduleOptimizer.cpp for20; details). This test check that in case it cannot be proved that21; the number of loop iterations can be evenly divided by tile sizes22; and we tile and unroll the point loops, it helps to get rid of23; the conditional expressions of the unrolled innermost loops, which24; prevents stores and loads of the unrolled loops from being sunk25; and hoisted. Otherwise, it causes a run-time regression in comparison26; to the vectorized code with sunk and hoisted memory accesses. */27; /* C := A * B + C */28; for (i = 0; i < 1020; i++)29; for (j = 0; j < 1020; j++)30; for (k = 0; k < 1020; ++k)31; C[i][j] += A[i][k] * B[k][j];32;33; CHECK: // 1st level tiling - Tiles34; CHECK-NEXT: for (int c1 = 0; c1 <= 3; c1 += 1) {35; CHECK-NEXT: for (int c3 = 0; c3 <= 1019; c3 += 1)36; CHECK-NEXT: for (int c4 = 256 * c1; c4 <= min(1019, 256 * c1 + 255); c4 += 1)37; CHECK-NEXT: CopyStmt_0(0, c3, c4);38; CHECK-NEXT: for (int c2 = 0; c2 <= 10; c2 += 1) {39; CHECK-NEXT: for (int c6 = 96 * c2; c6 <= min(1019, 96 * c2 + 95); c6 += 1)40; CHECK-NEXT: for (int c7 = 256 * c1; c7 <= min(1019, 256 * c1 + 255); c7 += 1)41; CHECK-NEXT: CopyStmt_1(0, c1, c2, c6, c7);42; CHECK-NEXT: // 1st level tiling - Points43; CHECK-NEXT: // Register tiling - Tiles44; CHECK-NEXT: {45; CHECK-NEXT: for (int c3 = 0; c3 <= 126; c3 += 1)46; CHECK-NEXT: for (int c4 = 0; c4 <= min(23, -24 * c2 + 254); c4 += 1)47; CHECK-NEXT: for (int c5 = 0; c5 <= min(255, -256 * c1 + 1019); c5 += 1) {48; CHECK-NEXT: // Loop Vectorizer Disabled49; CHECK-NEXT: // Register tiling - Points50; CHECK-NEXT: {51; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3, 256 * c1 + c5);52; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 1, 256 * c1 + c5);53; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 2, 256 * c1 + c5);54; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 3, 256 * c1 + c5);55; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 4, 256 * c1 + c5);56; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 5, 256 * c1 + c5);57; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 6, 256 * c1 + c5);58; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 7, 256 * c1 + c5);59; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3, 256 * c1 + c5);60; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 1, 256 * c1 + c5);61; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 2, 256 * c1 + c5);62; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 3, 256 * c1 + c5);63; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 4, 256 * c1 + c5);64; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 5, 256 * c1 + c5);65; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 6, 256 * c1 + c5);66; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 7, 256 * c1 + c5);67; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3, 256 * c1 + c5);68; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 1, 256 * c1 + c5);69; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 2, 256 * c1 + c5);70; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 3, 256 * c1 + c5);71; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 4, 256 * c1 + c5);72; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 5, 256 * c1 + c5);73; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 6, 256 * c1 + c5);74; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 7, 256 * c1 + c5);75; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3, 256 * c1 + c5);76; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 1, 256 * c1 + c5);77; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 2, 256 * c1 + c5);78; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 3, 256 * c1 + c5);79; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 4, 256 * c1 + c5);80; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 5, 256 * c1 + c5);81; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 6, 256 * c1 + c5);82; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 7, 256 * c1 + c5);83; CHECK-NEXT: }84; CHECK-NEXT: }85; CHECK-NEXT: for (int c4 = 0; c4 <= min(23, -24 * c2 + 254); c4 += 1)86; CHECK-NEXT: for (int c5 = 0; c5 <= min(255, -256 * c1 + 1019); c5 += 1) {87; CHECK-NEXT: // Loop Vectorizer Disabled88; CHECK-NEXT: // Register tiling - Points89; CHECK-NEXT: {90; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 1016, 256 * c1 + c5);91; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 1017, 256 * c1 + c5);92; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 1018, 256 * c1 + c5);93; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 1019, 256 * c1 + c5);94; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 1016, 256 * c1 + c5);95; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 1017, 256 * c1 + c5);96; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 1018, 256 * c1 + c5);97; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 1019, 256 * c1 + c5);98; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 1016, 256 * c1 + c5);99; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 1017, 256 * c1 + c5);100; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 1018, 256 * c1 + c5);101; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 1019, 256 * c1 + c5);102; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 1016, 256 * c1 + c5);103; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 1017, 256 * c1 + c5);104; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 1018, 256 * c1 + c5);105; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 1019, 256 * c1 + c5);106; CHECK-NEXT: }107; CHECK-NEXT: }108; CHECK-NEXT: }109; CHECK-NEXT: }110; CHECK-NEXT: }111;112; AUTO-VECTORIZATION: fmul <4 x double>113; AUTO-VECTORIZATION: fadd <4 x double>114 115; AUTO-VECTORIZATION: 36 SLP - Number of vector instructions generated116; AUTO-VECTORIZATION: 146 licm - Number of instructions hoisted out of loop117; AUTO-VECTORIZATION: 1 licm - Number of load insts hoisted or sunk118; AUTO-VECTORIZATION: 32 licm - Number of memory locations promoted to registers119;120target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"121target triple = "x86_64-unknown-unknown"122 123define internal void @kernel_gemm(i32 %ni, i32 %nj, i32 %nk, double %alpha, double %beta, ptr %C, ptr %A, ptr %B) #0 {124entry:125 br label %entry.split126 127entry.split: ; preds = %entry128 br label %for.cond1.preheader129 130for.cond1.preheader: ; preds = %for.inc20, %entry.split131 %indvars.iv41 = phi i64 [ 0, %entry.split ], [ %indvars.iv.next42, %for.inc20 ]132 br label %for.cond4.preheader133 134for.cond4.preheader: ; preds = %for.inc17, %for.cond1.preheader135 %indvars.iv38 = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next39, %for.inc17 ]136 br label %for.body6137 138for.body6: ; preds = %for.body6, %for.cond4.preheader139 %indvars.iv = phi i64 [ 0, %for.cond4.preheader ], [ %indvars.iv.next, %for.body6 ]140 %arrayidx8 = getelementptr inbounds [1020 x double], ptr %A, i64 %indvars.iv41, i64 %indvars.iv141 %tmp = load double, ptr %arrayidx8, align 8142 %arrayidx12 = getelementptr inbounds [1020 x double], ptr %B, i64 %indvars.iv, i64 %indvars.iv38143 %tmp1 = load double, ptr %arrayidx12, align 8144 %mul = fmul double %tmp, %tmp1145 %arrayidx16 = getelementptr inbounds [1020 x double], ptr %C, i64 %indvars.iv41, i64 %indvars.iv38146 %tmp2 = load double, ptr %arrayidx16, align 8147 %add = fadd double %tmp2, %mul148 store double %add, ptr %arrayidx16, align 8149 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1150 %exitcond = icmp ne i64 %indvars.iv.next, 1020151 br i1 %exitcond, label %for.body6, label %for.inc17152 153for.inc17: ; preds = %for.body6154 %indvars.iv.next39 = add nuw nsw i64 %indvars.iv38, 1155 %exitcond40 = icmp ne i64 %indvars.iv.next39, 1020156 br i1 %exitcond40, label %for.cond4.preheader, label %for.inc20157 158for.inc20: ; preds = %for.inc17159 %indvars.iv.next42 = add nuw nsw i64 %indvars.iv41, 1160 %exitcond43 = icmp ne i64 %indvars.iv.next42, 1020161 br i1 %exitcond43, label %for.cond1.preheader, label %for.end22162 163for.end22: ; preds = %for.inc20164 ret void165}166 167attributes #0 = { nounwind uwtable "target-cpu"="x86-64" "target-features"="+aes,+avx,+cmov,+cx16,+fxsr,+mmx,+pclmul,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" }168