121 lines · plain
1; RUN: opt %loadNPMPolly '-passes=polly-custom<scops>' -polly-print-scops -disable-output < %s 2>&1 | FileCheck %s2;3; The assumed context should be empty since the <nsw> flags on the IV4; increments already guarantee that there is no wrap in the loop trip5; count.6;7; int jd(int *restrict A, int x, int N) {8; for (int i = 1; i < N; i++)9; for (int j = 3; j < N; j++)10; x += A[i];11; return x;12; }13 14; CHECK: Assumed Context:15; CHECK-NEXT: [N] -> { : }16;17; CHECK: Statements {18; CHECK-NEXT: Stmt_for_cond19; CHECK-NEXT: Domain :=20; CHECK-NEXT: [N] -> { Stmt_for_cond[i0] : 0 <= i0 < N; Stmt_for_cond[0] : N <= 0 };21; CHECK-NEXT: Schedule :=22; CHECK-NEXT: [N] -> { Stmt_for_cond[i0] -> [i0, 0, 0, 0] : i0 < N; Stmt_for_cond[0] -> [0, 0, 0, 0] : N <= 0 };23; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]24; CHECK-NEXT: [N] -> { Stmt_for_cond[i0] -> MemRef_x_addr_0__phi[] };25; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]26; CHECK-NEXT: [N] -> { Stmt_for_cond[i0] -> MemRef_x_addr_0[] };27; CHECK-NEXT: Stmt_for_body28; CHECK-NEXT: Domain :=29; CHECK-NEXT: [N] -> { Stmt_for_body[i0] : 0 <= i0 <= -2 + N };30; CHECK-NEXT: Schedule :=31; CHECK-NEXT: [N] -> { Stmt_for_body[i0] -> [i0, 1, 0, 0] };32; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]33; CHECK-NEXT: [N] -> { Stmt_for_body[i0] -> MemRef_x_addr_0[] };34; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]35; CHECK-NEXT: [N] -> { Stmt_for_body[i0] -> MemRef_x_addr_1__phi[] };36; CHECK-NEXT: Stmt_for_cond137; CHECK-NEXT: Domain :=38; CHECK-NEXT: [N] -> { Stmt_for_cond1[i0, i1] : 0 <= i0 <= -2 + N and 0 <= i1 <= -3 + N };39; CHECK-NEXT: Schedule :=40; CHECK-NEXT: [N] -> { Stmt_for_cond1[i0, i1] -> [i0, 2, i1, 0] };41; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]42; CHECK-NEXT: [N] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1__phi[] };43; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]44; CHECK-NEXT: [N] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1[] };45; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]46; CHECK-NEXT: [N] -> { Stmt_for_cond1[i0, i1] -> MemRef_x_addr_1_lcssa__phi[] };47; CHECK-NEXT: Stmt_for_inc48; CHECK-NEXT: Domain :=49; CHECK-NEXT: [N] -> { Stmt_for_inc[i0, i1] : 0 <= i0 <= -2 + N and 0 <= i1 <= -4 + N };50; CHECK-NEXT: Schedule :=51; CHECK-NEXT: [N] -> { Stmt_for_inc[i0, i1] -> [i0, 2, i1, 1] };52; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]53; CHECK-NEXT: [N] -> { Stmt_for_inc[i0, i1] -> MemRef_x_addr_1__phi[] };54; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]55; CHECK-NEXT: [N] -> { Stmt_for_inc[i0, i1] -> MemRef_A[1 + i0] };56; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]57; CHECK-NEXT: [N] -> { Stmt_for_inc[i0, i1] -> MemRef_x_addr_1[] };58; CHECK-NEXT: Stmt_for_end59; CHECK-NEXT: Domain :=60; CHECK-NEXT: [N] -> { Stmt_for_end[i0] : N >= 3 and 0 <= i0 <= -2 + N };61; CHECK-NEXT: Schedule :=62; CHECK-NEXT: [N] -> { Stmt_for_end[i0] -> [i0, 3, 0, 0] };63; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]64; CHECK-NEXT: [N] -> { Stmt_for_end[i0] -> MemRef_x_addr_1_lcssa[] };65; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]66; CHECK-NEXT: [N] -> { Stmt_for_end[i0] -> MemRef_x_addr_1_lcssa__phi[] };67; CHECK-NEXT: Stmt_for_inc468; CHECK-NEXT: Domain :=69; CHECK-NEXT: [N] -> { Stmt_for_inc4[i0] : N >= 3 and 0 <= i0 <= -2 + N };70; CHECK-NEXT: Schedule :=71; CHECK-NEXT: [N] -> { Stmt_for_inc4[i0] -> [i0, 4, 0, 0] };72; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]73; CHECK-NEXT: [N] -> { Stmt_for_inc4[i0] -> MemRef_x_addr_1_lcssa[] };74; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]75; CHECK-NEXT: [N] -> { Stmt_for_inc4[i0] -> MemRef_x_addr_0__phi[] };76; CHECK-NEXT: }77 78target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"79 80define i32 @jd(ptr noalias %A, i32 %x, i32 %N) {81entry:82 %tmp = sext i32 %N to i6483 br label %for.cond84 85for.cond: ; preds = %for.inc4, %entry86 %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc4 ], [ 1, %entry ]87 %x.addr.0 = phi i32 [ %x, %entry ], [ %x.addr.1.lcssa, %for.inc4 ]88 %cmp = icmp slt i64 %indvars.iv, %tmp89 br i1 %cmp, label %for.body, label %for.end690 91for.body: ; preds = %for.cond92 br label %for.cond193 94for.cond1: ; preds = %for.inc, %for.body95 %x.addr.1 = phi i32 [ %x.addr.0, %for.body ], [ %add, %for.inc ]96 %j.0 = phi i32 [ 3, %for.body ], [ %inc, %for.inc ]97 %exitcond = icmp ne i32 %j.0, %N98 br i1 %exitcond, label %for.body3, label %for.end99 100for.body3: ; preds = %for.cond1101 br label %for.inc102 103for.inc: ; preds = %for.body3104 %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv105 %tmp1 = load i32, ptr %arrayidx, align 4106 %add = add nsw i32 %x.addr.1, %tmp1107 %inc = add nsw i32 %j.0, 1108 br label %for.cond1109 110for.end: ; preds = %for.cond1111 %x.addr.1.lcssa = phi i32 [ %x.addr.1, %for.cond1 ]112 br label %for.inc4113 114for.inc4: ; preds = %for.end115 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1116 br label %for.cond117 118for.end6: ; preds = %for.cond119 ret i32 %x.addr.0120}121