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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_CPU_IF_REGS_H_14#define ASIC_REG_CPU_IF_REGS_H_15 16/*17 *****************************************18 * CPU_IF (Prototype: CPU_IF)19 *****************************************20 */21 22#define mmCPU_IF_ARUSER_OVR 0x44210423 24#define mmCPU_IF_ARUSER_OVR_EN 0x44210825 26#define mmCPU_IF_AWUSER_OVR 0x44210C27 28#define mmCPU_IF_AWUSER_OVR_EN 0x44211029 30#define mmCPU_IF_AXCACHE_OVR 0x44211431 32#define mmCPU_IF_LOCK_OVR 0x44211833 34#define mmCPU_IF_PROT_OVR 0x44211C35 36#define mmCPU_IF_MAX_OUTSTANDING 0x44212037 38#define mmCPU_IF_EARLY_BRESP_EN 0x44212439 40#define mmCPU_IF_FORCE_RSP_OK 0x44212841 42#define mmCPU_IF_CPU_MSB_ADDR 0x44212C43 44#define mmCPU_IF_AXI_SPLIT_INTR 0x44213045 46#define mmCPU_IF_TOTAL_WR_CNT 0x44214047 48#define mmCPU_IF_INFLIGHT_WR_CNT 0x44214449 50#define mmCPU_IF_TOTAL_RD_CNT 0x44215051 52#define mmCPU_IF_INFLIGHT_RD_CNT 0x44215453 54#define mmCPU_IF_PF_PQ_PI 0x44220055 56#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x44220457 58#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x44220859 60#define mmCPU_IF_PQ_LENGTH 0x44220C61 62#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x44221063 64#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x44221465 66#define mmCPU_IF_CQ_LENGTH 0x44221867 68#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x44222069 70#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x44222471 72#define mmCPU_IF_EQ_LENGTH 0x44222873 74#define mmCPU_IF_EQ_RD_OFFS 0x44222C75 76#define mmCPU_IF_QUEUE_INIT 0x44223077 78#define mmCPU_IF_TPC_SERR_INTR_STS 0x44230079 80#define mmCPU_IF_TPC_SERR_INTR_CLR 0x44230481 82#define mmCPU_IF_TPC_SERR_INTR_MASK 0x44230883 84#define mmCPU_IF_TPC_DERR_INTR_STS 0x44231085 86#define mmCPU_IF_TPC_DERR_INTR_CLR 0x44231487 88#define mmCPU_IF_TPC_DERR_INTR_MASK 0x44231889 90#define mmCPU_IF_DMA_SERR_INTR_STS 0x44232091 92#define mmCPU_IF_DMA_SERR_INTR_CLR 0x44232493 94#define mmCPU_IF_DMA_SERR_INTR_MASK 0x44232895 96#define mmCPU_IF_DMA_DERR_INTR_STS 0x44233097 98#define mmCPU_IF_DMA_DERR_INTR_CLR 0x44233499 100#define mmCPU_IF_DMA_DERR_INTR_MASK 0x442338101 102#define mmCPU_IF_SRAM_SERR_INTR_STS 0x442340103 104#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x442344105 106#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x442348107 108#define mmCPU_IF_SRAM_DERR_INTR_STS 0x442350109 110#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x442354111 112#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x442358113 114#define mmCPU_IF_NIC_SERR_INTR_STS 0x442360115 116#define mmCPU_IF_NIC_SERR_INTR_CLR 0x442364117 118#define mmCPU_IF_NIC_SERR_INTR_MASK 0x442368119 120#define mmCPU_IF_NIC_DERR_INTR_STS 0x442370121 122#define mmCPU_IF_NIC_DERR_INTR_CLR 0x442374123 124#define mmCPU_IF_NIC_DERR_INTR_MASK 0x442378125 126#define mmCPU_IF_DMA_IF_SERR_INTR_STS 0x442380127 128#define mmCPU_IF_DMA_IF_SERR_INTR_CLR 0x442384129 130#define mmCPU_IF_DMA_IF_SERR_INTR_MASK 0x442388131 132#define mmCPU_IF_DMA_IF_DERR_INTR_STS 0x442390133 134#define mmCPU_IF_DMA_IF_DERR_INTR_CLR 0x442394135 136#define mmCPU_IF_DMA_IF_DERR_INTR_MASK 0x442398137 138#define mmCPU_IF_HBM_SERR_INTR_STS 0x4423A0139 140#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4423A4141 142#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4423A8143 144#define mmCPU_IF_HBM_DERR_INTR_STS 0x4423B0145 146#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4423B4147 148#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4423B8149 150#define mmCPU_IF_PLL_SEI_INTR_STS 0x442400151 152#define mmCPU_IF_PLL_SEI_INTR_CLR 0x442404153 154#define mmCPU_IF_PLL_SEI_INTR_MASK 0x442408155 156#define mmCPU_IF_NIC_SEI_INTR_STS 0x442410157 158#define mmCPU_IF_NIC_SEI_INTR_CLR 0x442414159 160#define mmCPU_IF_NIC_SEI_INTR_MASK 0x442418161 162#define mmCPU_IF_DMA_SEI_INTR_STS 0x442420163 164#define mmCPU_IF_DMA_SEI_INTR_CLR 0x442424165 166#define mmCPU_IF_DMA_SEI_INTR_MASK 0x442428167 168#define mmCPU_IF_DMA_IF_SEI_INTR_STS 0x442430169 170#define mmCPU_IF_DMA_IF_SEI_INTR_CLR 0x442434171 172#define mmCPU_IF_DMA_IF_SEI_INTR_MASK 0x442438173 174#endif /* ASIC_REG_CPU_IF_REGS_H_ */175