835 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA0_QM_REGS_H_14#define ASIC_REG_DMA0_QM_REGS_H_15 16/*17 *****************************************18 * DMA0_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmDMA0_QM_GLBL_CFG0 0x50800023 24#define mmDMA0_QM_GLBL_CFG1 0x50800425 26#define mmDMA0_QM_GLBL_PROT 0x50800827 28#define mmDMA0_QM_GLBL_ERR_CFG 0x50800C29 30#define mmDMA0_QM_GLBL_SECURE_PROPS_0 0x50801031 32#define mmDMA0_QM_GLBL_SECURE_PROPS_1 0x50801433 34#define mmDMA0_QM_GLBL_SECURE_PROPS_2 0x50801835 36#define mmDMA0_QM_GLBL_SECURE_PROPS_3 0x50801C37 38#define mmDMA0_QM_GLBL_SECURE_PROPS_4 0x50802039 40#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 0x50802441 42#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 0x50802843 44#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 0x50802C45 46#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 0x50803047 48#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 0x50803449 50#define mmDMA0_QM_GLBL_STS0 0x50803851 52#define mmDMA0_QM_GLBL_STS1_0 0x50804053 54#define mmDMA0_QM_GLBL_STS1_1 0x50804455 56#define mmDMA0_QM_GLBL_STS1_2 0x50804857 58#define mmDMA0_QM_GLBL_STS1_3 0x50804C59 60#define mmDMA0_QM_GLBL_STS1_4 0x50805061 62#define mmDMA0_QM_GLBL_MSG_EN_0 0x50805463 64#define mmDMA0_QM_GLBL_MSG_EN_1 0x50805865 66#define mmDMA0_QM_GLBL_MSG_EN_2 0x50805C67 68#define mmDMA0_QM_GLBL_MSG_EN_3 0x50806069 70#define mmDMA0_QM_GLBL_MSG_EN_4 0x50806871 72#define mmDMA0_QM_PQ_BASE_LO_0 0x50807073 74#define mmDMA0_QM_PQ_BASE_LO_1 0x50807475 76#define mmDMA0_QM_PQ_BASE_LO_2 0x50807877 78#define mmDMA0_QM_PQ_BASE_LO_3 0x50807C79 80#define mmDMA0_QM_PQ_BASE_HI_0 0x50808081 82#define mmDMA0_QM_PQ_BASE_HI_1 0x50808483 84#define mmDMA0_QM_PQ_BASE_HI_2 0x50808885 86#define mmDMA0_QM_PQ_BASE_HI_3 0x50808C87 88#define mmDMA0_QM_PQ_SIZE_0 0x50809089 90#define mmDMA0_QM_PQ_SIZE_1 0x50809491 92#define mmDMA0_QM_PQ_SIZE_2 0x50809893 94#define mmDMA0_QM_PQ_SIZE_3 0x50809C95 96#define mmDMA0_QM_PQ_PI_0 0x5080A097 98#define mmDMA0_QM_PQ_PI_1 0x5080A499 100#define mmDMA0_QM_PQ_PI_2 0x5080A8101 102#define mmDMA0_QM_PQ_PI_3 0x5080AC103 104#define mmDMA0_QM_PQ_CI_0 0x5080B0105 106#define mmDMA0_QM_PQ_CI_1 0x5080B4107 108#define mmDMA0_QM_PQ_CI_2 0x5080B8109 110#define mmDMA0_QM_PQ_CI_3 0x5080BC111 112#define mmDMA0_QM_PQ_CFG0_0 0x5080C0113 114#define mmDMA0_QM_PQ_CFG0_1 0x5080C4115 116#define mmDMA0_QM_PQ_CFG0_2 0x5080C8117 118#define mmDMA0_QM_PQ_CFG0_3 0x5080CC119 120#define mmDMA0_QM_PQ_CFG1_0 0x5080D0121 122#define mmDMA0_QM_PQ_CFG1_1 0x5080D4123 124#define mmDMA0_QM_PQ_CFG1_2 0x5080D8125 126#define mmDMA0_QM_PQ_CFG1_3 0x5080DC127 128#define mmDMA0_QM_PQ_ARUSER_31_11_0 0x5080E0129 130#define mmDMA0_QM_PQ_ARUSER_31_11_1 0x5080E4131 132#define mmDMA0_QM_PQ_ARUSER_31_11_2 0x5080E8133 134#define mmDMA0_QM_PQ_ARUSER_31_11_3 0x5080EC135 136#define mmDMA0_QM_PQ_STS0_0 0x5080F0137 138#define mmDMA0_QM_PQ_STS0_1 0x5080F4139 140#define mmDMA0_QM_PQ_STS0_2 0x5080F8141 142#define mmDMA0_QM_PQ_STS0_3 0x5080FC143 144#define mmDMA0_QM_PQ_STS1_0 0x508100145 146#define mmDMA0_QM_PQ_STS1_1 0x508104147 148#define mmDMA0_QM_PQ_STS1_2 0x508108149 150#define mmDMA0_QM_PQ_STS1_3 0x50810C151 152#define mmDMA0_QM_CQ_CFG0_0 0x508110153 154#define mmDMA0_QM_CQ_CFG0_1 0x508114155 156#define mmDMA0_QM_CQ_CFG0_2 0x508118157 158#define mmDMA0_QM_CQ_CFG0_3 0x50811C159 160#define mmDMA0_QM_CQ_CFG0_4 0x508120161 162#define mmDMA0_QM_CQ_CFG1_0 0x508124163 164#define mmDMA0_QM_CQ_CFG1_1 0x508128165 166#define mmDMA0_QM_CQ_CFG1_2 0x50812C167 168#define mmDMA0_QM_CQ_CFG1_3 0x508130169 170#define mmDMA0_QM_CQ_CFG1_4 0x508134171 172#define mmDMA0_QM_CQ_ARUSER_31_11_0 0x508138173 174#define mmDMA0_QM_CQ_ARUSER_31_11_1 0x50813C175 176#define mmDMA0_QM_CQ_ARUSER_31_11_2 0x508140177 178#define mmDMA0_QM_CQ_ARUSER_31_11_3 0x508144179 180#define mmDMA0_QM_CQ_ARUSER_31_11_4 0x508148181 182#define mmDMA0_QM_CQ_STS0_0 0x50814C183 184#define mmDMA0_QM_CQ_STS0_1 0x508150185 186#define mmDMA0_QM_CQ_STS0_2 0x508154187 188#define mmDMA0_QM_CQ_STS0_3 0x508158189 190#define mmDMA0_QM_CQ_STS0_4 0x50815C191 192#define mmDMA0_QM_CQ_STS1_0 0x508160193 194#define mmDMA0_QM_CQ_STS1_1 0x508164195 196#define mmDMA0_QM_CQ_STS1_2 0x508168197 198#define mmDMA0_QM_CQ_STS1_3 0x50816C199 200#define mmDMA0_QM_CQ_STS1_4 0x508170201 202#define mmDMA0_QM_CQ_PTR_LO_0 0x508174203 204#define mmDMA0_QM_CQ_PTR_HI_0 0x508178205 206#define mmDMA0_QM_CQ_TSIZE_0 0x50817C207 208#define mmDMA0_QM_CQ_CTL_0 0x508180209 210#define mmDMA0_QM_CQ_PTR_LO_1 0x508184211 212#define mmDMA0_QM_CQ_PTR_HI_1 0x508188213 214#define mmDMA0_QM_CQ_TSIZE_1 0x50818C215 216#define mmDMA0_QM_CQ_CTL_1 0x508190217 218#define mmDMA0_QM_CQ_PTR_LO_2 0x508194219 220#define mmDMA0_QM_CQ_PTR_HI_2 0x508198221 222#define mmDMA0_QM_CQ_TSIZE_2 0x50819C223 224#define mmDMA0_QM_CQ_CTL_2 0x5081A0225 226#define mmDMA0_QM_CQ_PTR_LO_3 0x5081A4227 228#define mmDMA0_QM_CQ_PTR_HI_3 0x5081A8229 230#define mmDMA0_QM_CQ_TSIZE_3 0x5081AC231 232#define mmDMA0_QM_CQ_CTL_3 0x5081B0233 234#define mmDMA0_QM_CQ_PTR_LO_4 0x5081B4235 236#define mmDMA0_QM_CQ_PTR_HI_4 0x5081B8237 238#define mmDMA0_QM_CQ_TSIZE_4 0x5081BC239 240#define mmDMA0_QM_CQ_CTL_4 0x5081C0241 242#define mmDMA0_QM_CQ_PTR_LO_STS_0 0x5081C4243 244#define mmDMA0_QM_CQ_PTR_LO_STS_1 0x5081C8245 246#define mmDMA0_QM_CQ_PTR_LO_STS_2 0x5081CC247 248#define mmDMA0_QM_CQ_PTR_LO_STS_3 0x5081D0249 250#define mmDMA0_QM_CQ_PTR_LO_STS_4 0x5081D4251 252#define mmDMA0_QM_CQ_PTR_HI_STS_0 0x5081D8253 254#define mmDMA0_QM_CQ_PTR_HI_STS_1 0x5081DC255 256#define mmDMA0_QM_CQ_PTR_HI_STS_2 0x5081E0257 258#define mmDMA0_QM_CQ_PTR_HI_STS_3 0x5081E4259 260#define mmDMA0_QM_CQ_PTR_HI_STS_4 0x5081E8261 262#define mmDMA0_QM_CQ_TSIZE_STS_0 0x5081EC263 264#define mmDMA0_QM_CQ_TSIZE_STS_1 0x5081F0265 266#define mmDMA0_QM_CQ_TSIZE_STS_2 0x5081F4267 268#define mmDMA0_QM_CQ_TSIZE_STS_3 0x5081F8269 270#define mmDMA0_QM_CQ_TSIZE_STS_4 0x5081FC271 272#define mmDMA0_QM_CQ_CTL_STS_0 0x508200273 274#define mmDMA0_QM_CQ_CTL_STS_1 0x508204275 276#define mmDMA0_QM_CQ_CTL_STS_2 0x508208277 278#define mmDMA0_QM_CQ_CTL_STS_3 0x50820C279 280#define mmDMA0_QM_CQ_CTL_STS_4 0x508210281 282#define mmDMA0_QM_CQ_IFIFO_CNT_0 0x508214283 284#define mmDMA0_QM_CQ_IFIFO_CNT_1 0x508218285 286#define mmDMA0_QM_CQ_IFIFO_CNT_2 0x50821C287 288#define mmDMA0_QM_CQ_IFIFO_CNT_3 0x508220289 290#define mmDMA0_QM_CQ_IFIFO_CNT_4 0x508224291 292#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x508228293 294#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x50822C295 296#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x508230297 298#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x508234299 300#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x508238301 302#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x50823C303 304#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x508240305 306#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x508244307 308#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x508248309 310#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x50824C311 312#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x508250313 314#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x508254315 316#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x508258317 318#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x50825C319 320#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x508260321 322#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x508264323 324#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x508268325 326#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x50826C327 328#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x508270329 330#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x508274331 332#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x508278333 334#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x50827C335 336#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x508280337 338#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x508284339 340#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x508288341 342#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x50828C343 344#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x508290345 346#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x508294347 348#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x508298349 350#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x50829C351 352#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x5082A0353 354#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x5082A4355 356#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x5082A8357 358#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x5082AC359 360#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x5082B0361 362#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x5082B4363 364#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x5082B8365 366#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x5082BC367 368#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x5082C0369 370#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x5082C4371 372#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 0x5082C8373 374#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 0x5082CC375 376#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 0x5082D0377 378#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 0x5082D4379 380#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 0x5082D8381 382#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5082E0383 384#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5082E4385 386#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5082E8387 388#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5082EC389 390#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5082F0391 392#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5082F4393 394#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5082F8395 396#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5082FC397 398#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x508300399 400#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x508304401 402#define mmDMA0_QM_CP_FENCE0_RDATA_0 0x508308403 404#define mmDMA0_QM_CP_FENCE0_RDATA_1 0x50830C405 406#define mmDMA0_QM_CP_FENCE0_RDATA_2 0x508310407 408#define mmDMA0_QM_CP_FENCE0_RDATA_3 0x508314409 410#define mmDMA0_QM_CP_FENCE0_RDATA_4 0x508318411 412#define mmDMA0_QM_CP_FENCE1_RDATA_0 0x50831C413 414#define mmDMA0_QM_CP_FENCE1_RDATA_1 0x508320415 416#define mmDMA0_QM_CP_FENCE1_RDATA_2 0x508324417 418#define mmDMA0_QM_CP_FENCE1_RDATA_3 0x508328419 420#define mmDMA0_QM_CP_FENCE1_RDATA_4 0x50832C421 422#define mmDMA0_QM_CP_FENCE2_RDATA_0 0x508330423 424#define mmDMA0_QM_CP_FENCE2_RDATA_1 0x508334425 426#define mmDMA0_QM_CP_FENCE2_RDATA_2 0x508338427 428#define mmDMA0_QM_CP_FENCE2_RDATA_3 0x50833C429 430#define mmDMA0_QM_CP_FENCE2_RDATA_4 0x508340431 432#define mmDMA0_QM_CP_FENCE3_RDATA_0 0x508344433 434#define mmDMA0_QM_CP_FENCE3_RDATA_1 0x508348435 436#define mmDMA0_QM_CP_FENCE3_RDATA_2 0x50834C437 438#define mmDMA0_QM_CP_FENCE3_RDATA_3 0x508350439 440#define mmDMA0_QM_CP_FENCE3_RDATA_4 0x508354441 442#define mmDMA0_QM_CP_FENCE0_CNT_0 0x508358443 444#define mmDMA0_QM_CP_FENCE0_CNT_1 0x50835C445 446#define mmDMA0_QM_CP_FENCE0_CNT_2 0x508360447 448#define mmDMA0_QM_CP_FENCE0_CNT_3 0x508364449 450#define mmDMA0_QM_CP_FENCE0_CNT_4 0x508368451 452#define mmDMA0_QM_CP_FENCE1_CNT_0 0x50836C453 454#define mmDMA0_QM_CP_FENCE1_CNT_1 0x508370455 456#define mmDMA0_QM_CP_FENCE1_CNT_2 0x508374457 458#define mmDMA0_QM_CP_FENCE1_CNT_3 0x508378459 460#define mmDMA0_QM_CP_FENCE1_CNT_4 0x50837C461 462#define mmDMA0_QM_CP_FENCE2_CNT_0 0x508380463 464#define mmDMA0_QM_CP_FENCE2_CNT_1 0x508384465 466#define mmDMA0_QM_CP_FENCE2_CNT_2 0x508388467 468#define mmDMA0_QM_CP_FENCE2_CNT_3 0x50838C469 470#define mmDMA0_QM_CP_FENCE2_CNT_4 0x508390471 472#define mmDMA0_QM_CP_FENCE3_CNT_0 0x508394473 474#define mmDMA0_QM_CP_FENCE3_CNT_1 0x508398475 476#define mmDMA0_QM_CP_FENCE3_CNT_2 0x50839C477 478#define mmDMA0_QM_CP_FENCE3_CNT_3 0x5083A0479 480#define mmDMA0_QM_CP_FENCE3_CNT_4 0x5083A4481 482#define mmDMA0_QM_CP_STS_0 0x5083A8483 484#define mmDMA0_QM_CP_STS_1 0x5083AC485 486#define mmDMA0_QM_CP_STS_2 0x5083B0487 488#define mmDMA0_QM_CP_STS_3 0x5083B4489 490#define mmDMA0_QM_CP_STS_4 0x5083B8491 492#define mmDMA0_QM_CP_CURRENT_INST_LO_0 0x5083BC493 494#define mmDMA0_QM_CP_CURRENT_INST_LO_1 0x5083C0495 496#define mmDMA0_QM_CP_CURRENT_INST_LO_2 0x5083C4497 498#define mmDMA0_QM_CP_CURRENT_INST_LO_3 0x5083C8499 500#define mmDMA0_QM_CP_CURRENT_INST_LO_4 0x5083CC501 502#define mmDMA0_QM_CP_CURRENT_INST_HI_0 0x5083D0503 504#define mmDMA0_QM_CP_CURRENT_INST_HI_1 0x5083D4505 506#define mmDMA0_QM_CP_CURRENT_INST_HI_2 0x5083D8507 508#define mmDMA0_QM_CP_CURRENT_INST_HI_3 0x5083DC509 510#define mmDMA0_QM_CP_CURRENT_INST_HI_4 0x5083E0511 512#define mmDMA0_QM_CP_BARRIER_CFG_0 0x5083F4513 514#define mmDMA0_QM_CP_BARRIER_CFG_1 0x5083F8515 516#define mmDMA0_QM_CP_BARRIER_CFG_2 0x5083FC517 518#define mmDMA0_QM_CP_BARRIER_CFG_3 0x508400519 520#define mmDMA0_QM_CP_BARRIER_CFG_4 0x508404521 522#define mmDMA0_QM_CP_DBG_0_0 0x508408523 524#define mmDMA0_QM_CP_DBG_0_1 0x50840C525 526#define mmDMA0_QM_CP_DBG_0_2 0x508410527 528#define mmDMA0_QM_CP_DBG_0_3 0x508414529 530#define mmDMA0_QM_CP_DBG_0_4 0x508418531 532#define mmDMA0_QM_CP_ARUSER_31_11_0 0x50841C533 534#define mmDMA0_QM_CP_ARUSER_31_11_1 0x508420535 536#define mmDMA0_QM_CP_ARUSER_31_11_2 0x508424537 538#define mmDMA0_QM_CP_ARUSER_31_11_3 0x508428539 540#define mmDMA0_QM_CP_ARUSER_31_11_4 0x50842C541 542#define mmDMA0_QM_CP_AWUSER_31_11_0 0x508430543 544#define mmDMA0_QM_CP_AWUSER_31_11_1 0x508434545 546#define mmDMA0_QM_CP_AWUSER_31_11_2 0x508438547 548#define mmDMA0_QM_CP_AWUSER_31_11_3 0x50843C549 550#define mmDMA0_QM_CP_AWUSER_31_11_4 0x508440551 552#define mmDMA0_QM_ARB_CFG_0 0x508A00553 554#define mmDMA0_QM_ARB_CHOISE_Q_PUSH 0x508A04555 556#define mmDMA0_QM_ARB_WRR_WEIGHT_0 0x508A08557 558#define mmDMA0_QM_ARB_WRR_WEIGHT_1 0x508A0C559 560#define mmDMA0_QM_ARB_WRR_WEIGHT_2 0x508A10561 562#define mmDMA0_QM_ARB_WRR_WEIGHT_3 0x508A14563 564#define mmDMA0_QM_ARB_CFG_1 0x508A18565 566#define mmDMA0_QM_ARB_MST_AVAIL_CRED_0 0x508A20567 568#define mmDMA0_QM_ARB_MST_AVAIL_CRED_1 0x508A24569 570#define mmDMA0_QM_ARB_MST_AVAIL_CRED_2 0x508A28571 572#define mmDMA0_QM_ARB_MST_AVAIL_CRED_3 0x508A2C573 574#define mmDMA0_QM_ARB_MST_AVAIL_CRED_4 0x508A30575 576#define mmDMA0_QM_ARB_MST_AVAIL_CRED_5 0x508A34577 578#define mmDMA0_QM_ARB_MST_AVAIL_CRED_6 0x508A38579 580#define mmDMA0_QM_ARB_MST_AVAIL_CRED_7 0x508A3C581 582#define mmDMA0_QM_ARB_MST_AVAIL_CRED_8 0x508A40583 584#define mmDMA0_QM_ARB_MST_AVAIL_CRED_9 0x508A44585 586#define mmDMA0_QM_ARB_MST_AVAIL_CRED_10 0x508A48587 588#define mmDMA0_QM_ARB_MST_AVAIL_CRED_11 0x508A4C589 590#define mmDMA0_QM_ARB_MST_AVAIL_CRED_12 0x508A50591 592#define mmDMA0_QM_ARB_MST_AVAIL_CRED_13 0x508A54593 594#define mmDMA0_QM_ARB_MST_AVAIL_CRED_14 0x508A58595 596#define mmDMA0_QM_ARB_MST_AVAIL_CRED_15 0x508A5C597 598#define mmDMA0_QM_ARB_MST_AVAIL_CRED_16 0x508A60599 600#define mmDMA0_QM_ARB_MST_AVAIL_CRED_17 0x508A64601 602#define mmDMA0_QM_ARB_MST_AVAIL_CRED_18 0x508A68603 604#define mmDMA0_QM_ARB_MST_AVAIL_CRED_19 0x508A6C605 606#define mmDMA0_QM_ARB_MST_AVAIL_CRED_20 0x508A70607 608#define mmDMA0_QM_ARB_MST_AVAIL_CRED_21 0x508A74609 610#define mmDMA0_QM_ARB_MST_AVAIL_CRED_22 0x508A78611 612#define mmDMA0_QM_ARB_MST_AVAIL_CRED_23 0x508A7C613 614#define mmDMA0_QM_ARB_MST_AVAIL_CRED_24 0x508A80615 616#define mmDMA0_QM_ARB_MST_AVAIL_CRED_25 0x508A84617 618#define mmDMA0_QM_ARB_MST_AVAIL_CRED_26 0x508A88619 620#define mmDMA0_QM_ARB_MST_AVAIL_CRED_27 0x508A8C621 622#define mmDMA0_QM_ARB_MST_AVAIL_CRED_28 0x508A90623 624#define mmDMA0_QM_ARB_MST_AVAIL_CRED_29 0x508A94625 626#define mmDMA0_QM_ARB_MST_AVAIL_CRED_30 0x508A98627 628#define mmDMA0_QM_ARB_MST_AVAIL_CRED_31 0x508A9C629 630#define mmDMA0_QM_ARB_MST_CRED_INC 0x508AA0631 632#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x508AA4633 634#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x508AA8635 636#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x508AAC637 638#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x508AB0639 640#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x508AB4641 642#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x508AB8643 644#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x508ABC645 646#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x508AC0647 648#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x508AC4649 650#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x508AC8651 652#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x508ACC653 654#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x508AD0655 656#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x508AD4657 658#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x508AD8659 660#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x508ADC661 662#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x508AE0663 664#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x508AE4665 666#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x508AE8667 668#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x508AEC669 670#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x508AF0671 672#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x508AF4673 674#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x508AF8675 676#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x508AFC677 678#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x508B00679 680#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x508B04681 682#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x508B08683 684#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x508B0C685 686#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x508B10687 688#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x508B14689 690#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x508B18691 692#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x508B1C693 694#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x508B20695 696#define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x508B28697 698#define mmDMA0_QM_ARB_MST_SLAVE_EN 0x508B2C699 700#define mmDMA0_QM_ARB_MST_QUIET_PER 0x508B34701 702#define mmDMA0_QM_ARB_SLV_CHOISE_WDT 0x508B38703 704#define mmDMA0_QM_ARB_SLV_ID 0x508B3C705 706#define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x508B44707 708#define mmDMA0_QM_ARB_MSG_AWUSER_31_11 0x508B48709 710#define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP 0x508B4C711 712#define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x508B50713 714#define mmDMA0_QM_ARB_BASE_LO 0x508B54715 716#define mmDMA0_QM_ARB_BASE_HI 0x508B58717 718#define mmDMA0_QM_ARB_STATE_STS 0x508B80719 720#define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS 0x508B84721 722#define mmDMA0_QM_ARB_MSG_STS 0x508B88723 724#define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD 0x508B8C725 726#define mmDMA0_QM_ARB_ERR_CAUSE 0x508B9C727 728#define mmDMA0_QM_ARB_ERR_MSG_EN 0x508BA0729 730#define mmDMA0_QM_ARB_ERR_STS_DRP 0x508BA8731 732#define mmDMA0_QM_ARB_MST_CRED_STS_0 0x508BB0733 734#define mmDMA0_QM_ARB_MST_CRED_STS_1 0x508BB4735 736#define mmDMA0_QM_ARB_MST_CRED_STS_2 0x508BB8737 738#define mmDMA0_QM_ARB_MST_CRED_STS_3 0x508BBC739 740#define mmDMA0_QM_ARB_MST_CRED_STS_4 0x508BC0741 742#define mmDMA0_QM_ARB_MST_CRED_STS_5 0x508BC4743 744#define mmDMA0_QM_ARB_MST_CRED_STS_6 0x508BC8745 746#define mmDMA0_QM_ARB_MST_CRED_STS_7 0x508BCC747 748#define mmDMA0_QM_ARB_MST_CRED_STS_8 0x508BD0749 750#define mmDMA0_QM_ARB_MST_CRED_STS_9 0x508BD4751 752#define mmDMA0_QM_ARB_MST_CRED_STS_10 0x508BD8753 754#define mmDMA0_QM_ARB_MST_CRED_STS_11 0x508BDC755 756#define mmDMA0_QM_ARB_MST_CRED_STS_12 0x508BE0757 758#define mmDMA0_QM_ARB_MST_CRED_STS_13 0x508BE4759 760#define mmDMA0_QM_ARB_MST_CRED_STS_14 0x508BE8761 762#define mmDMA0_QM_ARB_MST_CRED_STS_15 0x508BEC763 764#define mmDMA0_QM_ARB_MST_CRED_STS_16 0x508BF0765 766#define mmDMA0_QM_ARB_MST_CRED_STS_17 0x508BF4767 768#define mmDMA0_QM_ARB_MST_CRED_STS_18 0x508BF8769 770#define mmDMA0_QM_ARB_MST_CRED_STS_19 0x508BFC771 772#define mmDMA0_QM_ARB_MST_CRED_STS_20 0x508C00773 774#define mmDMA0_QM_ARB_MST_CRED_STS_21 0x508C04775 776#define mmDMA0_QM_ARB_MST_CRED_STS_22 0x508C08777 778#define mmDMA0_QM_ARB_MST_CRED_STS_23 0x508C0C779 780#define mmDMA0_QM_ARB_MST_CRED_STS_24 0x508C10781 782#define mmDMA0_QM_ARB_MST_CRED_STS_25 0x508C14783 784#define mmDMA0_QM_ARB_MST_CRED_STS_26 0x508C18785 786#define mmDMA0_QM_ARB_MST_CRED_STS_27 0x508C1C787 788#define mmDMA0_QM_ARB_MST_CRED_STS_28 0x508C20789 790#define mmDMA0_QM_ARB_MST_CRED_STS_29 0x508C24791 792#define mmDMA0_QM_ARB_MST_CRED_STS_30 0x508C28793 794#define mmDMA0_QM_ARB_MST_CRED_STS_31 0x508C2C795 796#define mmDMA0_QM_CGM_CFG 0x508C70797 798#define mmDMA0_QM_CGM_STS 0x508C74799 800#define mmDMA0_QM_CGM_CFG1 0x508C78801 802#define mmDMA0_QM_LOCAL_RANGE_BASE 0x508C80803 804#define mmDMA0_QM_LOCAL_RANGE_SIZE 0x508C84805 806#define mmDMA0_QM_CSMR_STRICT_PRIO_CFG 0x508C90807 808#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x508C94809 810#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x508C98811 812#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x508C9C813 814#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x508CA0815 816#define mmDMA0_QM_GLBL_AXCACHE 0x508CA4817 818#define mmDMA0_QM_IND_GW_APB_CFG 0x508CB0819 820#define mmDMA0_QM_IND_GW_APB_WDATA 0x508CB4821 822#define mmDMA0_QM_IND_GW_APB_RDATA 0x508CB8823 824#define mmDMA0_QM_IND_GW_APB_STATUS 0x508CBC825 826#define mmDMA0_QM_GLBL_ERR_ADDR_LO 0x508CD0827 828#define mmDMA0_QM_GLBL_ERR_ADDR_HI 0x508CD4829 830#define mmDMA0_QM_GLBL_ERR_WDATA 0x508CD8831 832#define mmDMA0_QM_GLBL_MEM_INIT_BUSY 0x508D00833 834#endif /* ASIC_REG_DMA0_QM_REGS_H_ */835