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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA1_QM_REGS_H_14#define ASIC_REG_DMA1_QM_REGS_H_15 16/*17 *****************************************18 * DMA1_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmDMA1_QM_GLBL_CFG0 0x52800023 24#define mmDMA1_QM_GLBL_CFG1 0x52800425 26#define mmDMA1_QM_GLBL_PROT 0x52800827 28#define mmDMA1_QM_GLBL_ERR_CFG 0x52800C29 30#define mmDMA1_QM_GLBL_SECURE_PROPS_0 0x52801031 32#define mmDMA1_QM_GLBL_SECURE_PROPS_1 0x52801433 34#define mmDMA1_QM_GLBL_SECURE_PROPS_2 0x52801835 36#define mmDMA1_QM_GLBL_SECURE_PROPS_3 0x52801C37 38#define mmDMA1_QM_GLBL_SECURE_PROPS_4 0x52802039 40#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 0x52802441 42#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 0x52802843 44#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 0x52802C45 46#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 0x52803047 48#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 0x52803449 50#define mmDMA1_QM_GLBL_STS0 0x52803851 52#define mmDMA1_QM_GLBL_STS1_0 0x52804053 54#define mmDMA1_QM_GLBL_STS1_1 0x52804455 56#define mmDMA1_QM_GLBL_STS1_2 0x52804857 58#define mmDMA1_QM_GLBL_STS1_3 0x52804C59 60#define mmDMA1_QM_GLBL_STS1_4 0x52805061 62#define mmDMA1_QM_GLBL_MSG_EN_0 0x52805463 64#define mmDMA1_QM_GLBL_MSG_EN_1 0x52805865 66#define mmDMA1_QM_GLBL_MSG_EN_2 0x52805C67 68#define mmDMA1_QM_GLBL_MSG_EN_3 0x52806069 70#define mmDMA1_QM_GLBL_MSG_EN_4 0x52806871 72#define mmDMA1_QM_PQ_BASE_LO_0 0x52807073 74#define mmDMA1_QM_PQ_BASE_LO_1 0x52807475 76#define mmDMA1_QM_PQ_BASE_LO_2 0x52807877 78#define mmDMA1_QM_PQ_BASE_LO_3 0x52807C79 80#define mmDMA1_QM_PQ_BASE_HI_0 0x52808081 82#define mmDMA1_QM_PQ_BASE_HI_1 0x52808483 84#define mmDMA1_QM_PQ_BASE_HI_2 0x52808885 86#define mmDMA1_QM_PQ_BASE_HI_3 0x52808C87 88#define mmDMA1_QM_PQ_SIZE_0 0x52809089 90#define mmDMA1_QM_PQ_SIZE_1 0x52809491 92#define mmDMA1_QM_PQ_SIZE_2 0x52809893 94#define mmDMA1_QM_PQ_SIZE_3 0x52809C95 96#define mmDMA1_QM_PQ_PI_0 0x5280A097 98#define mmDMA1_QM_PQ_PI_1 0x5280A499 100#define mmDMA1_QM_PQ_PI_2 0x5280A8101 102#define mmDMA1_QM_PQ_PI_3 0x5280AC103 104#define mmDMA1_QM_PQ_CI_0 0x5280B0105 106#define mmDMA1_QM_PQ_CI_1 0x5280B4107 108#define mmDMA1_QM_PQ_CI_2 0x5280B8109 110#define mmDMA1_QM_PQ_CI_3 0x5280BC111 112#define mmDMA1_QM_PQ_CFG0_0 0x5280C0113 114#define mmDMA1_QM_PQ_CFG0_1 0x5280C4115 116#define mmDMA1_QM_PQ_CFG0_2 0x5280C8117 118#define mmDMA1_QM_PQ_CFG0_3 0x5280CC119 120#define mmDMA1_QM_PQ_CFG1_0 0x5280D0121 122#define mmDMA1_QM_PQ_CFG1_1 0x5280D4123 124#define mmDMA1_QM_PQ_CFG1_2 0x5280D8125 126#define mmDMA1_QM_PQ_CFG1_3 0x5280DC127 128#define mmDMA1_QM_PQ_ARUSER_31_11_0 0x5280E0129 130#define mmDMA1_QM_PQ_ARUSER_31_11_1 0x5280E4131 132#define mmDMA1_QM_PQ_ARUSER_31_11_2 0x5280E8133 134#define mmDMA1_QM_PQ_ARUSER_31_11_3 0x5280EC135 136#define mmDMA1_QM_PQ_STS0_0 0x5280F0137 138#define mmDMA1_QM_PQ_STS0_1 0x5280F4139 140#define mmDMA1_QM_PQ_STS0_2 0x5280F8141 142#define mmDMA1_QM_PQ_STS0_3 0x5280FC143 144#define mmDMA1_QM_PQ_STS1_0 0x528100145 146#define mmDMA1_QM_PQ_STS1_1 0x528104147 148#define mmDMA1_QM_PQ_STS1_2 0x528108149 150#define mmDMA1_QM_PQ_STS1_3 0x52810C151 152#define mmDMA1_QM_CQ_CFG0_0 0x528110153 154#define mmDMA1_QM_CQ_CFG0_1 0x528114155 156#define mmDMA1_QM_CQ_CFG0_2 0x528118157 158#define mmDMA1_QM_CQ_CFG0_3 0x52811C159 160#define mmDMA1_QM_CQ_CFG0_4 0x528120161 162#define mmDMA1_QM_CQ_CFG1_0 0x528124163 164#define mmDMA1_QM_CQ_CFG1_1 0x528128165 166#define mmDMA1_QM_CQ_CFG1_2 0x52812C167 168#define mmDMA1_QM_CQ_CFG1_3 0x528130169 170#define mmDMA1_QM_CQ_CFG1_4 0x528134171 172#define mmDMA1_QM_CQ_ARUSER_31_11_0 0x528138173 174#define mmDMA1_QM_CQ_ARUSER_31_11_1 0x52813C175 176#define mmDMA1_QM_CQ_ARUSER_31_11_2 0x528140177 178#define mmDMA1_QM_CQ_ARUSER_31_11_3 0x528144179 180#define mmDMA1_QM_CQ_ARUSER_31_11_4 0x528148181 182#define mmDMA1_QM_CQ_STS0_0 0x52814C183 184#define mmDMA1_QM_CQ_STS0_1 0x528150185 186#define mmDMA1_QM_CQ_STS0_2 0x528154187 188#define mmDMA1_QM_CQ_STS0_3 0x528158189 190#define mmDMA1_QM_CQ_STS0_4 0x52815C191 192#define mmDMA1_QM_CQ_STS1_0 0x528160193 194#define mmDMA1_QM_CQ_STS1_1 0x528164195 196#define mmDMA1_QM_CQ_STS1_2 0x528168197 198#define mmDMA1_QM_CQ_STS1_3 0x52816C199 200#define mmDMA1_QM_CQ_STS1_4 0x528170201 202#define mmDMA1_QM_CQ_PTR_LO_0 0x528174203 204#define mmDMA1_QM_CQ_PTR_HI_0 0x528178205 206#define mmDMA1_QM_CQ_TSIZE_0 0x52817C207 208#define mmDMA1_QM_CQ_CTL_0 0x528180209 210#define mmDMA1_QM_CQ_PTR_LO_1 0x528184211 212#define mmDMA1_QM_CQ_PTR_HI_1 0x528188213 214#define mmDMA1_QM_CQ_TSIZE_1 0x52818C215 216#define mmDMA1_QM_CQ_CTL_1 0x528190217 218#define mmDMA1_QM_CQ_PTR_LO_2 0x528194219 220#define mmDMA1_QM_CQ_PTR_HI_2 0x528198221 222#define mmDMA1_QM_CQ_TSIZE_2 0x52819C223 224#define mmDMA1_QM_CQ_CTL_2 0x5281A0225 226#define mmDMA1_QM_CQ_PTR_LO_3 0x5281A4227 228#define mmDMA1_QM_CQ_PTR_HI_3 0x5281A8229 230#define mmDMA1_QM_CQ_TSIZE_3 0x5281AC231 232#define mmDMA1_QM_CQ_CTL_3 0x5281B0233 234#define mmDMA1_QM_CQ_PTR_LO_4 0x5281B4235 236#define mmDMA1_QM_CQ_PTR_HI_4 0x5281B8237 238#define mmDMA1_QM_CQ_TSIZE_4 0x5281BC239 240#define mmDMA1_QM_CQ_CTL_4 0x5281C0241 242#define mmDMA1_QM_CQ_PTR_LO_STS_0 0x5281C4243 244#define mmDMA1_QM_CQ_PTR_LO_STS_1 0x5281C8245 246#define mmDMA1_QM_CQ_PTR_LO_STS_2 0x5281CC247 248#define mmDMA1_QM_CQ_PTR_LO_STS_3 0x5281D0249 250#define mmDMA1_QM_CQ_PTR_LO_STS_4 0x5281D4251 252#define mmDMA1_QM_CQ_PTR_HI_STS_0 0x5281D8253 254#define mmDMA1_QM_CQ_PTR_HI_STS_1 0x5281DC255 256#define mmDMA1_QM_CQ_PTR_HI_STS_2 0x5281E0257 258#define mmDMA1_QM_CQ_PTR_HI_STS_3 0x5281E4259 260#define mmDMA1_QM_CQ_PTR_HI_STS_4 0x5281E8261 262#define mmDMA1_QM_CQ_TSIZE_STS_0 0x5281EC263 264#define mmDMA1_QM_CQ_TSIZE_STS_1 0x5281F0265 266#define mmDMA1_QM_CQ_TSIZE_STS_2 0x5281F4267 268#define mmDMA1_QM_CQ_TSIZE_STS_3 0x5281F8269 270#define mmDMA1_QM_CQ_TSIZE_STS_4 0x5281FC271 272#define mmDMA1_QM_CQ_CTL_STS_0 0x528200273 274#define mmDMA1_QM_CQ_CTL_STS_1 0x528204275 276#define mmDMA1_QM_CQ_CTL_STS_2 0x528208277 278#define mmDMA1_QM_CQ_CTL_STS_3 0x52820C279 280#define mmDMA1_QM_CQ_CTL_STS_4 0x528210281 282#define mmDMA1_QM_CQ_IFIFO_CNT_0 0x528214283 284#define mmDMA1_QM_CQ_IFIFO_CNT_1 0x528218285 286#define mmDMA1_QM_CQ_IFIFO_CNT_2 0x52821C287 288#define mmDMA1_QM_CQ_IFIFO_CNT_3 0x528220289 290#define mmDMA1_QM_CQ_IFIFO_CNT_4 0x528224291 292#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 0x528228293 294#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 0x52822C295 296#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 0x528230297 298#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 0x528234299 300#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 0x528238301 302#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 0x52823C303 304#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 0x528240305 306#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 0x528244307 308#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 0x528248309 310#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 0x52824C311 312#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 0x528250313 314#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 0x528254315 316#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 0x528258317 318#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 0x52825C319 320#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 0x528260321 322#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 0x528264323 324#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 0x528268325 326#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 0x52826C327 328#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 0x528270329 330#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 0x528274331 332#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 0x528278333 334#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 0x52827C335 336#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 0x528280337 338#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 0x528284339 340#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 0x528288341 342#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 0x52828C343 344#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 0x528290345 346#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 0x528294347 348#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 0x528298349 350#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 0x52829C351 352#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 0x5282A0353 354#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 0x5282A4355 356#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 0x5282A8357 358#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 0x5282AC359 360#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 0x5282B0361 362#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 0x5282B4363 364#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 0x5282B8365 366#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 0x5282BC367 368#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 0x5282C0369 370#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 0x5282C4371 372#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 0x5282C8373 374#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 0x5282CC375 376#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 0x5282D0377 378#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 0x5282D4379 380#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 0x5282D8381 382#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5282E0383 384#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5282E4385 386#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5282E8387 388#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5282EC389 390#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5282F0391 392#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5282F4393 394#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5282F8395 396#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5282FC397 398#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x528300399 400#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x528304401 402#define mmDMA1_QM_CP_FENCE0_RDATA_0 0x528308403 404#define mmDMA1_QM_CP_FENCE0_RDATA_1 0x52830C405 406#define mmDMA1_QM_CP_FENCE0_RDATA_2 0x528310407 408#define mmDMA1_QM_CP_FENCE0_RDATA_3 0x528314409 410#define mmDMA1_QM_CP_FENCE0_RDATA_4 0x528318411 412#define mmDMA1_QM_CP_FENCE1_RDATA_0 0x52831C413 414#define mmDMA1_QM_CP_FENCE1_RDATA_1 0x528320415 416#define mmDMA1_QM_CP_FENCE1_RDATA_2 0x528324417 418#define mmDMA1_QM_CP_FENCE1_RDATA_3 0x528328419 420#define mmDMA1_QM_CP_FENCE1_RDATA_4 0x52832C421 422#define mmDMA1_QM_CP_FENCE2_RDATA_0 0x528330423 424#define mmDMA1_QM_CP_FENCE2_RDATA_1 0x528334425 426#define mmDMA1_QM_CP_FENCE2_RDATA_2 0x528338427 428#define mmDMA1_QM_CP_FENCE2_RDATA_3 0x52833C429 430#define mmDMA1_QM_CP_FENCE2_RDATA_4 0x528340431 432#define mmDMA1_QM_CP_FENCE3_RDATA_0 0x528344433 434#define mmDMA1_QM_CP_FENCE3_RDATA_1 0x528348435 436#define mmDMA1_QM_CP_FENCE3_RDATA_2 0x52834C437 438#define mmDMA1_QM_CP_FENCE3_RDATA_3 0x528350439 440#define mmDMA1_QM_CP_FENCE3_RDATA_4 0x528354441 442#define mmDMA1_QM_CP_FENCE0_CNT_0 0x528358443 444#define mmDMA1_QM_CP_FENCE0_CNT_1 0x52835C445 446#define mmDMA1_QM_CP_FENCE0_CNT_2 0x528360447 448#define mmDMA1_QM_CP_FENCE0_CNT_3 0x528364449 450#define mmDMA1_QM_CP_FENCE0_CNT_4 0x528368451 452#define mmDMA1_QM_CP_FENCE1_CNT_0 0x52836C453 454#define mmDMA1_QM_CP_FENCE1_CNT_1 0x528370455 456#define mmDMA1_QM_CP_FENCE1_CNT_2 0x528374457 458#define mmDMA1_QM_CP_FENCE1_CNT_3 0x528378459 460#define mmDMA1_QM_CP_FENCE1_CNT_4 0x52837C461 462#define mmDMA1_QM_CP_FENCE2_CNT_0 0x528380463 464#define mmDMA1_QM_CP_FENCE2_CNT_1 0x528384465 466#define mmDMA1_QM_CP_FENCE2_CNT_2 0x528388467 468#define mmDMA1_QM_CP_FENCE2_CNT_3 0x52838C469 470#define mmDMA1_QM_CP_FENCE2_CNT_4 0x528390471 472#define mmDMA1_QM_CP_FENCE3_CNT_0 0x528394473 474#define mmDMA1_QM_CP_FENCE3_CNT_1 0x528398475 476#define mmDMA1_QM_CP_FENCE3_CNT_2 0x52839C477 478#define mmDMA1_QM_CP_FENCE3_CNT_3 0x5283A0479 480#define mmDMA1_QM_CP_FENCE3_CNT_4 0x5283A4481 482#define mmDMA1_QM_CP_STS_0 0x5283A8483 484#define mmDMA1_QM_CP_STS_1 0x5283AC485 486#define mmDMA1_QM_CP_STS_2 0x5283B0487 488#define mmDMA1_QM_CP_STS_3 0x5283B4489 490#define mmDMA1_QM_CP_STS_4 0x5283B8491 492#define mmDMA1_QM_CP_CURRENT_INST_LO_0 0x5283BC493 494#define mmDMA1_QM_CP_CURRENT_INST_LO_1 0x5283C0495 496#define mmDMA1_QM_CP_CURRENT_INST_LO_2 0x5283C4497 498#define mmDMA1_QM_CP_CURRENT_INST_LO_3 0x5283C8499 500#define mmDMA1_QM_CP_CURRENT_INST_LO_4 0x5283CC501 502#define mmDMA1_QM_CP_CURRENT_INST_HI_0 0x5283D0503 504#define mmDMA1_QM_CP_CURRENT_INST_HI_1 0x5283D4505 506#define mmDMA1_QM_CP_CURRENT_INST_HI_2 0x5283D8507 508#define mmDMA1_QM_CP_CURRENT_INST_HI_3 0x5283DC509 510#define mmDMA1_QM_CP_CURRENT_INST_HI_4 0x5283E0511 512#define mmDMA1_QM_CP_BARRIER_CFG_0 0x5283F4513 514#define mmDMA1_QM_CP_BARRIER_CFG_1 0x5283F8515 516#define mmDMA1_QM_CP_BARRIER_CFG_2 0x5283FC517 518#define mmDMA1_QM_CP_BARRIER_CFG_3 0x528400519 520#define mmDMA1_QM_CP_BARRIER_CFG_4 0x528404521 522#define mmDMA1_QM_CP_DBG_0_0 0x528408523 524#define mmDMA1_QM_CP_DBG_0_1 0x52840C525 526#define mmDMA1_QM_CP_DBG_0_2 0x528410527 528#define mmDMA1_QM_CP_DBG_0_3 0x528414529 530#define mmDMA1_QM_CP_DBG_0_4 0x528418531 532#define mmDMA1_QM_CP_ARUSER_31_11_0 0x52841C533 534#define mmDMA1_QM_CP_ARUSER_31_11_1 0x528420535 536#define mmDMA1_QM_CP_ARUSER_31_11_2 0x528424537 538#define mmDMA1_QM_CP_ARUSER_31_11_3 0x528428539 540#define mmDMA1_QM_CP_ARUSER_31_11_4 0x52842C541 542#define mmDMA1_QM_CP_AWUSER_31_11_0 0x528430543 544#define mmDMA1_QM_CP_AWUSER_31_11_1 0x528434545 546#define mmDMA1_QM_CP_AWUSER_31_11_2 0x528438547 548#define mmDMA1_QM_CP_AWUSER_31_11_3 0x52843C549 550#define mmDMA1_QM_CP_AWUSER_31_11_4 0x528440551 552#define mmDMA1_QM_ARB_CFG_0 0x528A00553 554#define mmDMA1_QM_ARB_CHOISE_Q_PUSH 0x528A04555 556#define mmDMA1_QM_ARB_WRR_WEIGHT_0 0x528A08557 558#define mmDMA1_QM_ARB_WRR_WEIGHT_1 0x528A0C559 560#define mmDMA1_QM_ARB_WRR_WEIGHT_2 0x528A10561 562#define mmDMA1_QM_ARB_WRR_WEIGHT_3 0x528A14563 564#define mmDMA1_QM_ARB_CFG_1 0x528A18565 566#define mmDMA1_QM_ARB_MST_AVAIL_CRED_0 0x528A20567 568#define mmDMA1_QM_ARB_MST_AVAIL_CRED_1 0x528A24569 570#define mmDMA1_QM_ARB_MST_AVAIL_CRED_2 0x528A28571 572#define mmDMA1_QM_ARB_MST_AVAIL_CRED_3 0x528A2C573 574#define mmDMA1_QM_ARB_MST_AVAIL_CRED_4 0x528A30575 576#define mmDMA1_QM_ARB_MST_AVAIL_CRED_5 0x528A34577 578#define mmDMA1_QM_ARB_MST_AVAIL_CRED_6 0x528A38579 580#define mmDMA1_QM_ARB_MST_AVAIL_CRED_7 0x528A3C581 582#define mmDMA1_QM_ARB_MST_AVAIL_CRED_8 0x528A40583 584#define mmDMA1_QM_ARB_MST_AVAIL_CRED_9 0x528A44585 586#define mmDMA1_QM_ARB_MST_AVAIL_CRED_10 0x528A48587 588#define mmDMA1_QM_ARB_MST_AVAIL_CRED_11 0x528A4C589 590#define mmDMA1_QM_ARB_MST_AVAIL_CRED_12 0x528A50591 592#define mmDMA1_QM_ARB_MST_AVAIL_CRED_13 0x528A54593 594#define mmDMA1_QM_ARB_MST_AVAIL_CRED_14 0x528A58595 596#define mmDMA1_QM_ARB_MST_AVAIL_CRED_15 0x528A5C597 598#define mmDMA1_QM_ARB_MST_AVAIL_CRED_16 0x528A60599 600#define mmDMA1_QM_ARB_MST_AVAIL_CRED_17 0x528A64601 602#define mmDMA1_QM_ARB_MST_AVAIL_CRED_18 0x528A68603 604#define mmDMA1_QM_ARB_MST_AVAIL_CRED_19 0x528A6C605 606#define mmDMA1_QM_ARB_MST_AVAIL_CRED_20 0x528A70607 608#define mmDMA1_QM_ARB_MST_AVAIL_CRED_21 0x528A74609 610#define mmDMA1_QM_ARB_MST_AVAIL_CRED_22 0x528A78611 612#define mmDMA1_QM_ARB_MST_AVAIL_CRED_23 0x528A7C613 614#define mmDMA1_QM_ARB_MST_AVAIL_CRED_24 0x528A80615 616#define mmDMA1_QM_ARB_MST_AVAIL_CRED_25 0x528A84617 618#define mmDMA1_QM_ARB_MST_AVAIL_CRED_26 0x528A88619 620#define mmDMA1_QM_ARB_MST_AVAIL_CRED_27 0x528A8C621 622#define mmDMA1_QM_ARB_MST_AVAIL_CRED_28 0x528A90623 624#define mmDMA1_QM_ARB_MST_AVAIL_CRED_29 0x528A94625 626#define mmDMA1_QM_ARB_MST_AVAIL_CRED_30 0x528A98627 628#define mmDMA1_QM_ARB_MST_AVAIL_CRED_31 0x528A9C629 630#define mmDMA1_QM_ARB_MST_CRED_INC 0x528AA0631 632#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x528AA4633 634#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x528AA8635 636#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x528AAC637 638#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x528AB0639 640#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x528AB4641 642#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x528AB8643 644#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x528ABC645 646#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x528AC0647 648#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x528AC4649 650#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x528AC8651 652#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x528ACC653 654#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x528AD0655 656#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x528AD4657 658#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x528AD8659 660#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x528ADC661 662#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x528AE0663 664#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x528AE4665 666#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x528AE8667 668#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x528AEC669 670#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x528AF0671 672#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x528AF4673 674#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x528AF8675 676#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x528AFC677 678#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x528B00679 680#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x528B04681 682#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x528B08683 684#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x528B0C685 686#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x528B10687 688#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x528B14689 690#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x528B18691 692#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x528B1C693 694#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x528B20695 696#define mmDMA1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x528B28697 698#define mmDMA1_QM_ARB_MST_SLAVE_EN 0x528B2C699 700#define mmDMA1_QM_ARB_MST_QUIET_PER 0x528B34701 702#define mmDMA1_QM_ARB_SLV_CHOISE_WDT 0x528B38703 704#define mmDMA1_QM_ARB_SLV_ID 0x528B3C705 706#define mmDMA1_QM_ARB_MSG_MAX_INFLIGHT 0x528B44707 708#define mmDMA1_QM_ARB_MSG_AWUSER_31_11 0x528B48709 710#define mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP 0x528B4C711 712#define mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x528B50713 714#define mmDMA1_QM_ARB_BASE_LO 0x528B54715 716#define mmDMA1_QM_ARB_BASE_HI 0x528B58717 718#define mmDMA1_QM_ARB_STATE_STS 0x528B80719 720#define mmDMA1_QM_ARB_CHOISE_FULLNESS_STS 0x528B84721 722#define mmDMA1_QM_ARB_MSG_STS 0x528B88723 724#define mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD 0x528B8C725 726#define mmDMA1_QM_ARB_ERR_CAUSE 0x528B9C727 728#define mmDMA1_QM_ARB_ERR_MSG_EN 0x528BA0729 730#define mmDMA1_QM_ARB_ERR_STS_DRP 0x528BA8731 732#define mmDMA1_QM_ARB_MST_CRED_STS_0 0x528BB0733 734#define mmDMA1_QM_ARB_MST_CRED_STS_1 0x528BB4735 736#define mmDMA1_QM_ARB_MST_CRED_STS_2 0x528BB8737 738#define mmDMA1_QM_ARB_MST_CRED_STS_3 0x528BBC739 740#define mmDMA1_QM_ARB_MST_CRED_STS_4 0x528BC0741 742#define mmDMA1_QM_ARB_MST_CRED_STS_5 0x528BC4743 744#define mmDMA1_QM_ARB_MST_CRED_STS_6 0x528BC8745 746#define mmDMA1_QM_ARB_MST_CRED_STS_7 0x528BCC747 748#define mmDMA1_QM_ARB_MST_CRED_STS_8 0x528BD0749 750#define mmDMA1_QM_ARB_MST_CRED_STS_9 0x528BD4751 752#define mmDMA1_QM_ARB_MST_CRED_STS_10 0x528BD8753 754#define mmDMA1_QM_ARB_MST_CRED_STS_11 0x528BDC755 756#define mmDMA1_QM_ARB_MST_CRED_STS_12 0x528BE0757 758#define mmDMA1_QM_ARB_MST_CRED_STS_13 0x528BE4759 760#define mmDMA1_QM_ARB_MST_CRED_STS_14 0x528BE8761 762#define mmDMA1_QM_ARB_MST_CRED_STS_15 0x528BEC763 764#define mmDMA1_QM_ARB_MST_CRED_STS_16 0x528BF0765 766#define mmDMA1_QM_ARB_MST_CRED_STS_17 0x528BF4767 768#define mmDMA1_QM_ARB_MST_CRED_STS_18 0x528BF8769 770#define mmDMA1_QM_ARB_MST_CRED_STS_19 0x528BFC771 772#define mmDMA1_QM_ARB_MST_CRED_STS_20 0x528C00773 774#define mmDMA1_QM_ARB_MST_CRED_STS_21 0x528C04775 776#define mmDMA1_QM_ARB_MST_CRED_STS_22 0x528C08777 778#define mmDMA1_QM_ARB_MST_CRED_STS_23 0x528C0C779 780#define mmDMA1_QM_ARB_MST_CRED_STS_24 0x528C10781 782#define mmDMA1_QM_ARB_MST_CRED_STS_25 0x528C14783 784#define mmDMA1_QM_ARB_MST_CRED_STS_26 0x528C18785 786#define mmDMA1_QM_ARB_MST_CRED_STS_27 0x528C1C787 788#define mmDMA1_QM_ARB_MST_CRED_STS_28 0x528C20789 790#define mmDMA1_QM_ARB_MST_CRED_STS_29 0x528C24791 792#define mmDMA1_QM_ARB_MST_CRED_STS_30 0x528C28793 794#define mmDMA1_QM_ARB_MST_CRED_STS_31 0x528C2C795 796#define mmDMA1_QM_CGM_CFG 0x528C70797 798#define mmDMA1_QM_CGM_STS 0x528C74799 800#define mmDMA1_QM_CGM_CFG1 0x528C78801 802#define mmDMA1_QM_LOCAL_RANGE_BASE 0x528C80803 804#define mmDMA1_QM_LOCAL_RANGE_SIZE 0x528C84805 806#define mmDMA1_QM_CSMR_STRICT_PRIO_CFG 0x528C90807 808#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 0x528C94809 810#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 0x528C98811 812#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 0x528C9C813 814#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 0x528CA0815 816#define mmDMA1_QM_GLBL_AXCACHE 0x528CA4817 818#define mmDMA1_QM_IND_GW_APB_CFG 0x528CB0819 820#define mmDMA1_QM_IND_GW_APB_WDATA 0x528CB4821 822#define mmDMA1_QM_IND_GW_APB_RDATA 0x528CB8823 824#define mmDMA1_QM_IND_GW_APB_STATUS 0x528CBC825 826#define mmDMA1_QM_GLBL_ERR_ADDR_LO 0x528CD0827 828#define mmDMA1_QM_GLBL_ERR_ADDR_HI 0x528CD4829 830#define mmDMA1_QM_GLBL_ERR_WDATA 0x528CD8831 832#define mmDMA1_QM_GLBL_MEM_INIT_BUSY 0x528D00833 834#endif /* ASIC_REG_DMA1_QM_REGS_H_ */835