835 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA2_QM_REGS_H_14#define ASIC_REG_DMA2_QM_REGS_H_15 16/*17 *****************************************18 * DMA2_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmDMA2_QM_GLBL_CFG0 0x54800023 24#define mmDMA2_QM_GLBL_CFG1 0x54800425 26#define mmDMA2_QM_GLBL_PROT 0x54800827 28#define mmDMA2_QM_GLBL_ERR_CFG 0x54800C29 30#define mmDMA2_QM_GLBL_SECURE_PROPS_0 0x54801031 32#define mmDMA2_QM_GLBL_SECURE_PROPS_1 0x54801433 34#define mmDMA2_QM_GLBL_SECURE_PROPS_2 0x54801835 36#define mmDMA2_QM_GLBL_SECURE_PROPS_3 0x54801C37 38#define mmDMA2_QM_GLBL_SECURE_PROPS_4 0x54802039 40#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 0x54802441 42#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 0x54802843 44#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 0x54802C45 46#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 0x54803047 48#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 0x54803449 50#define mmDMA2_QM_GLBL_STS0 0x54803851 52#define mmDMA2_QM_GLBL_STS1_0 0x54804053 54#define mmDMA2_QM_GLBL_STS1_1 0x54804455 56#define mmDMA2_QM_GLBL_STS1_2 0x54804857 58#define mmDMA2_QM_GLBL_STS1_3 0x54804C59 60#define mmDMA2_QM_GLBL_STS1_4 0x54805061 62#define mmDMA2_QM_GLBL_MSG_EN_0 0x54805463 64#define mmDMA2_QM_GLBL_MSG_EN_1 0x54805865 66#define mmDMA2_QM_GLBL_MSG_EN_2 0x54805C67 68#define mmDMA2_QM_GLBL_MSG_EN_3 0x54806069 70#define mmDMA2_QM_GLBL_MSG_EN_4 0x54806871 72#define mmDMA2_QM_PQ_BASE_LO_0 0x54807073 74#define mmDMA2_QM_PQ_BASE_LO_1 0x54807475 76#define mmDMA2_QM_PQ_BASE_LO_2 0x54807877 78#define mmDMA2_QM_PQ_BASE_LO_3 0x54807C79 80#define mmDMA2_QM_PQ_BASE_HI_0 0x54808081 82#define mmDMA2_QM_PQ_BASE_HI_1 0x54808483 84#define mmDMA2_QM_PQ_BASE_HI_2 0x54808885 86#define mmDMA2_QM_PQ_BASE_HI_3 0x54808C87 88#define mmDMA2_QM_PQ_SIZE_0 0x54809089 90#define mmDMA2_QM_PQ_SIZE_1 0x54809491 92#define mmDMA2_QM_PQ_SIZE_2 0x54809893 94#define mmDMA2_QM_PQ_SIZE_3 0x54809C95 96#define mmDMA2_QM_PQ_PI_0 0x5480A097 98#define mmDMA2_QM_PQ_PI_1 0x5480A499 100#define mmDMA2_QM_PQ_PI_2 0x5480A8101 102#define mmDMA2_QM_PQ_PI_3 0x5480AC103 104#define mmDMA2_QM_PQ_CI_0 0x5480B0105 106#define mmDMA2_QM_PQ_CI_1 0x5480B4107 108#define mmDMA2_QM_PQ_CI_2 0x5480B8109 110#define mmDMA2_QM_PQ_CI_3 0x5480BC111 112#define mmDMA2_QM_PQ_CFG0_0 0x5480C0113 114#define mmDMA2_QM_PQ_CFG0_1 0x5480C4115 116#define mmDMA2_QM_PQ_CFG0_2 0x5480C8117 118#define mmDMA2_QM_PQ_CFG0_3 0x5480CC119 120#define mmDMA2_QM_PQ_CFG1_0 0x5480D0121 122#define mmDMA2_QM_PQ_CFG1_1 0x5480D4123 124#define mmDMA2_QM_PQ_CFG1_2 0x5480D8125 126#define mmDMA2_QM_PQ_CFG1_3 0x5480DC127 128#define mmDMA2_QM_PQ_ARUSER_31_11_0 0x5480E0129 130#define mmDMA2_QM_PQ_ARUSER_31_11_1 0x5480E4131 132#define mmDMA2_QM_PQ_ARUSER_31_11_2 0x5480E8133 134#define mmDMA2_QM_PQ_ARUSER_31_11_3 0x5480EC135 136#define mmDMA2_QM_PQ_STS0_0 0x5480F0137 138#define mmDMA2_QM_PQ_STS0_1 0x5480F4139 140#define mmDMA2_QM_PQ_STS0_2 0x5480F8141 142#define mmDMA2_QM_PQ_STS0_3 0x5480FC143 144#define mmDMA2_QM_PQ_STS1_0 0x548100145 146#define mmDMA2_QM_PQ_STS1_1 0x548104147 148#define mmDMA2_QM_PQ_STS1_2 0x548108149 150#define mmDMA2_QM_PQ_STS1_3 0x54810C151 152#define mmDMA2_QM_CQ_CFG0_0 0x548110153 154#define mmDMA2_QM_CQ_CFG0_1 0x548114155 156#define mmDMA2_QM_CQ_CFG0_2 0x548118157 158#define mmDMA2_QM_CQ_CFG0_3 0x54811C159 160#define mmDMA2_QM_CQ_CFG0_4 0x548120161 162#define mmDMA2_QM_CQ_CFG1_0 0x548124163 164#define mmDMA2_QM_CQ_CFG1_1 0x548128165 166#define mmDMA2_QM_CQ_CFG1_2 0x54812C167 168#define mmDMA2_QM_CQ_CFG1_3 0x548130169 170#define mmDMA2_QM_CQ_CFG1_4 0x548134171 172#define mmDMA2_QM_CQ_ARUSER_31_11_0 0x548138173 174#define mmDMA2_QM_CQ_ARUSER_31_11_1 0x54813C175 176#define mmDMA2_QM_CQ_ARUSER_31_11_2 0x548140177 178#define mmDMA2_QM_CQ_ARUSER_31_11_3 0x548144179 180#define mmDMA2_QM_CQ_ARUSER_31_11_4 0x548148181 182#define mmDMA2_QM_CQ_STS0_0 0x54814C183 184#define mmDMA2_QM_CQ_STS0_1 0x548150185 186#define mmDMA2_QM_CQ_STS0_2 0x548154187 188#define mmDMA2_QM_CQ_STS0_3 0x548158189 190#define mmDMA2_QM_CQ_STS0_4 0x54815C191 192#define mmDMA2_QM_CQ_STS1_0 0x548160193 194#define mmDMA2_QM_CQ_STS1_1 0x548164195 196#define mmDMA2_QM_CQ_STS1_2 0x548168197 198#define mmDMA2_QM_CQ_STS1_3 0x54816C199 200#define mmDMA2_QM_CQ_STS1_4 0x548170201 202#define mmDMA2_QM_CQ_PTR_LO_0 0x548174203 204#define mmDMA2_QM_CQ_PTR_HI_0 0x548178205 206#define mmDMA2_QM_CQ_TSIZE_0 0x54817C207 208#define mmDMA2_QM_CQ_CTL_0 0x548180209 210#define mmDMA2_QM_CQ_PTR_LO_1 0x548184211 212#define mmDMA2_QM_CQ_PTR_HI_1 0x548188213 214#define mmDMA2_QM_CQ_TSIZE_1 0x54818C215 216#define mmDMA2_QM_CQ_CTL_1 0x548190217 218#define mmDMA2_QM_CQ_PTR_LO_2 0x548194219 220#define mmDMA2_QM_CQ_PTR_HI_2 0x548198221 222#define mmDMA2_QM_CQ_TSIZE_2 0x54819C223 224#define mmDMA2_QM_CQ_CTL_2 0x5481A0225 226#define mmDMA2_QM_CQ_PTR_LO_3 0x5481A4227 228#define mmDMA2_QM_CQ_PTR_HI_3 0x5481A8229 230#define mmDMA2_QM_CQ_TSIZE_3 0x5481AC231 232#define mmDMA2_QM_CQ_CTL_3 0x5481B0233 234#define mmDMA2_QM_CQ_PTR_LO_4 0x5481B4235 236#define mmDMA2_QM_CQ_PTR_HI_4 0x5481B8237 238#define mmDMA2_QM_CQ_TSIZE_4 0x5481BC239 240#define mmDMA2_QM_CQ_CTL_4 0x5481C0241 242#define mmDMA2_QM_CQ_PTR_LO_STS_0 0x5481C4243 244#define mmDMA2_QM_CQ_PTR_LO_STS_1 0x5481C8245 246#define mmDMA2_QM_CQ_PTR_LO_STS_2 0x5481CC247 248#define mmDMA2_QM_CQ_PTR_LO_STS_3 0x5481D0249 250#define mmDMA2_QM_CQ_PTR_LO_STS_4 0x5481D4251 252#define mmDMA2_QM_CQ_PTR_HI_STS_0 0x5481D8253 254#define mmDMA2_QM_CQ_PTR_HI_STS_1 0x5481DC255 256#define mmDMA2_QM_CQ_PTR_HI_STS_2 0x5481E0257 258#define mmDMA2_QM_CQ_PTR_HI_STS_3 0x5481E4259 260#define mmDMA2_QM_CQ_PTR_HI_STS_4 0x5481E8261 262#define mmDMA2_QM_CQ_TSIZE_STS_0 0x5481EC263 264#define mmDMA2_QM_CQ_TSIZE_STS_1 0x5481F0265 266#define mmDMA2_QM_CQ_TSIZE_STS_2 0x5481F4267 268#define mmDMA2_QM_CQ_TSIZE_STS_3 0x5481F8269 270#define mmDMA2_QM_CQ_TSIZE_STS_4 0x5481FC271 272#define mmDMA2_QM_CQ_CTL_STS_0 0x548200273 274#define mmDMA2_QM_CQ_CTL_STS_1 0x548204275 276#define mmDMA2_QM_CQ_CTL_STS_2 0x548208277 278#define mmDMA2_QM_CQ_CTL_STS_3 0x54820C279 280#define mmDMA2_QM_CQ_CTL_STS_4 0x548210281 282#define mmDMA2_QM_CQ_IFIFO_CNT_0 0x548214283 284#define mmDMA2_QM_CQ_IFIFO_CNT_1 0x548218285 286#define mmDMA2_QM_CQ_IFIFO_CNT_2 0x54821C287 288#define mmDMA2_QM_CQ_IFIFO_CNT_3 0x548220289 290#define mmDMA2_QM_CQ_IFIFO_CNT_4 0x548224291 292#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 0x548228293 294#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 0x54822C295 296#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 0x548230297 298#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 0x548234299 300#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 0x548238301 302#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 0x54823C303 304#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 0x548240305 306#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 0x548244307 308#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 0x548248309 310#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 0x54824C311 312#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 0x548250313 314#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 0x548254315 316#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 0x548258317 318#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 0x54825C319 320#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 0x548260321 322#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 0x548264323 324#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 0x548268325 326#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 0x54826C327 328#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 0x548270329 330#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 0x548274331 332#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 0x548278333 334#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 0x54827C335 336#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 0x548280337 338#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 0x548284339 340#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 0x548288341 342#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 0x54828C343 344#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 0x548290345 346#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 0x548294347 348#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 0x548298349 350#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 0x54829C351 352#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 0x5482A0353 354#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 0x5482A4355 356#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 0x5482A8357 358#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 0x5482AC359 360#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 0x5482B0361 362#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 0x5482B4363 364#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 0x5482B8365 366#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 0x5482BC367 368#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 0x5482C0369 370#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 0x5482C4371 372#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 0x5482C8373 374#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 0x5482CC375 376#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 0x5482D0377 378#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 0x5482D4379 380#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 0x5482D8381 382#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5482E0383 384#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5482E4385 386#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5482E8387 388#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5482EC389 390#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5482F0391 392#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5482F4393 394#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5482F8395 396#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5482FC397 398#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x548300399 400#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x548304401 402#define mmDMA2_QM_CP_FENCE0_RDATA_0 0x548308403 404#define mmDMA2_QM_CP_FENCE0_RDATA_1 0x54830C405 406#define mmDMA2_QM_CP_FENCE0_RDATA_2 0x548310407 408#define mmDMA2_QM_CP_FENCE0_RDATA_3 0x548314409 410#define mmDMA2_QM_CP_FENCE0_RDATA_4 0x548318411 412#define mmDMA2_QM_CP_FENCE1_RDATA_0 0x54831C413 414#define mmDMA2_QM_CP_FENCE1_RDATA_1 0x548320415 416#define mmDMA2_QM_CP_FENCE1_RDATA_2 0x548324417 418#define mmDMA2_QM_CP_FENCE1_RDATA_3 0x548328419 420#define mmDMA2_QM_CP_FENCE1_RDATA_4 0x54832C421 422#define mmDMA2_QM_CP_FENCE2_RDATA_0 0x548330423 424#define mmDMA2_QM_CP_FENCE2_RDATA_1 0x548334425 426#define mmDMA2_QM_CP_FENCE2_RDATA_2 0x548338427 428#define mmDMA2_QM_CP_FENCE2_RDATA_3 0x54833C429 430#define mmDMA2_QM_CP_FENCE2_RDATA_4 0x548340431 432#define mmDMA2_QM_CP_FENCE3_RDATA_0 0x548344433 434#define mmDMA2_QM_CP_FENCE3_RDATA_1 0x548348435 436#define mmDMA2_QM_CP_FENCE3_RDATA_2 0x54834C437 438#define mmDMA2_QM_CP_FENCE3_RDATA_3 0x548350439 440#define mmDMA2_QM_CP_FENCE3_RDATA_4 0x548354441 442#define mmDMA2_QM_CP_FENCE0_CNT_0 0x548358443 444#define mmDMA2_QM_CP_FENCE0_CNT_1 0x54835C445 446#define mmDMA2_QM_CP_FENCE0_CNT_2 0x548360447 448#define mmDMA2_QM_CP_FENCE0_CNT_3 0x548364449 450#define mmDMA2_QM_CP_FENCE0_CNT_4 0x548368451 452#define mmDMA2_QM_CP_FENCE1_CNT_0 0x54836C453 454#define mmDMA2_QM_CP_FENCE1_CNT_1 0x548370455 456#define mmDMA2_QM_CP_FENCE1_CNT_2 0x548374457 458#define mmDMA2_QM_CP_FENCE1_CNT_3 0x548378459 460#define mmDMA2_QM_CP_FENCE1_CNT_4 0x54837C461 462#define mmDMA2_QM_CP_FENCE2_CNT_0 0x548380463 464#define mmDMA2_QM_CP_FENCE2_CNT_1 0x548384465 466#define mmDMA2_QM_CP_FENCE2_CNT_2 0x548388467 468#define mmDMA2_QM_CP_FENCE2_CNT_3 0x54838C469 470#define mmDMA2_QM_CP_FENCE2_CNT_4 0x548390471 472#define mmDMA2_QM_CP_FENCE3_CNT_0 0x548394473 474#define mmDMA2_QM_CP_FENCE3_CNT_1 0x548398475 476#define mmDMA2_QM_CP_FENCE3_CNT_2 0x54839C477 478#define mmDMA2_QM_CP_FENCE3_CNT_3 0x5483A0479 480#define mmDMA2_QM_CP_FENCE3_CNT_4 0x5483A4481 482#define mmDMA2_QM_CP_STS_0 0x5483A8483 484#define mmDMA2_QM_CP_STS_1 0x5483AC485 486#define mmDMA2_QM_CP_STS_2 0x5483B0487 488#define mmDMA2_QM_CP_STS_3 0x5483B4489 490#define mmDMA2_QM_CP_STS_4 0x5483B8491 492#define mmDMA2_QM_CP_CURRENT_INST_LO_0 0x5483BC493 494#define mmDMA2_QM_CP_CURRENT_INST_LO_1 0x5483C0495 496#define mmDMA2_QM_CP_CURRENT_INST_LO_2 0x5483C4497 498#define mmDMA2_QM_CP_CURRENT_INST_LO_3 0x5483C8499 500#define mmDMA2_QM_CP_CURRENT_INST_LO_4 0x5483CC501 502#define mmDMA2_QM_CP_CURRENT_INST_HI_0 0x5483D0503 504#define mmDMA2_QM_CP_CURRENT_INST_HI_1 0x5483D4505 506#define mmDMA2_QM_CP_CURRENT_INST_HI_2 0x5483D8507 508#define mmDMA2_QM_CP_CURRENT_INST_HI_3 0x5483DC509 510#define mmDMA2_QM_CP_CURRENT_INST_HI_4 0x5483E0511 512#define mmDMA2_QM_CP_BARRIER_CFG_0 0x5483F4513 514#define mmDMA2_QM_CP_BARRIER_CFG_1 0x5483F8515 516#define mmDMA2_QM_CP_BARRIER_CFG_2 0x5483FC517 518#define mmDMA2_QM_CP_BARRIER_CFG_3 0x548400519 520#define mmDMA2_QM_CP_BARRIER_CFG_4 0x548404521 522#define mmDMA2_QM_CP_DBG_0_0 0x548408523 524#define mmDMA2_QM_CP_DBG_0_1 0x54840C525 526#define mmDMA2_QM_CP_DBG_0_2 0x548410527 528#define mmDMA2_QM_CP_DBG_0_3 0x548414529 530#define mmDMA2_QM_CP_DBG_0_4 0x548418531 532#define mmDMA2_QM_CP_ARUSER_31_11_0 0x54841C533 534#define mmDMA2_QM_CP_ARUSER_31_11_1 0x548420535 536#define mmDMA2_QM_CP_ARUSER_31_11_2 0x548424537 538#define mmDMA2_QM_CP_ARUSER_31_11_3 0x548428539 540#define mmDMA2_QM_CP_ARUSER_31_11_4 0x54842C541 542#define mmDMA2_QM_CP_AWUSER_31_11_0 0x548430543 544#define mmDMA2_QM_CP_AWUSER_31_11_1 0x548434545 546#define mmDMA2_QM_CP_AWUSER_31_11_2 0x548438547 548#define mmDMA2_QM_CP_AWUSER_31_11_3 0x54843C549 550#define mmDMA2_QM_CP_AWUSER_31_11_4 0x548440551 552#define mmDMA2_QM_ARB_CFG_0 0x548A00553 554#define mmDMA2_QM_ARB_CHOISE_Q_PUSH 0x548A04555 556#define mmDMA2_QM_ARB_WRR_WEIGHT_0 0x548A08557 558#define mmDMA2_QM_ARB_WRR_WEIGHT_1 0x548A0C559 560#define mmDMA2_QM_ARB_WRR_WEIGHT_2 0x548A10561 562#define mmDMA2_QM_ARB_WRR_WEIGHT_3 0x548A14563 564#define mmDMA2_QM_ARB_CFG_1 0x548A18565 566#define mmDMA2_QM_ARB_MST_AVAIL_CRED_0 0x548A20567 568#define mmDMA2_QM_ARB_MST_AVAIL_CRED_1 0x548A24569 570#define mmDMA2_QM_ARB_MST_AVAIL_CRED_2 0x548A28571 572#define mmDMA2_QM_ARB_MST_AVAIL_CRED_3 0x548A2C573 574#define mmDMA2_QM_ARB_MST_AVAIL_CRED_4 0x548A30575 576#define mmDMA2_QM_ARB_MST_AVAIL_CRED_5 0x548A34577 578#define mmDMA2_QM_ARB_MST_AVAIL_CRED_6 0x548A38579 580#define mmDMA2_QM_ARB_MST_AVAIL_CRED_7 0x548A3C581 582#define mmDMA2_QM_ARB_MST_AVAIL_CRED_8 0x548A40583 584#define mmDMA2_QM_ARB_MST_AVAIL_CRED_9 0x548A44585 586#define mmDMA2_QM_ARB_MST_AVAIL_CRED_10 0x548A48587 588#define mmDMA2_QM_ARB_MST_AVAIL_CRED_11 0x548A4C589 590#define mmDMA2_QM_ARB_MST_AVAIL_CRED_12 0x548A50591 592#define mmDMA2_QM_ARB_MST_AVAIL_CRED_13 0x548A54593 594#define mmDMA2_QM_ARB_MST_AVAIL_CRED_14 0x548A58595 596#define mmDMA2_QM_ARB_MST_AVAIL_CRED_15 0x548A5C597 598#define mmDMA2_QM_ARB_MST_AVAIL_CRED_16 0x548A60599 600#define mmDMA2_QM_ARB_MST_AVAIL_CRED_17 0x548A64601 602#define mmDMA2_QM_ARB_MST_AVAIL_CRED_18 0x548A68603 604#define mmDMA2_QM_ARB_MST_AVAIL_CRED_19 0x548A6C605 606#define mmDMA2_QM_ARB_MST_AVAIL_CRED_20 0x548A70607 608#define mmDMA2_QM_ARB_MST_AVAIL_CRED_21 0x548A74609 610#define mmDMA2_QM_ARB_MST_AVAIL_CRED_22 0x548A78611 612#define mmDMA2_QM_ARB_MST_AVAIL_CRED_23 0x548A7C613 614#define mmDMA2_QM_ARB_MST_AVAIL_CRED_24 0x548A80615 616#define mmDMA2_QM_ARB_MST_AVAIL_CRED_25 0x548A84617 618#define mmDMA2_QM_ARB_MST_AVAIL_CRED_26 0x548A88619 620#define mmDMA2_QM_ARB_MST_AVAIL_CRED_27 0x548A8C621 622#define mmDMA2_QM_ARB_MST_AVAIL_CRED_28 0x548A90623 624#define mmDMA2_QM_ARB_MST_AVAIL_CRED_29 0x548A94625 626#define mmDMA2_QM_ARB_MST_AVAIL_CRED_30 0x548A98627 628#define mmDMA2_QM_ARB_MST_AVAIL_CRED_31 0x548A9C629 630#define mmDMA2_QM_ARB_MST_CRED_INC 0x548AA0631 632#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x548AA4633 634#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x548AA8635 636#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x548AAC637 638#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x548AB0639 640#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x548AB4641 642#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x548AB8643 644#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x548ABC645 646#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x548AC0647 648#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x548AC4649 650#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x548AC8651 652#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x548ACC653 654#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x548AD0655 656#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x548AD4657 658#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x548AD8659 660#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x548ADC661 662#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x548AE0663 664#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x548AE4665 666#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x548AE8667 668#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x548AEC669 670#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x548AF0671 672#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x548AF4673 674#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x548AF8675 676#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x548AFC677 678#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x548B00679 680#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x548B04681 682#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x548B08683 684#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x548B0C685 686#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x548B10687 688#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x548B14689 690#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x548B18691 692#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x548B1C693 694#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x548B20695 696#define mmDMA2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x548B28697 698#define mmDMA2_QM_ARB_MST_SLAVE_EN 0x548B2C699 700#define mmDMA2_QM_ARB_MST_QUIET_PER 0x548B34701 702#define mmDMA2_QM_ARB_SLV_CHOISE_WDT 0x548B38703 704#define mmDMA2_QM_ARB_SLV_ID 0x548B3C705 706#define mmDMA2_QM_ARB_MSG_MAX_INFLIGHT 0x548B44707 708#define mmDMA2_QM_ARB_MSG_AWUSER_31_11 0x548B48709 710#define mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP 0x548B4C711 712#define mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x548B50713 714#define mmDMA2_QM_ARB_BASE_LO 0x548B54715 716#define mmDMA2_QM_ARB_BASE_HI 0x548B58717 718#define mmDMA2_QM_ARB_STATE_STS 0x548B80719 720#define mmDMA2_QM_ARB_CHOISE_FULLNESS_STS 0x548B84721 722#define mmDMA2_QM_ARB_MSG_STS 0x548B88723 724#define mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD 0x548B8C725 726#define mmDMA2_QM_ARB_ERR_CAUSE 0x548B9C727 728#define mmDMA2_QM_ARB_ERR_MSG_EN 0x548BA0729 730#define mmDMA2_QM_ARB_ERR_STS_DRP 0x548BA8731 732#define mmDMA2_QM_ARB_MST_CRED_STS_0 0x548BB0733 734#define mmDMA2_QM_ARB_MST_CRED_STS_1 0x548BB4735 736#define mmDMA2_QM_ARB_MST_CRED_STS_2 0x548BB8737 738#define mmDMA2_QM_ARB_MST_CRED_STS_3 0x548BBC739 740#define mmDMA2_QM_ARB_MST_CRED_STS_4 0x548BC0741 742#define mmDMA2_QM_ARB_MST_CRED_STS_5 0x548BC4743 744#define mmDMA2_QM_ARB_MST_CRED_STS_6 0x548BC8745 746#define mmDMA2_QM_ARB_MST_CRED_STS_7 0x548BCC747 748#define mmDMA2_QM_ARB_MST_CRED_STS_8 0x548BD0749 750#define mmDMA2_QM_ARB_MST_CRED_STS_9 0x548BD4751 752#define mmDMA2_QM_ARB_MST_CRED_STS_10 0x548BD8753 754#define mmDMA2_QM_ARB_MST_CRED_STS_11 0x548BDC755 756#define mmDMA2_QM_ARB_MST_CRED_STS_12 0x548BE0757 758#define mmDMA2_QM_ARB_MST_CRED_STS_13 0x548BE4759 760#define mmDMA2_QM_ARB_MST_CRED_STS_14 0x548BE8761 762#define mmDMA2_QM_ARB_MST_CRED_STS_15 0x548BEC763 764#define mmDMA2_QM_ARB_MST_CRED_STS_16 0x548BF0765 766#define mmDMA2_QM_ARB_MST_CRED_STS_17 0x548BF4767 768#define mmDMA2_QM_ARB_MST_CRED_STS_18 0x548BF8769 770#define mmDMA2_QM_ARB_MST_CRED_STS_19 0x548BFC771 772#define mmDMA2_QM_ARB_MST_CRED_STS_20 0x548C00773 774#define mmDMA2_QM_ARB_MST_CRED_STS_21 0x548C04775 776#define mmDMA2_QM_ARB_MST_CRED_STS_22 0x548C08777 778#define mmDMA2_QM_ARB_MST_CRED_STS_23 0x548C0C779 780#define mmDMA2_QM_ARB_MST_CRED_STS_24 0x548C10781 782#define mmDMA2_QM_ARB_MST_CRED_STS_25 0x548C14783 784#define mmDMA2_QM_ARB_MST_CRED_STS_26 0x548C18785 786#define mmDMA2_QM_ARB_MST_CRED_STS_27 0x548C1C787 788#define mmDMA2_QM_ARB_MST_CRED_STS_28 0x548C20789 790#define mmDMA2_QM_ARB_MST_CRED_STS_29 0x548C24791 792#define mmDMA2_QM_ARB_MST_CRED_STS_30 0x548C28793 794#define mmDMA2_QM_ARB_MST_CRED_STS_31 0x548C2C795 796#define mmDMA2_QM_CGM_CFG 0x548C70797 798#define mmDMA2_QM_CGM_STS 0x548C74799 800#define mmDMA2_QM_CGM_CFG1 0x548C78801 802#define mmDMA2_QM_LOCAL_RANGE_BASE 0x548C80803 804#define mmDMA2_QM_LOCAL_RANGE_SIZE 0x548C84805 806#define mmDMA2_QM_CSMR_STRICT_PRIO_CFG 0x548C90807 808#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 0x548C94809 810#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 0x548C98811 812#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 0x548C9C813 814#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 0x548CA0815 816#define mmDMA2_QM_GLBL_AXCACHE 0x548CA4817 818#define mmDMA2_QM_IND_GW_APB_CFG 0x548CB0819 820#define mmDMA2_QM_IND_GW_APB_WDATA 0x548CB4821 822#define mmDMA2_QM_IND_GW_APB_RDATA 0x548CB8823 824#define mmDMA2_QM_IND_GW_APB_STATUS 0x548CBC825 826#define mmDMA2_QM_GLBL_ERR_ADDR_LO 0x548CD0827 828#define mmDMA2_QM_GLBL_ERR_ADDR_HI 0x548CD4829 830#define mmDMA2_QM_GLBL_ERR_WDATA 0x548CD8831 832#define mmDMA2_QM_GLBL_MEM_INIT_BUSY 0x548D00833 834#endif /* ASIC_REG_DMA2_QM_REGS_H_ */835