835 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA3_QM_REGS_H_14#define ASIC_REG_DMA3_QM_REGS_H_15 16/*17 *****************************************18 * DMA3_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmDMA3_QM_GLBL_CFG0 0x56800023 24#define mmDMA3_QM_GLBL_CFG1 0x56800425 26#define mmDMA3_QM_GLBL_PROT 0x56800827 28#define mmDMA3_QM_GLBL_ERR_CFG 0x56800C29 30#define mmDMA3_QM_GLBL_SECURE_PROPS_0 0x56801031 32#define mmDMA3_QM_GLBL_SECURE_PROPS_1 0x56801433 34#define mmDMA3_QM_GLBL_SECURE_PROPS_2 0x56801835 36#define mmDMA3_QM_GLBL_SECURE_PROPS_3 0x56801C37 38#define mmDMA3_QM_GLBL_SECURE_PROPS_4 0x56802039 40#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 0x56802441 42#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 0x56802843 44#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 0x56802C45 46#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 0x56803047 48#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 0x56803449 50#define mmDMA3_QM_GLBL_STS0 0x56803851 52#define mmDMA3_QM_GLBL_STS1_0 0x56804053 54#define mmDMA3_QM_GLBL_STS1_1 0x56804455 56#define mmDMA3_QM_GLBL_STS1_2 0x56804857 58#define mmDMA3_QM_GLBL_STS1_3 0x56804C59 60#define mmDMA3_QM_GLBL_STS1_4 0x56805061 62#define mmDMA3_QM_GLBL_MSG_EN_0 0x56805463 64#define mmDMA3_QM_GLBL_MSG_EN_1 0x56805865 66#define mmDMA3_QM_GLBL_MSG_EN_2 0x56805C67 68#define mmDMA3_QM_GLBL_MSG_EN_3 0x56806069 70#define mmDMA3_QM_GLBL_MSG_EN_4 0x56806871 72#define mmDMA3_QM_PQ_BASE_LO_0 0x56807073 74#define mmDMA3_QM_PQ_BASE_LO_1 0x56807475 76#define mmDMA3_QM_PQ_BASE_LO_2 0x56807877 78#define mmDMA3_QM_PQ_BASE_LO_3 0x56807C79 80#define mmDMA3_QM_PQ_BASE_HI_0 0x56808081 82#define mmDMA3_QM_PQ_BASE_HI_1 0x56808483 84#define mmDMA3_QM_PQ_BASE_HI_2 0x56808885 86#define mmDMA3_QM_PQ_BASE_HI_3 0x56808C87 88#define mmDMA3_QM_PQ_SIZE_0 0x56809089 90#define mmDMA3_QM_PQ_SIZE_1 0x56809491 92#define mmDMA3_QM_PQ_SIZE_2 0x56809893 94#define mmDMA3_QM_PQ_SIZE_3 0x56809C95 96#define mmDMA3_QM_PQ_PI_0 0x5680A097 98#define mmDMA3_QM_PQ_PI_1 0x5680A499 100#define mmDMA3_QM_PQ_PI_2 0x5680A8101 102#define mmDMA3_QM_PQ_PI_3 0x5680AC103 104#define mmDMA3_QM_PQ_CI_0 0x5680B0105 106#define mmDMA3_QM_PQ_CI_1 0x5680B4107 108#define mmDMA3_QM_PQ_CI_2 0x5680B8109 110#define mmDMA3_QM_PQ_CI_3 0x5680BC111 112#define mmDMA3_QM_PQ_CFG0_0 0x5680C0113 114#define mmDMA3_QM_PQ_CFG0_1 0x5680C4115 116#define mmDMA3_QM_PQ_CFG0_2 0x5680C8117 118#define mmDMA3_QM_PQ_CFG0_3 0x5680CC119 120#define mmDMA3_QM_PQ_CFG1_0 0x5680D0121 122#define mmDMA3_QM_PQ_CFG1_1 0x5680D4123 124#define mmDMA3_QM_PQ_CFG1_2 0x5680D8125 126#define mmDMA3_QM_PQ_CFG1_3 0x5680DC127 128#define mmDMA3_QM_PQ_ARUSER_31_11_0 0x5680E0129 130#define mmDMA3_QM_PQ_ARUSER_31_11_1 0x5680E4131 132#define mmDMA3_QM_PQ_ARUSER_31_11_2 0x5680E8133 134#define mmDMA3_QM_PQ_ARUSER_31_11_3 0x5680EC135 136#define mmDMA3_QM_PQ_STS0_0 0x5680F0137 138#define mmDMA3_QM_PQ_STS0_1 0x5680F4139 140#define mmDMA3_QM_PQ_STS0_2 0x5680F8141 142#define mmDMA3_QM_PQ_STS0_3 0x5680FC143 144#define mmDMA3_QM_PQ_STS1_0 0x568100145 146#define mmDMA3_QM_PQ_STS1_1 0x568104147 148#define mmDMA3_QM_PQ_STS1_2 0x568108149 150#define mmDMA3_QM_PQ_STS1_3 0x56810C151 152#define mmDMA3_QM_CQ_CFG0_0 0x568110153 154#define mmDMA3_QM_CQ_CFG0_1 0x568114155 156#define mmDMA3_QM_CQ_CFG0_2 0x568118157 158#define mmDMA3_QM_CQ_CFG0_3 0x56811C159 160#define mmDMA3_QM_CQ_CFG0_4 0x568120161 162#define mmDMA3_QM_CQ_CFG1_0 0x568124163 164#define mmDMA3_QM_CQ_CFG1_1 0x568128165 166#define mmDMA3_QM_CQ_CFG1_2 0x56812C167 168#define mmDMA3_QM_CQ_CFG1_3 0x568130169 170#define mmDMA3_QM_CQ_CFG1_4 0x568134171 172#define mmDMA3_QM_CQ_ARUSER_31_11_0 0x568138173 174#define mmDMA3_QM_CQ_ARUSER_31_11_1 0x56813C175 176#define mmDMA3_QM_CQ_ARUSER_31_11_2 0x568140177 178#define mmDMA3_QM_CQ_ARUSER_31_11_3 0x568144179 180#define mmDMA3_QM_CQ_ARUSER_31_11_4 0x568148181 182#define mmDMA3_QM_CQ_STS0_0 0x56814C183 184#define mmDMA3_QM_CQ_STS0_1 0x568150185 186#define mmDMA3_QM_CQ_STS0_2 0x568154187 188#define mmDMA3_QM_CQ_STS0_3 0x568158189 190#define mmDMA3_QM_CQ_STS0_4 0x56815C191 192#define mmDMA3_QM_CQ_STS1_0 0x568160193 194#define mmDMA3_QM_CQ_STS1_1 0x568164195 196#define mmDMA3_QM_CQ_STS1_2 0x568168197 198#define mmDMA3_QM_CQ_STS1_3 0x56816C199 200#define mmDMA3_QM_CQ_STS1_4 0x568170201 202#define mmDMA3_QM_CQ_PTR_LO_0 0x568174203 204#define mmDMA3_QM_CQ_PTR_HI_0 0x568178205 206#define mmDMA3_QM_CQ_TSIZE_0 0x56817C207 208#define mmDMA3_QM_CQ_CTL_0 0x568180209 210#define mmDMA3_QM_CQ_PTR_LO_1 0x568184211 212#define mmDMA3_QM_CQ_PTR_HI_1 0x568188213 214#define mmDMA3_QM_CQ_TSIZE_1 0x56818C215 216#define mmDMA3_QM_CQ_CTL_1 0x568190217 218#define mmDMA3_QM_CQ_PTR_LO_2 0x568194219 220#define mmDMA3_QM_CQ_PTR_HI_2 0x568198221 222#define mmDMA3_QM_CQ_TSIZE_2 0x56819C223 224#define mmDMA3_QM_CQ_CTL_2 0x5681A0225 226#define mmDMA3_QM_CQ_PTR_LO_3 0x5681A4227 228#define mmDMA3_QM_CQ_PTR_HI_3 0x5681A8229 230#define mmDMA3_QM_CQ_TSIZE_3 0x5681AC231 232#define mmDMA3_QM_CQ_CTL_3 0x5681B0233 234#define mmDMA3_QM_CQ_PTR_LO_4 0x5681B4235 236#define mmDMA3_QM_CQ_PTR_HI_4 0x5681B8237 238#define mmDMA3_QM_CQ_TSIZE_4 0x5681BC239 240#define mmDMA3_QM_CQ_CTL_4 0x5681C0241 242#define mmDMA3_QM_CQ_PTR_LO_STS_0 0x5681C4243 244#define mmDMA3_QM_CQ_PTR_LO_STS_1 0x5681C8245 246#define mmDMA3_QM_CQ_PTR_LO_STS_2 0x5681CC247 248#define mmDMA3_QM_CQ_PTR_LO_STS_3 0x5681D0249 250#define mmDMA3_QM_CQ_PTR_LO_STS_4 0x5681D4251 252#define mmDMA3_QM_CQ_PTR_HI_STS_0 0x5681D8253 254#define mmDMA3_QM_CQ_PTR_HI_STS_1 0x5681DC255 256#define mmDMA3_QM_CQ_PTR_HI_STS_2 0x5681E0257 258#define mmDMA3_QM_CQ_PTR_HI_STS_3 0x5681E4259 260#define mmDMA3_QM_CQ_PTR_HI_STS_4 0x5681E8261 262#define mmDMA3_QM_CQ_TSIZE_STS_0 0x5681EC263 264#define mmDMA3_QM_CQ_TSIZE_STS_1 0x5681F0265 266#define mmDMA3_QM_CQ_TSIZE_STS_2 0x5681F4267 268#define mmDMA3_QM_CQ_TSIZE_STS_3 0x5681F8269 270#define mmDMA3_QM_CQ_TSIZE_STS_4 0x5681FC271 272#define mmDMA3_QM_CQ_CTL_STS_0 0x568200273 274#define mmDMA3_QM_CQ_CTL_STS_1 0x568204275 276#define mmDMA3_QM_CQ_CTL_STS_2 0x568208277 278#define mmDMA3_QM_CQ_CTL_STS_3 0x56820C279 280#define mmDMA3_QM_CQ_CTL_STS_4 0x568210281 282#define mmDMA3_QM_CQ_IFIFO_CNT_0 0x568214283 284#define mmDMA3_QM_CQ_IFIFO_CNT_1 0x568218285 286#define mmDMA3_QM_CQ_IFIFO_CNT_2 0x56821C287 288#define mmDMA3_QM_CQ_IFIFO_CNT_3 0x568220289 290#define mmDMA3_QM_CQ_IFIFO_CNT_4 0x568224291 292#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 0x568228293 294#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 0x56822C295 296#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 0x568230297 298#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 0x568234299 300#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 0x568238301 302#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 0x56823C303 304#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 0x568240305 306#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 0x568244307 308#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 0x568248309 310#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 0x56824C311 312#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 0x568250313 314#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 0x568254315 316#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 0x568258317 318#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 0x56825C319 320#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 0x568260321 322#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 0x568264323 324#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 0x568268325 326#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 0x56826C327 328#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 0x568270329 330#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 0x568274331 332#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 0x568278333 334#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 0x56827C335 336#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 0x568280337 338#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 0x568284339 340#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 0x568288341 342#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 0x56828C343 344#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 0x568290345 346#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 0x568294347 348#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 0x568298349 350#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 0x56829C351 352#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 0x5682A0353 354#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 0x5682A4355 356#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 0x5682A8357 358#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 0x5682AC359 360#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 0x5682B0361 362#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 0x5682B4363 364#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 0x5682B8365 366#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 0x5682BC367 368#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 0x5682C0369 370#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 0x5682C4371 372#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 0x5682C8373 374#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 0x5682CC375 376#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 0x5682D0377 378#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 0x5682D4379 380#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 0x5682D8381 382#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5682E0383 384#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5682E4385 386#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5682E8387 388#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5682EC389 390#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5682F0391 392#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5682F4393 394#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5682F8395 396#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5682FC397 398#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x568300399 400#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x568304401 402#define mmDMA3_QM_CP_FENCE0_RDATA_0 0x568308403 404#define mmDMA3_QM_CP_FENCE0_RDATA_1 0x56830C405 406#define mmDMA3_QM_CP_FENCE0_RDATA_2 0x568310407 408#define mmDMA3_QM_CP_FENCE0_RDATA_3 0x568314409 410#define mmDMA3_QM_CP_FENCE0_RDATA_4 0x568318411 412#define mmDMA3_QM_CP_FENCE1_RDATA_0 0x56831C413 414#define mmDMA3_QM_CP_FENCE1_RDATA_1 0x568320415 416#define mmDMA3_QM_CP_FENCE1_RDATA_2 0x568324417 418#define mmDMA3_QM_CP_FENCE1_RDATA_3 0x568328419 420#define mmDMA3_QM_CP_FENCE1_RDATA_4 0x56832C421 422#define mmDMA3_QM_CP_FENCE2_RDATA_0 0x568330423 424#define mmDMA3_QM_CP_FENCE2_RDATA_1 0x568334425 426#define mmDMA3_QM_CP_FENCE2_RDATA_2 0x568338427 428#define mmDMA3_QM_CP_FENCE2_RDATA_3 0x56833C429 430#define mmDMA3_QM_CP_FENCE2_RDATA_4 0x568340431 432#define mmDMA3_QM_CP_FENCE3_RDATA_0 0x568344433 434#define mmDMA3_QM_CP_FENCE3_RDATA_1 0x568348435 436#define mmDMA3_QM_CP_FENCE3_RDATA_2 0x56834C437 438#define mmDMA3_QM_CP_FENCE3_RDATA_3 0x568350439 440#define mmDMA3_QM_CP_FENCE3_RDATA_4 0x568354441 442#define mmDMA3_QM_CP_FENCE0_CNT_0 0x568358443 444#define mmDMA3_QM_CP_FENCE0_CNT_1 0x56835C445 446#define mmDMA3_QM_CP_FENCE0_CNT_2 0x568360447 448#define mmDMA3_QM_CP_FENCE0_CNT_3 0x568364449 450#define mmDMA3_QM_CP_FENCE0_CNT_4 0x568368451 452#define mmDMA3_QM_CP_FENCE1_CNT_0 0x56836C453 454#define mmDMA3_QM_CP_FENCE1_CNT_1 0x568370455 456#define mmDMA3_QM_CP_FENCE1_CNT_2 0x568374457 458#define mmDMA3_QM_CP_FENCE1_CNT_3 0x568378459 460#define mmDMA3_QM_CP_FENCE1_CNT_4 0x56837C461 462#define mmDMA3_QM_CP_FENCE2_CNT_0 0x568380463 464#define mmDMA3_QM_CP_FENCE2_CNT_1 0x568384465 466#define mmDMA3_QM_CP_FENCE2_CNT_2 0x568388467 468#define mmDMA3_QM_CP_FENCE2_CNT_3 0x56838C469 470#define mmDMA3_QM_CP_FENCE2_CNT_4 0x568390471 472#define mmDMA3_QM_CP_FENCE3_CNT_0 0x568394473 474#define mmDMA3_QM_CP_FENCE3_CNT_1 0x568398475 476#define mmDMA3_QM_CP_FENCE3_CNT_2 0x56839C477 478#define mmDMA3_QM_CP_FENCE3_CNT_3 0x5683A0479 480#define mmDMA3_QM_CP_FENCE3_CNT_4 0x5683A4481 482#define mmDMA3_QM_CP_STS_0 0x5683A8483 484#define mmDMA3_QM_CP_STS_1 0x5683AC485 486#define mmDMA3_QM_CP_STS_2 0x5683B0487 488#define mmDMA3_QM_CP_STS_3 0x5683B4489 490#define mmDMA3_QM_CP_STS_4 0x5683B8491 492#define mmDMA3_QM_CP_CURRENT_INST_LO_0 0x5683BC493 494#define mmDMA3_QM_CP_CURRENT_INST_LO_1 0x5683C0495 496#define mmDMA3_QM_CP_CURRENT_INST_LO_2 0x5683C4497 498#define mmDMA3_QM_CP_CURRENT_INST_LO_3 0x5683C8499 500#define mmDMA3_QM_CP_CURRENT_INST_LO_4 0x5683CC501 502#define mmDMA3_QM_CP_CURRENT_INST_HI_0 0x5683D0503 504#define mmDMA3_QM_CP_CURRENT_INST_HI_1 0x5683D4505 506#define mmDMA3_QM_CP_CURRENT_INST_HI_2 0x5683D8507 508#define mmDMA3_QM_CP_CURRENT_INST_HI_3 0x5683DC509 510#define mmDMA3_QM_CP_CURRENT_INST_HI_4 0x5683E0511 512#define mmDMA3_QM_CP_BARRIER_CFG_0 0x5683F4513 514#define mmDMA3_QM_CP_BARRIER_CFG_1 0x5683F8515 516#define mmDMA3_QM_CP_BARRIER_CFG_2 0x5683FC517 518#define mmDMA3_QM_CP_BARRIER_CFG_3 0x568400519 520#define mmDMA3_QM_CP_BARRIER_CFG_4 0x568404521 522#define mmDMA3_QM_CP_DBG_0_0 0x568408523 524#define mmDMA3_QM_CP_DBG_0_1 0x56840C525 526#define mmDMA3_QM_CP_DBG_0_2 0x568410527 528#define mmDMA3_QM_CP_DBG_0_3 0x568414529 530#define mmDMA3_QM_CP_DBG_0_4 0x568418531 532#define mmDMA3_QM_CP_ARUSER_31_11_0 0x56841C533 534#define mmDMA3_QM_CP_ARUSER_31_11_1 0x568420535 536#define mmDMA3_QM_CP_ARUSER_31_11_2 0x568424537 538#define mmDMA3_QM_CP_ARUSER_31_11_3 0x568428539 540#define mmDMA3_QM_CP_ARUSER_31_11_4 0x56842C541 542#define mmDMA3_QM_CP_AWUSER_31_11_0 0x568430543 544#define mmDMA3_QM_CP_AWUSER_31_11_1 0x568434545 546#define mmDMA3_QM_CP_AWUSER_31_11_2 0x568438547 548#define mmDMA3_QM_CP_AWUSER_31_11_3 0x56843C549 550#define mmDMA3_QM_CP_AWUSER_31_11_4 0x568440551 552#define mmDMA3_QM_ARB_CFG_0 0x568A00553 554#define mmDMA3_QM_ARB_CHOISE_Q_PUSH 0x568A04555 556#define mmDMA3_QM_ARB_WRR_WEIGHT_0 0x568A08557 558#define mmDMA3_QM_ARB_WRR_WEIGHT_1 0x568A0C559 560#define mmDMA3_QM_ARB_WRR_WEIGHT_2 0x568A10561 562#define mmDMA3_QM_ARB_WRR_WEIGHT_3 0x568A14563 564#define mmDMA3_QM_ARB_CFG_1 0x568A18565 566#define mmDMA3_QM_ARB_MST_AVAIL_CRED_0 0x568A20567 568#define mmDMA3_QM_ARB_MST_AVAIL_CRED_1 0x568A24569 570#define mmDMA3_QM_ARB_MST_AVAIL_CRED_2 0x568A28571 572#define mmDMA3_QM_ARB_MST_AVAIL_CRED_3 0x568A2C573 574#define mmDMA3_QM_ARB_MST_AVAIL_CRED_4 0x568A30575 576#define mmDMA3_QM_ARB_MST_AVAIL_CRED_5 0x568A34577 578#define mmDMA3_QM_ARB_MST_AVAIL_CRED_6 0x568A38579 580#define mmDMA3_QM_ARB_MST_AVAIL_CRED_7 0x568A3C581 582#define mmDMA3_QM_ARB_MST_AVAIL_CRED_8 0x568A40583 584#define mmDMA3_QM_ARB_MST_AVAIL_CRED_9 0x568A44585 586#define mmDMA3_QM_ARB_MST_AVAIL_CRED_10 0x568A48587 588#define mmDMA3_QM_ARB_MST_AVAIL_CRED_11 0x568A4C589 590#define mmDMA3_QM_ARB_MST_AVAIL_CRED_12 0x568A50591 592#define mmDMA3_QM_ARB_MST_AVAIL_CRED_13 0x568A54593 594#define mmDMA3_QM_ARB_MST_AVAIL_CRED_14 0x568A58595 596#define mmDMA3_QM_ARB_MST_AVAIL_CRED_15 0x568A5C597 598#define mmDMA3_QM_ARB_MST_AVAIL_CRED_16 0x568A60599 600#define mmDMA3_QM_ARB_MST_AVAIL_CRED_17 0x568A64601 602#define mmDMA3_QM_ARB_MST_AVAIL_CRED_18 0x568A68603 604#define mmDMA3_QM_ARB_MST_AVAIL_CRED_19 0x568A6C605 606#define mmDMA3_QM_ARB_MST_AVAIL_CRED_20 0x568A70607 608#define mmDMA3_QM_ARB_MST_AVAIL_CRED_21 0x568A74609 610#define mmDMA3_QM_ARB_MST_AVAIL_CRED_22 0x568A78611 612#define mmDMA3_QM_ARB_MST_AVAIL_CRED_23 0x568A7C613 614#define mmDMA3_QM_ARB_MST_AVAIL_CRED_24 0x568A80615 616#define mmDMA3_QM_ARB_MST_AVAIL_CRED_25 0x568A84617 618#define mmDMA3_QM_ARB_MST_AVAIL_CRED_26 0x568A88619 620#define mmDMA3_QM_ARB_MST_AVAIL_CRED_27 0x568A8C621 622#define mmDMA3_QM_ARB_MST_AVAIL_CRED_28 0x568A90623 624#define mmDMA3_QM_ARB_MST_AVAIL_CRED_29 0x568A94625 626#define mmDMA3_QM_ARB_MST_AVAIL_CRED_30 0x568A98627 628#define mmDMA3_QM_ARB_MST_AVAIL_CRED_31 0x568A9C629 630#define mmDMA3_QM_ARB_MST_CRED_INC 0x568AA0631 632#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x568AA4633 634#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x568AA8635 636#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x568AAC637 638#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x568AB0639 640#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x568AB4641 642#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x568AB8643 644#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x568ABC645 646#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x568AC0647 648#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x568AC4649 650#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x568AC8651 652#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x568ACC653 654#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x568AD0655 656#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x568AD4657 658#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x568AD8659 660#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x568ADC661 662#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x568AE0663 664#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x568AE4665 666#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x568AE8667 668#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x568AEC669 670#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x568AF0671 672#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x568AF4673 674#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x568AF8675 676#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x568AFC677 678#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x568B00679 680#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x568B04681 682#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x568B08683 684#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x568B0C685 686#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x568B10687 688#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x568B14689 690#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x568B18691 692#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x568B1C693 694#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x568B20695 696#define mmDMA3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x568B28697 698#define mmDMA3_QM_ARB_MST_SLAVE_EN 0x568B2C699 700#define mmDMA3_QM_ARB_MST_QUIET_PER 0x568B34701 702#define mmDMA3_QM_ARB_SLV_CHOISE_WDT 0x568B38703 704#define mmDMA3_QM_ARB_SLV_ID 0x568B3C705 706#define mmDMA3_QM_ARB_MSG_MAX_INFLIGHT 0x568B44707 708#define mmDMA3_QM_ARB_MSG_AWUSER_31_11 0x568B48709 710#define mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP 0x568B4C711 712#define mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x568B50713 714#define mmDMA3_QM_ARB_BASE_LO 0x568B54715 716#define mmDMA3_QM_ARB_BASE_HI 0x568B58717 718#define mmDMA3_QM_ARB_STATE_STS 0x568B80719 720#define mmDMA3_QM_ARB_CHOISE_FULLNESS_STS 0x568B84721 722#define mmDMA3_QM_ARB_MSG_STS 0x568B88723 724#define mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD 0x568B8C725 726#define mmDMA3_QM_ARB_ERR_CAUSE 0x568B9C727 728#define mmDMA3_QM_ARB_ERR_MSG_EN 0x568BA0729 730#define mmDMA3_QM_ARB_ERR_STS_DRP 0x568BA8731 732#define mmDMA3_QM_ARB_MST_CRED_STS_0 0x568BB0733 734#define mmDMA3_QM_ARB_MST_CRED_STS_1 0x568BB4735 736#define mmDMA3_QM_ARB_MST_CRED_STS_2 0x568BB8737 738#define mmDMA3_QM_ARB_MST_CRED_STS_3 0x568BBC739 740#define mmDMA3_QM_ARB_MST_CRED_STS_4 0x568BC0741 742#define mmDMA3_QM_ARB_MST_CRED_STS_5 0x568BC4743 744#define mmDMA3_QM_ARB_MST_CRED_STS_6 0x568BC8745 746#define mmDMA3_QM_ARB_MST_CRED_STS_7 0x568BCC747 748#define mmDMA3_QM_ARB_MST_CRED_STS_8 0x568BD0749 750#define mmDMA3_QM_ARB_MST_CRED_STS_9 0x568BD4751 752#define mmDMA3_QM_ARB_MST_CRED_STS_10 0x568BD8753 754#define mmDMA3_QM_ARB_MST_CRED_STS_11 0x568BDC755 756#define mmDMA3_QM_ARB_MST_CRED_STS_12 0x568BE0757 758#define mmDMA3_QM_ARB_MST_CRED_STS_13 0x568BE4759 760#define mmDMA3_QM_ARB_MST_CRED_STS_14 0x568BE8761 762#define mmDMA3_QM_ARB_MST_CRED_STS_15 0x568BEC763 764#define mmDMA3_QM_ARB_MST_CRED_STS_16 0x568BF0765 766#define mmDMA3_QM_ARB_MST_CRED_STS_17 0x568BF4767 768#define mmDMA3_QM_ARB_MST_CRED_STS_18 0x568BF8769 770#define mmDMA3_QM_ARB_MST_CRED_STS_19 0x568BFC771 772#define mmDMA3_QM_ARB_MST_CRED_STS_20 0x568C00773 774#define mmDMA3_QM_ARB_MST_CRED_STS_21 0x568C04775 776#define mmDMA3_QM_ARB_MST_CRED_STS_22 0x568C08777 778#define mmDMA3_QM_ARB_MST_CRED_STS_23 0x568C0C779 780#define mmDMA3_QM_ARB_MST_CRED_STS_24 0x568C10781 782#define mmDMA3_QM_ARB_MST_CRED_STS_25 0x568C14783 784#define mmDMA3_QM_ARB_MST_CRED_STS_26 0x568C18785 786#define mmDMA3_QM_ARB_MST_CRED_STS_27 0x568C1C787 788#define mmDMA3_QM_ARB_MST_CRED_STS_28 0x568C20789 790#define mmDMA3_QM_ARB_MST_CRED_STS_29 0x568C24791 792#define mmDMA3_QM_ARB_MST_CRED_STS_30 0x568C28793 794#define mmDMA3_QM_ARB_MST_CRED_STS_31 0x568C2C795 796#define mmDMA3_QM_CGM_CFG 0x568C70797 798#define mmDMA3_QM_CGM_STS 0x568C74799 800#define mmDMA3_QM_CGM_CFG1 0x568C78801 802#define mmDMA3_QM_LOCAL_RANGE_BASE 0x568C80803 804#define mmDMA3_QM_LOCAL_RANGE_SIZE 0x568C84805 806#define mmDMA3_QM_CSMR_STRICT_PRIO_CFG 0x568C90807 808#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 0x568C94809 810#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 0x568C98811 812#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 0x568C9C813 814#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 0x568CA0815 816#define mmDMA3_QM_GLBL_AXCACHE 0x568CA4817 818#define mmDMA3_QM_IND_GW_APB_CFG 0x568CB0819 820#define mmDMA3_QM_IND_GW_APB_WDATA 0x568CB4821 822#define mmDMA3_QM_IND_GW_APB_RDATA 0x568CB8823 824#define mmDMA3_QM_IND_GW_APB_STATUS 0x568CBC825 826#define mmDMA3_QM_GLBL_ERR_ADDR_LO 0x568CD0827 828#define mmDMA3_QM_GLBL_ERR_ADDR_HI 0x568CD4829 830#define mmDMA3_QM_GLBL_ERR_WDATA 0x568CD8831 832#define mmDMA3_QM_GLBL_MEM_INIT_BUSY 0x568D00833 834#endif /* ASIC_REG_DMA3_QM_REGS_H_ */835