835 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA4_QM_REGS_H_14#define ASIC_REG_DMA4_QM_REGS_H_15 16/*17 *****************************************18 * DMA4_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmDMA4_QM_GLBL_CFG0 0x58800023 24#define mmDMA4_QM_GLBL_CFG1 0x58800425 26#define mmDMA4_QM_GLBL_PROT 0x58800827 28#define mmDMA4_QM_GLBL_ERR_CFG 0x58800C29 30#define mmDMA4_QM_GLBL_SECURE_PROPS_0 0x58801031 32#define mmDMA4_QM_GLBL_SECURE_PROPS_1 0x58801433 34#define mmDMA4_QM_GLBL_SECURE_PROPS_2 0x58801835 36#define mmDMA4_QM_GLBL_SECURE_PROPS_3 0x58801C37 38#define mmDMA4_QM_GLBL_SECURE_PROPS_4 0x58802039 40#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 0x58802441 42#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 0x58802843 44#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 0x58802C45 46#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 0x58803047 48#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 0x58803449 50#define mmDMA4_QM_GLBL_STS0 0x58803851 52#define mmDMA4_QM_GLBL_STS1_0 0x58804053 54#define mmDMA4_QM_GLBL_STS1_1 0x58804455 56#define mmDMA4_QM_GLBL_STS1_2 0x58804857 58#define mmDMA4_QM_GLBL_STS1_3 0x58804C59 60#define mmDMA4_QM_GLBL_STS1_4 0x58805061 62#define mmDMA4_QM_GLBL_MSG_EN_0 0x58805463 64#define mmDMA4_QM_GLBL_MSG_EN_1 0x58805865 66#define mmDMA4_QM_GLBL_MSG_EN_2 0x58805C67 68#define mmDMA4_QM_GLBL_MSG_EN_3 0x58806069 70#define mmDMA4_QM_GLBL_MSG_EN_4 0x58806871 72#define mmDMA4_QM_PQ_BASE_LO_0 0x58807073 74#define mmDMA4_QM_PQ_BASE_LO_1 0x58807475 76#define mmDMA4_QM_PQ_BASE_LO_2 0x58807877 78#define mmDMA4_QM_PQ_BASE_LO_3 0x58807C79 80#define mmDMA4_QM_PQ_BASE_HI_0 0x58808081 82#define mmDMA4_QM_PQ_BASE_HI_1 0x58808483 84#define mmDMA4_QM_PQ_BASE_HI_2 0x58808885 86#define mmDMA4_QM_PQ_BASE_HI_3 0x58808C87 88#define mmDMA4_QM_PQ_SIZE_0 0x58809089 90#define mmDMA4_QM_PQ_SIZE_1 0x58809491 92#define mmDMA4_QM_PQ_SIZE_2 0x58809893 94#define mmDMA4_QM_PQ_SIZE_3 0x58809C95 96#define mmDMA4_QM_PQ_PI_0 0x5880A097 98#define mmDMA4_QM_PQ_PI_1 0x5880A499 100#define mmDMA4_QM_PQ_PI_2 0x5880A8101 102#define mmDMA4_QM_PQ_PI_3 0x5880AC103 104#define mmDMA4_QM_PQ_CI_0 0x5880B0105 106#define mmDMA4_QM_PQ_CI_1 0x5880B4107 108#define mmDMA4_QM_PQ_CI_2 0x5880B8109 110#define mmDMA4_QM_PQ_CI_3 0x5880BC111 112#define mmDMA4_QM_PQ_CFG0_0 0x5880C0113 114#define mmDMA4_QM_PQ_CFG0_1 0x5880C4115 116#define mmDMA4_QM_PQ_CFG0_2 0x5880C8117 118#define mmDMA4_QM_PQ_CFG0_3 0x5880CC119 120#define mmDMA4_QM_PQ_CFG1_0 0x5880D0121 122#define mmDMA4_QM_PQ_CFG1_1 0x5880D4123 124#define mmDMA4_QM_PQ_CFG1_2 0x5880D8125 126#define mmDMA4_QM_PQ_CFG1_3 0x5880DC127 128#define mmDMA4_QM_PQ_ARUSER_31_11_0 0x5880E0129 130#define mmDMA4_QM_PQ_ARUSER_31_11_1 0x5880E4131 132#define mmDMA4_QM_PQ_ARUSER_31_11_2 0x5880E8133 134#define mmDMA4_QM_PQ_ARUSER_31_11_3 0x5880EC135 136#define mmDMA4_QM_PQ_STS0_0 0x5880F0137 138#define mmDMA4_QM_PQ_STS0_1 0x5880F4139 140#define mmDMA4_QM_PQ_STS0_2 0x5880F8141 142#define mmDMA4_QM_PQ_STS0_3 0x5880FC143 144#define mmDMA4_QM_PQ_STS1_0 0x588100145 146#define mmDMA4_QM_PQ_STS1_1 0x588104147 148#define mmDMA4_QM_PQ_STS1_2 0x588108149 150#define mmDMA4_QM_PQ_STS1_3 0x58810C151 152#define mmDMA4_QM_CQ_CFG0_0 0x588110153 154#define mmDMA4_QM_CQ_CFG0_1 0x588114155 156#define mmDMA4_QM_CQ_CFG0_2 0x588118157 158#define mmDMA4_QM_CQ_CFG0_3 0x58811C159 160#define mmDMA4_QM_CQ_CFG0_4 0x588120161 162#define mmDMA4_QM_CQ_CFG1_0 0x588124163 164#define mmDMA4_QM_CQ_CFG1_1 0x588128165 166#define mmDMA4_QM_CQ_CFG1_2 0x58812C167 168#define mmDMA4_QM_CQ_CFG1_3 0x588130169 170#define mmDMA4_QM_CQ_CFG1_4 0x588134171 172#define mmDMA4_QM_CQ_ARUSER_31_11_0 0x588138173 174#define mmDMA4_QM_CQ_ARUSER_31_11_1 0x58813C175 176#define mmDMA4_QM_CQ_ARUSER_31_11_2 0x588140177 178#define mmDMA4_QM_CQ_ARUSER_31_11_3 0x588144179 180#define mmDMA4_QM_CQ_ARUSER_31_11_4 0x588148181 182#define mmDMA4_QM_CQ_STS0_0 0x58814C183 184#define mmDMA4_QM_CQ_STS0_1 0x588150185 186#define mmDMA4_QM_CQ_STS0_2 0x588154187 188#define mmDMA4_QM_CQ_STS0_3 0x588158189 190#define mmDMA4_QM_CQ_STS0_4 0x58815C191 192#define mmDMA4_QM_CQ_STS1_0 0x588160193 194#define mmDMA4_QM_CQ_STS1_1 0x588164195 196#define mmDMA4_QM_CQ_STS1_2 0x588168197 198#define mmDMA4_QM_CQ_STS1_3 0x58816C199 200#define mmDMA4_QM_CQ_STS1_4 0x588170201 202#define mmDMA4_QM_CQ_PTR_LO_0 0x588174203 204#define mmDMA4_QM_CQ_PTR_HI_0 0x588178205 206#define mmDMA4_QM_CQ_TSIZE_0 0x58817C207 208#define mmDMA4_QM_CQ_CTL_0 0x588180209 210#define mmDMA4_QM_CQ_PTR_LO_1 0x588184211 212#define mmDMA4_QM_CQ_PTR_HI_1 0x588188213 214#define mmDMA4_QM_CQ_TSIZE_1 0x58818C215 216#define mmDMA4_QM_CQ_CTL_1 0x588190217 218#define mmDMA4_QM_CQ_PTR_LO_2 0x588194219 220#define mmDMA4_QM_CQ_PTR_HI_2 0x588198221 222#define mmDMA4_QM_CQ_TSIZE_2 0x58819C223 224#define mmDMA4_QM_CQ_CTL_2 0x5881A0225 226#define mmDMA4_QM_CQ_PTR_LO_3 0x5881A4227 228#define mmDMA4_QM_CQ_PTR_HI_3 0x5881A8229 230#define mmDMA4_QM_CQ_TSIZE_3 0x5881AC231 232#define mmDMA4_QM_CQ_CTL_3 0x5881B0233 234#define mmDMA4_QM_CQ_PTR_LO_4 0x5881B4235 236#define mmDMA4_QM_CQ_PTR_HI_4 0x5881B8237 238#define mmDMA4_QM_CQ_TSIZE_4 0x5881BC239 240#define mmDMA4_QM_CQ_CTL_4 0x5881C0241 242#define mmDMA4_QM_CQ_PTR_LO_STS_0 0x5881C4243 244#define mmDMA4_QM_CQ_PTR_LO_STS_1 0x5881C8245 246#define mmDMA4_QM_CQ_PTR_LO_STS_2 0x5881CC247 248#define mmDMA4_QM_CQ_PTR_LO_STS_3 0x5881D0249 250#define mmDMA4_QM_CQ_PTR_LO_STS_4 0x5881D4251 252#define mmDMA4_QM_CQ_PTR_HI_STS_0 0x5881D8253 254#define mmDMA4_QM_CQ_PTR_HI_STS_1 0x5881DC255 256#define mmDMA4_QM_CQ_PTR_HI_STS_2 0x5881E0257 258#define mmDMA4_QM_CQ_PTR_HI_STS_3 0x5881E4259 260#define mmDMA4_QM_CQ_PTR_HI_STS_4 0x5881E8261 262#define mmDMA4_QM_CQ_TSIZE_STS_0 0x5881EC263 264#define mmDMA4_QM_CQ_TSIZE_STS_1 0x5881F0265 266#define mmDMA4_QM_CQ_TSIZE_STS_2 0x5881F4267 268#define mmDMA4_QM_CQ_TSIZE_STS_3 0x5881F8269 270#define mmDMA4_QM_CQ_TSIZE_STS_4 0x5881FC271 272#define mmDMA4_QM_CQ_CTL_STS_0 0x588200273 274#define mmDMA4_QM_CQ_CTL_STS_1 0x588204275 276#define mmDMA4_QM_CQ_CTL_STS_2 0x588208277 278#define mmDMA4_QM_CQ_CTL_STS_3 0x58820C279 280#define mmDMA4_QM_CQ_CTL_STS_4 0x588210281 282#define mmDMA4_QM_CQ_IFIFO_CNT_0 0x588214283 284#define mmDMA4_QM_CQ_IFIFO_CNT_1 0x588218285 286#define mmDMA4_QM_CQ_IFIFO_CNT_2 0x58821C287 288#define mmDMA4_QM_CQ_IFIFO_CNT_3 0x588220289 290#define mmDMA4_QM_CQ_IFIFO_CNT_4 0x588224291 292#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 0x588228293 294#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 0x58822C295 296#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 0x588230297 298#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 0x588234299 300#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 0x588238301 302#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 0x58823C303 304#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 0x588240305 306#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 0x588244307 308#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 0x588248309 310#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 0x58824C311 312#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 0x588250313 314#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 0x588254315 316#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 0x588258317 318#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 0x58825C319 320#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 0x588260321 322#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 0x588264323 324#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 0x588268325 326#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 0x58826C327 328#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 0x588270329 330#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 0x588274331 332#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 0x588278333 334#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 0x58827C335 336#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 0x588280337 338#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 0x588284339 340#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 0x588288341 342#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 0x58828C343 344#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 0x588290345 346#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 0x588294347 348#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 0x588298349 350#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 0x58829C351 352#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 0x5882A0353 354#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 0x5882A4355 356#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 0x5882A8357 358#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 0x5882AC359 360#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 0x5882B0361 362#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 0x5882B4363 364#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 0x5882B8365 366#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 0x5882BC367 368#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 0x5882C0369 370#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 0x5882C4371 372#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 0x5882C8373 374#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 0x5882CC375 376#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 0x5882D0377 378#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 0x5882D4379 380#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 0x5882D8381 382#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5882E0383 384#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5882E4385 386#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5882E8387 388#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5882EC389 390#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5882F0391 392#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5882F4393 394#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5882F8395 396#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5882FC397 398#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x588300399 400#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x588304401 402#define mmDMA4_QM_CP_FENCE0_RDATA_0 0x588308403 404#define mmDMA4_QM_CP_FENCE0_RDATA_1 0x58830C405 406#define mmDMA4_QM_CP_FENCE0_RDATA_2 0x588310407 408#define mmDMA4_QM_CP_FENCE0_RDATA_3 0x588314409 410#define mmDMA4_QM_CP_FENCE0_RDATA_4 0x588318411 412#define mmDMA4_QM_CP_FENCE1_RDATA_0 0x58831C413 414#define mmDMA4_QM_CP_FENCE1_RDATA_1 0x588320415 416#define mmDMA4_QM_CP_FENCE1_RDATA_2 0x588324417 418#define mmDMA4_QM_CP_FENCE1_RDATA_3 0x588328419 420#define mmDMA4_QM_CP_FENCE1_RDATA_4 0x58832C421 422#define mmDMA4_QM_CP_FENCE2_RDATA_0 0x588330423 424#define mmDMA4_QM_CP_FENCE2_RDATA_1 0x588334425 426#define mmDMA4_QM_CP_FENCE2_RDATA_2 0x588338427 428#define mmDMA4_QM_CP_FENCE2_RDATA_3 0x58833C429 430#define mmDMA4_QM_CP_FENCE2_RDATA_4 0x588340431 432#define mmDMA4_QM_CP_FENCE3_RDATA_0 0x588344433 434#define mmDMA4_QM_CP_FENCE3_RDATA_1 0x588348435 436#define mmDMA4_QM_CP_FENCE3_RDATA_2 0x58834C437 438#define mmDMA4_QM_CP_FENCE3_RDATA_3 0x588350439 440#define mmDMA4_QM_CP_FENCE3_RDATA_4 0x588354441 442#define mmDMA4_QM_CP_FENCE0_CNT_0 0x588358443 444#define mmDMA4_QM_CP_FENCE0_CNT_1 0x58835C445 446#define mmDMA4_QM_CP_FENCE0_CNT_2 0x588360447 448#define mmDMA4_QM_CP_FENCE0_CNT_3 0x588364449 450#define mmDMA4_QM_CP_FENCE0_CNT_4 0x588368451 452#define mmDMA4_QM_CP_FENCE1_CNT_0 0x58836C453 454#define mmDMA4_QM_CP_FENCE1_CNT_1 0x588370455 456#define mmDMA4_QM_CP_FENCE1_CNT_2 0x588374457 458#define mmDMA4_QM_CP_FENCE1_CNT_3 0x588378459 460#define mmDMA4_QM_CP_FENCE1_CNT_4 0x58837C461 462#define mmDMA4_QM_CP_FENCE2_CNT_0 0x588380463 464#define mmDMA4_QM_CP_FENCE2_CNT_1 0x588384465 466#define mmDMA4_QM_CP_FENCE2_CNT_2 0x588388467 468#define mmDMA4_QM_CP_FENCE2_CNT_3 0x58838C469 470#define mmDMA4_QM_CP_FENCE2_CNT_4 0x588390471 472#define mmDMA4_QM_CP_FENCE3_CNT_0 0x588394473 474#define mmDMA4_QM_CP_FENCE3_CNT_1 0x588398475 476#define mmDMA4_QM_CP_FENCE3_CNT_2 0x58839C477 478#define mmDMA4_QM_CP_FENCE3_CNT_3 0x5883A0479 480#define mmDMA4_QM_CP_FENCE3_CNT_4 0x5883A4481 482#define mmDMA4_QM_CP_STS_0 0x5883A8483 484#define mmDMA4_QM_CP_STS_1 0x5883AC485 486#define mmDMA4_QM_CP_STS_2 0x5883B0487 488#define mmDMA4_QM_CP_STS_3 0x5883B4489 490#define mmDMA4_QM_CP_STS_4 0x5883B8491 492#define mmDMA4_QM_CP_CURRENT_INST_LO_0 0x5883BC493 494#define mmDMA4_QM_CP_CURRENT_INST_LO_1 0x5883C0495 496#define mmDMA4_QM_CP_CURRENT_INST_LO_2 0x5883C4497 498#define mmDMA4_QM_CP_CURRENT_INST_LO_3 0x5883C8499 500#define mmDMA4_QM_CP_CURRENT_INST_LO_4 0x5883CC501 502#define mmDMA4_QM_CP_CURRENT_INST_HI_0 0x5883D0503 504#define mmDMA4_QM_CP_CURRENT_INST_HI_1 0x5883D4505 506#define mmDMA4_QM_CP_CURRENT_INST_HI_2 0x5883D8507 508#define mmDMA4_QM_CP_CURRENT_INST_HI_3 0x5883DC509 510#define mmDMA4_QM_CP_CURRENT_INST_HI_4 0x5883E0511 512#define mmDMA4_QM_CP_BARRIER_CFG_0 0x5883F4513 514#define mmDMA4_QM_CP_BARRIER_CFG_1 0x5883F8515 516#define mmDMA4_QM_CP_BARRIER_CFG_2 0x5883FC517 518#define mmDMA4_QM_CP_BARRIER_CFG_3 0x588400519 520#define mmDMA4_QM_CP_BARRIER_CFG_4 0x588404521 522#define mmDMA4_QM_CP_DBG_0_0 0x588408523 524#define mmDMA4_QM_CP_DBG_0_1 0x58840C525 526#define mmDMA4_QM_CP_DBG_0_2 0x588410527 528#define mmDMA4_QM_CP_DBG_0_3 0x588414529 530#define mmDMA4_QM_CP_DBG_0_4 0x588418531 532#define mmDMA4_QM_CP_ARUSER_31_11_0 0x58841C533 534#define mmDMA4_QM_CP_ARUSER_31_11_1 0x588420535 536#define mmDMA4_QM_CP_ARUSER_31_11_2 0x588424537 538#define mmDMA4_QM_CP_ARUSER_31_11_3 0x588428539 540#define mmDMA4_QM_CP_ARUSER_31_11_4 0x58842C541 542#define mmDMA4_QM_CP_AWUSER_31_11_0 0x588430543 544#define mmDMA4_QM_CP_AWUSER_31_11_1 0x588434545 546#define mmDMA4_QM_CP_AWUSER_31_11_2 0x588438547 548#define mmDMA4_QM_CP_AWUSER_31_11_3 0x58843C549 550#define mmDMA4_QM_CP_AWUSER_31_11_4 0x588440551 552#define mmDMA4_QM_ARB_CFG_0 0x588A00553 554#define mmDMA4_QM_ARB_CHOISE_Q_PUSH 0x588A04555 556#define mmDMA4_QM_ARB_WRR_WEIGHT_0 0x588A08557 558#define mmDMA4_QM_ARB_WRR_WEIGHT_1 0x588A0C559 560#define mmDMA4_QM_ARB_WRR_WEIGHT_2 0x588A10561 562#define mmDMA4_QM_ARB_WRR_WEIGHT_3 0x588A14563 564#define mmDMA4_QM_ARB_CFG_1 0x588A18565 566#define mmDMA4_QM_ARB_MST_AVAIL_CRED_0 0x588A20567 568#define mmDMA4_QM_ARB_MST_AVAIL_CRED_1 0x588A24569 570#define mmDMA4_QM_ARB_MST_AVAIL_CRED_2 0x588A28571 572#define mmDMA4_QM_ARB_MST_AVAIL_CRED_3 0x588A2C573 574#define mmDMA4_QM_ARB_MST_AVAIL_CRED_4 0x588A30575 576#define mmDMA4_QM_ARB_MST_AVAIL_CRED_5 0x588A34577 578#define mmDMA4_QM_ARB_MST_AVAIL_CRED_6 0x588A38579 580#define mmDMA4_QM_ARB_MST_AVAIL_CRED_7 0x588A3C581 582#define mmDMA4_QM_ARB_MST_AVAIL_CRED_8 0x588A40583 584#define mmDMA4_QM_ARB_MST_AVAIL_CRED_9 0x588A44585 586#define mmDMA4_QM_ARB_MST_AVAIL_CRED_10 0x588A48587 588#define mmDMA4_QM_ARB_MST_AVAIL_CRED_11 0x588A4C589 590#define mmDMA4_QM_ARB_MST_AVAIL_CRED_12 0x588A50591 592#define mmDMA4_QM_ARB_MST_AVAIL_CRED_13 0x588A54593 594#define mmDMA4_QM_ARB_MST_AVAIL_CRED_14 0x588A58595 596#define mmDMA4_QM_ARB_MST_AVAIL_CRED_15 0x588A5C597 598#define mmDMA4_QM_ARB_MST_AVAIL_CRED_16 0x588A60599 600#define mmDMA4_QM_ARB_MST_AVAIL_CRED_17 0x588A64601 602#define mmDMA4_QM_ARB_MST_AVAIL_CRED_18 0x588A68603 604#define mmDMA4_QM_ARB_MST_AVAIL_CRED_19 0x588A6C605 606#define mmDMA4_QM_ARB_MST_AVAIL_CRED_20 0x588A70607 608#define mmDMA4_QM_ARB_MST_AVAIL_CRED_21 0x588A74609 610#define mmDMA4_QM_ARB_MST_AVAIL_CRED_22 0x588A78611 612#define mmDMA4_QM_ARB_MST_AVAIL_CRED_23 0x588A7C613 614#define mmDMA4_QM_ARB_MST_AVAIL_CRED_24 0x588A80615 616#define mmDMA4_QM_ARB_MST_AVAIL_CRED_25 0x588A84617 618#define mmDMA4_QM_ARB_MST_AVAIL_CRED_26 0x588A88619 620#define mmDMA4_QM_ARB_MST_AVAIL_CRED_27 0x588A8C621 622#define mmDMA4_QM_ARB_MST_AVAIL_CRED_28 0x588A90623 624#define mmDMA4_QM_ARB_MST_AVAIL_CRED_29 0x588A94625 626#define mmDMA4_QM_ARB_MST_AVAIL_CRED_30 0x588A98627 628#define mmDMA4_QM_ARB_MST_AVAIL_CRED_31 0x588A9C629 630#define mmDMA4_QM_ARB_MST_CRED_INC 0x588AA0631 632#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x588AA4633 634#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x588AA8635 636#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x588AAC637 638#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x588AB0639 640#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x588AB4641 642#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x588AB8643 644#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x588ABC645 646#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x588AC0647 648#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x588AC4649 650#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x588AC8651 652#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x588ACC653 654#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x588AD0655 656#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x588AD4657 658#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x588AD8659 660#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x588ADC661 662#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x588AE0663 664#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x588AE4665 666#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x588AE8667 668#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x588AEC669 670#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x588AF0671 672#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x588AF4673 674#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x588AF8675 676#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x588AFC677 678#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x588B00679 680#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x588B04681 682#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x588B08683 684#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x588B0C685 686#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x588B10687 688#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x588B14689 690#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x588B18691 692#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x588B1C693 694#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x588B20695 696#define mmDMA4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x588B28697 698#define mmDMA4_QM_ARB_MST_SLAVE_EN 0x588B2C699 700#define mmDMA4_QM_ARB_MST_QUIET_PER 0x588B34701 702#define mmDMA4_QM_ARB_SLV_CHOISE_WDT 0x588B38703 704#define mmDMA4_QM_ARB_SLV_ID 0x588B3C705 706#define mmDMA4_QM_ARB_MSG_MAX_INFLIGHT 0x588B44707 708#define mmDMA4_QM_ARB_MSG_AWUSER_31_11 0x588B48709 710#define mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP 0x588B4C711 712#define mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x588B50713 714#define mmDMA4_QM_ARB_BASE_LO 0x588B54715 716#define mmDMA4_QM_ARB_BASE_HI 0x588B58717 718#define mmDMA4_QM_ARB_STATE_STS 0x588B80719 720#define mmDMA4_QM_ARB_CHOISE_FULLNESS_STS 0x588B84721 722#define mmDMA4_QM_ARB_MSG_STS 0x588B88723 724#define mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD 0x588B8C725 726#define mmDMA4_QM_ARB_ERR_CAUSE 0x588B9C727 728#define mmDMA4_QM_ARB_ERR_MSG_EN 0x588BA0729 730#define mmDMA4_QM_ARB_ERR_STS_DRP 0x588BA8731 732#define mmDMA4_QM_ARB_MST_CRED_STS_0 0x588BB0733 734#define mmDMA4_QM_ARB_MST_CRED_STS_1 0x588BB4735 736#define mmDMA4_QM_ARB_MST_CRED_STS_2 0x588BB8737 738#define mmDMA4_QM_ARB_MST_CRED_STS_3 0x588BBC739 740#define mmDMA4_QM_ARB_MST_CRED_STS_4 0x588BC0741 742#define mmDMA4_QM_ARB_MST_CRED_STS_5 0x588BC4743 744#define mmDMA4_QM_ARB_MST_CRED_STS_6 0x588BC8745 746#define mmDMA4_QM_ARB_MST_CRED_STS_7 0x588BCC747 748#define mmDMA4_QM_ARB_MST_CRED_STS_8 0x588BD0749 750#define mmDMA4_QM_ARB_MST_CRED_STS_9 0x588BD4751 752#define mmDMA4_QM_ARB_MST_CRED_STS_10 0x588BD8753 754#define mmDMA4_QM_ARB_MST_CRED_STS_11 0x588BDC755 756#define mmDMA4_QM_ARB_MST_CRED_STS_12 0x588BE0757 758#define mmDMA4_QM_ARB_MST_CRED_STS_13 0x588BE4759 760#define mmDMA4_QM_ARB_MST_CRED_STS_14 0x588BE8761 762#define mmDMA4_QM_ARB_MST_CRED_STS_15 0x588BEC763 764#define mmDMA4_QM_ARB_MST_CRED_STS_16 0x588BF0765 766#define mmDMA4_QM_ARB_MST_CRED_STS_17 0x588BF4767 768#define mmDMA4_QM_ARB_MST_CRED_STS_18 0x588BF8769 770#define mmDMA4_QM_ARB_MST_CRED_STS_19 0x588BFC771 772#define mmDMA4_QM_ARB_MST_CRED_STS_20 0x588C00773 774#define mmDMA4_QM_ARB_MST_CRED_STS_21 0x588C04775 776#define mmDMA4_QM_ARB_MST_CRED_STS_22 0x588C08777 778#define mmDMA4_QM_ARB_MST_CRED_STS_23 0x588C0C779 780#define mmDMA4_QM_ARB_MST_CRED_STS_24 0x588C10781 782#define mmDMA4_QM_ARB_MST_CRED_STS_25 0x588C14783 784#define mmDMA4_QM_ARB_MST_CRED_STS_26 0x588C18785 786#define mmDMA4_QM_ARB_MST_CRED_STS_27 0x588C1C787 788#define mmDMA4_QM_ARB_MST_CRED_STS_28 0x588C20789 790#define mmDMA4_QM_ARB_MST_CRED_STS_29 0x588C24791 792#define mmDMA4_QM_ARB_MST_CRED_STS_30 0x588C28793 794#define mmDMA4_QM_ARB_MST_CRED_STS_31 0x588C2C795 796#define mmDMA4_QM_CGM_CFG 0x588C70797 798#define mmDMA4_QM_CGM_STS 0x588C74799 800#define mmDMA4_QM_CGM_CFG1 0x588C78801 802#define mmDMA4_QM_LOCAL_RANGE_BASE 0x588C80803 804#define mmDMA4_QM_LOCAL_RANGE_SIZE 0x588C84805 806#define mmDMA4_QM_CSMR_STRICT_PRIO_CFG 0x588C90807 808#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 0x588C94809 810#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 0x588C98811 812#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 0x588C9C813 814#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 0x588CA0815 816#define mmDMA4_QM_GLBL_AXCACHE 0x588CA4817 818#define mmDMA4_QM_IND_GW_APB_CFG 0x588CB0819 820#define mmDMA4_QM_IND_GW_APB_WDATA 0x588CB4821 822#define mmDMA4_QM_IND_GW_APB_RDATA 0x588CB8823 824#define mmDMA4_QM_IND_GW_APB_STATUS 0x588CBC825 826#define mmDMA4_QM_GLBL_ERR_ADDR_LO 0x588CD0827 828#define mmDMA4_QM_GLBL_ERR_ADDR_HI 0x588CD4829 830#define mmDMA4_QM_GLBL_ERR_WDATA 0x588CD8831 832#define mmDMA4_QM_GLBL_MEM_INIT_BUSY 0x588D00833 834#endif /* ASIC_REG_DMA4_QM_REGS_H_ */835