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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA5_QM_REGS_H_14#define ASIC_REG_DMA5_QM_REGS_H_15 16/*17 *****************************************18 * DMA5_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmDMA5_QM_GLBL_CFG0 0x5A800023 24#define mmDMA5_QM_GLBL_CFG1 0x5A800425 26#define mmDMA5_QM_GLBL_PROT 0x5A800827 28#define mmDMA5_QM_GLBL_ERR_CFG 0x5A800C29 30#define mmDMA5_QM_GLBL_SECURE_PROPS_0 0x5A801031 32#define mmDMA5_QM_GLBL_SECURE_PROPS_1 0x5A801433 34#define mmDMA5_QM_GLBL_SECURE_PROPS_2 0x5A801835 36#define mmDMA5_QM_GLBL_SECURE_PROPS_3 0x5A801C37 38#define mmDMA5_QM_GLBL_SECURE_PROPS_4 0x5A802039 40#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 0x5A802441 42#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 0x5A802843 44#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 0x5A802C45 46#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 0x5A803047 48#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 0x5A803449 50#define mmDMA5_QM_GLBL_STS0 0x5A803851 52#define mmDMA5_QM_GLBL_STS1_0 0x5A804053 54#define mmDMA5_QM_GLBL_STS1_1 0x5A804455 56#define mmDMA5_QM_GLBL_STS1_2 0x5A804857 58#define mmDMA5_QM_GLBL_STS1_3 0x5A804C59 60#define mmDMA5_QM_GLBL_STS1_4 0x5A805061 62#define mmDMA5_QM_GLBL_MSG_EN_0 0x5A805463 64#define mmDMA5_QM_GLBL_MSG_EN_1 0x5A805865 66#define mmDMA5_QM_GLBL_MSG_EN_2 0x5A805C67 68#define mmDMA5_QM_GLBL_MSG_EN_3 0x5A806069 70#define mmDMA5_QM_GLBL_MSG_EN_4 0x5A806871 72#define mmDMA5_QM_PQ_BASE_LO_0 0x5A807073 74#define mmDMA5_QM_PQ_BASE_LO_1 0x5A807475 76#define mmDMA5_QM_PQ_BASE_LO_2 0x5A807877 78#define mmDMA5_QM_PQ_BASE_LO_3 0x5A807C79 80#define mmDMA5_QM_PQ_BASE_HI_0 0x5A808081 82#define mmDMA5_QM_PQ_BASE_HI_1 0x5A808483 84#define mmDMA5_QM_PQ_BASE_HI_2 0x5A808885 86#define mmDMA5_QM_PQ_BASE_HI_3 0x5A808C87 88#define mmDMA5_QM_PQ_SIZE_0 0x5A809089 90#define mmDMA5_QM_PQ_SIZE_1 0x5A809491 92#define mmDMA5_QM_PQ_SIZE_2 0x5A809893 94#define mmDMA5_QM_PQ_SIZE_3 0x5A809C95 96#define mmDMA5_QM_PQ_PI_0 0x5A80A097 98#define mmDMA5_QM_PQ_PI_1 0x5A80A499 100#define mmDMA5_QM_PQ_PI_2 0x5A80A8101 102#define mmDMA5_QM_PQ_PI_3 0x5A80AC103 104#define mmDMA5_QM_PQ_CI_0 0x5A80B0105 106#define mmDMA5_QM_PQ_CI_1 0x5A80B4107 108#define mmDMA5_QM_PQ_CI_2 0x5A80B8109 110#define mmDMA5_QM_PQ_CI_3 0x5A80BC111 112#define mmDMA5_QM_PQ_CFG0_0 0x5A80C0113 114#define mmDMA5_QM_PQ_CFG0_1 0x5A80C4115 116#define mmDMA5_QM_PQ_CFG0_2 0x5A80C8117 118#define mmDMA5_QM_PQ_CFG0_3 0x5A80CC119 120#define mmDMA5_QM_PQ_CFG1_0 0x5A80D0121 122#define mmDMA5_QM_PQ_CFG1_1 0x5A80D4123 124#define mmDMA5_QM_PQ_CFG1_2 0x5A80D8125 126#define mmDMA5_QM_PQ_CFG1_3 0x5A80DC127 128#define mmDMA5_QM_PQ_ARUSER_31_11_0 0x5A80E0129 130#define mmDMA5_QM_PQ_ARUSER_31_11_1 0x5A80E4131 132#define mmDMA5_QM_PQ_ARUSER_31_11_2 0x5A80E8133 134#define mmDMA5_QM_PQ_ARUSER_31_11_3 0x5A80EC135 136#define mmDMA5_QM_PQ_STS0_0 0x5A80F0137 138#define mmDMA5_QM_PQ_STS0_1 0x5A80F4139 140#define mmDMA5_QM_PQ_STS0_2 0x5A80F8141 142#define mmDMA5_QM_PQ_STS0_3 0x5A80FC143 144#define mmDMA5_QM_PQ_STS1_0 0x5A8100145 146#define mmDMA5_QM_PQ_STS1_1 0x5A8104147 148#define mmDMA5_QM_PQ_STS1_2 0x5A8108149 150#define mmDMA5_QM_PQ_STS1_3 0x5A810C151 152#define mmDMA5_QM_CQ_CFG0_0 0x5A8110153 154#define mmDMA5_QM_CQ_CFG0_1 0x5A8114155 156#define mmDMA5_QM_CQ_CFG0_2 0x5A8118157 158#define mmDMA5_QM_CQ_CFG0_3 0x5A811C159 160#define mmDMA5_QM_CQ_CFG0_4 0x5A8120161 162#define mmDMA5_QM_CQ_CFG1_0 0x5A8124163 164#define mmDMA5_QM_CQ_CFG1_1 0x5A8128165 166#define mmDMA5_QM_CQ_CFG1_2 0x5A812C167 168#define mmDMA5_QM_CQ_CFG1_3 0x5A8130169 170#define mmDMA5_QM_CQ_CFG1_4 0x5A8134171 172#define mmDMA5_QM_CQ_ARUSER_31_11_0 0x5A8138173 174#define mmDMA5_QM_CQ_ARUSER_31_11_1 0x5A813C175 176#define mmDMA5_QM_CQ_ARUSER_31_11_2 0x5A8140177 178#define mmDMA5_QM_CQ_ARUSER_31_11_3 0x5A8144179 180#define mmDMA5_QM_CQ_ARUSER_31_11_4 0x5A8148181 182#define mmDMA5_QM_CQ_STS0_0 0x5A814C183 184#define mmDMA5_QM_CQ_STS0_1 0x5A8150185 186#define mmDMA5_QM_CQ_STS0_2 0x5A8154187 188#define mmDMA5_QM_CQ_STS0_3 0x5A8158189 190#define mmDMA5_QM_CQ_STS0_4 0x5A815C191 192#define mmDMA5_QM_CQ_STS1_0 0x5A8160193 194#define mmDMA5_QM_CQ_STS1_1 0x5A8164195 196#define mmDMA5_QM_CQ_STS1_2 0x5A8168197 198#define mmDMA5_QM_CQ_STS1_3 0x5A816C199 200#define mmDMA5_QM_CQ_STS1_4 0x5A8170201 202#define mmDMA5_QM_CQ_PTR_LO_0 0x5A8174203 204#define mmDMA5_QM_CQ_PTR_HI_0 0x5A8178205 206#define mmDMA5_QM_CQ_TSIZE_0 0x5A817C207 208#define mmDMA5_QM_CQ_CTL_0 0x5A8180209 210#define mmDMA5_QM_CQ_PTR_LO_1 0x5A8184211 212#define mmDMA5_QM_CQ_PTR_HI_1 0x5A8188213 214#define mmDMA5_QM_CQ_TSIZE_1 0x5A818C215 216#define mmDMA5_QM_CQ_CTL_1 0x5A8190217 218#define mmDMA5_QM_CQ_PTR_LO_2 0x5A8194219 220#define mmDMA5_QM_CQ_PTR_HI_2 0x5A8198221 222#define mmDMA5_QM_CQ_TSIZE_2 0x5A819C223 224#define mmDMA5_QM_CQ_CTL_2 0x5A81A0225 226#define mmDMA5_QM_CQ_PTR_LO_3 0x5A81A4227 228#define mmDMA5_QM_CQ_PTR_HI_3 0x5A81A8229 230#define mmDMA5_QM_CQ_TSIZE_3 0x5A81AC231 232#define mmDMA5_QM_CQ_CTL_3 0x5A81B0233 234#define mmDMA5_QM_CQ_PTR_LO_4 0x5A81B4235 236#define mmDMA5_QM_CQ_PTR_HI_4 0x5A81B8237 238#define mmDMA5_QM_CQ_TSIZE_4 0x5A81BC239 240#define mmDMA5_QM_CQ_CTL_4 0x5A81C0241 242#define mmDMA5_QM_CQ_PTR_LO_STS_0 0x5A81C4243 244#define mmDMA5_QM_CQ_PTR_LO_STS_1 0x5A81C8245 246#define mmDMA5_QM_CQ_PTR_LO_STS_2 0x5A81CC247 248#define mmDMA5_QM_CQ_PTR_LO_STS_3 0x5A81D0249 250#define mmDMA5_QM_CQ_PTR_LO_STS_4 0x5A81D4251 252#define mmDMA5_QM_CQ_PTR_HI_STS_0 0x5A81D8253 254#define mmDMA5_QM_CQ_PTR_HI_STS_1 0x5A81DC255 256#define mmDMA5_QM_CQ_PTR_HI_STS_2 0x5A81E0257 258#define mmDMA5_QM_CQ_PTR_HI_STS_3 0x5A81E4259 260#define mmDMA5_QM_CQ_PTR_HI_STS_4 0x5A81E8261 262#define mmDMA5_QM_CQ_TSIZE_STS_0 0x5A81EC263 264#define mmDMA5_QM_CQ_TSIZE_STS_1 0x5A81F0265 266#define mmDMA5_QM_CQ_TSIZE_STS_2 0x5A81F4267 268#define mmDMA5_QM_CQ_TSIZE_STS_3 0x5A81F8269 270#define mmDMA5_QM_CQ_TSIZE_STS_4 0x5A81FC271 272#define mmDMA5_QM_CQ_CTL_STS_0 0x5A8200273 274#define mmDMA5_QM_CQ_CTL_STS_1 0x5A8204275 276#define mmDMA5_QM_CQ_CTL_STS_2 0x5A8208277 278#define mmDMA5_QM_CQ_CTL_STS_3 0x5A820C279 280#define mmDMA5_QM_CQ_CTL_STS_4 0x5A8210281 282#define mmDMA5_QM_CQ_IFIFO_CNT_0 0x5A8214283 284#define mmDMA5_QM_CQ_IFIFO_CNT_1 0x5A8218285 286#define mmDMA5_QM_CQ_IFIFO_CNT_2 0x5A821C287 288#define mmDMA5_QM_CQ_IFIFO_CNT_3 0x5A8220289 290#define mmDMA5_QM_CQ_IFIFO_CNT_4 0x5A8224291 292#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 0x5A8228293 294#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 0x5A822C295 296#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 0x5A8230297 298#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 0x5A8234299 300#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 0x5A8238301 302#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 0x5A823C303 304#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 0x5A8240305 306#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 0x5A8244307 308#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 0x5A8248309 310#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 0x5A824C311 312#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 0x5A8250313 314#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 0x5A8254315 316#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 0x5A8258317 318#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 0x5A825C319 320#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 0x5A8260321 322#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 0x5A8264323 324#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 0x5A8268325 326#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 0x5A826C327 328#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 0x5A8270329 330#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 0x5A8274331 332#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 0x5A8278333 334#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 0x5A827C335 336#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 0x5A8280337 338#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 0x5A8284339 340#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 0x5A8288341 342#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 0x5A828C343 344#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 0x5A8290345 346#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 0x5A8294347 348#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 0x5A8298349 350#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 0x5A829C351 352#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 0x5A82A0353 354#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 0x5A82A4355 356#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 0x5A82A8357 358#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 0x5A82AC359 360#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 0x5A82B0361 362#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 0x5A82B4363 364#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 0x5A82B8365 366#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 0x5A82BC367 368#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 0x5A82C0369 370#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 0x5A82C4371 372#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 0x5A82C8373 374#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 0x5A82CC375 376#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 0x5A82D0377 378#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 0x5A82D4379 380#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 0x5A82D8381 382#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5A82E0383 384#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5A82E4385 386#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5A82E8387 388#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5A82EC389 390#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5A82F0391 392#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5A82F4393 394#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5A82F8395 396#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5A82FC397 398#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5A8300399 400#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5A8304401 402#define mmDMA5_QM_CP_FENCE0_RDATA_0 0x5A8308403 404#define mmDMA5_QM_CP_FENCE0_RDATA_1 0x5A830C405 406#define mmDMA5_QM_CP_FENCE0_RDATA_2 0x5A8310407 408#define mmDMA5_QM_CP_FENCE0_RDATA_3 0x5A8314409 410#define mmDMA5_QM_CP_FENCE0_RDATA_4 0x5A8318411 412#define mmDMA5_QM_CP_FENCE1_RDATA_0 0x5A831C413 414#define mmDMA5_QM_CP_FENCE1_RDATA_1 0x5A8320415 416#define mmDMA5_QM_CP_FENCE1_RDATA_2 0x5A8324417 418#define mmDMA5_QM_CP_FENCE1_RDATA_3 0x5A8328419 420#define mmDMA5_QM_CP_FENCE1_RDATA_4 0x5A832C421 422#define mmDMA5_QM_CP_FENCE2_RDATA_0 0x5A8330423 424#define mmDMA5_QM_CP_FENCE2_RDATA_1 0x5A8334425 426#define mmDMA5_QM_CP_FENCE2_RDATA_2 0x5A8338427 428#define mmDMA5_QM_CP_FENCE2_RDATA_3 0x5A833C429 430#define mmDMA5_QM_CP_FENCE2_RDATA_4 0x5A8340431 432#define mmDMA5_QM_CP_FENCE3_RDATA_0 0x5A8344433 434#define mmDMA5_QM_CP_FENCE3_RDATA_1 0x5A8348435 436#define mmDMA5_QM_CP_FENCE3_RDATA_2 0x5A834C437 438#define mmDMA5_QM_CP_FENCE3_RDATA_3 0x5A8350439 440#define mmDMA5_QM_CP_FENCE3_RDATA_4 0x5A8354441 442#define mmDMA5_QM_CP_FENCE0_CNT_0 0x5A8358443 444#define mmDMA5_QM_CP_FENCE0_CNT_1 0x5A835C445 446#define mmDMA5_QM_CP_FENCE0_CNT_2 0x5A8360447 448#define mmDMA5_QM_CP_FENCE0_CNT_3 0x5A8364449 450#define mmDMA5_QM_CP_FENCE0_CNT_4 0x5A8368451 452#define mmDMA5_QM_CP_FENCE1_CNT_0 0x5A836C453 454#define mmDMA5_QM_CP_FENCE1_CNT_1 0x5A8370455 456#define mmDMA5_QM_CP_FENCE1_CNT_2 0x5A8374457 458#define mmDMA5_QM_CP_FENCE1_CNT_3 0x5A8378459 460#define mmDMA5_QM_CP_FENCE1_CNT_4 0x5A837C461 462#define mmDMA5_QM_CP_FENCE2_CNT_0 0x5A8380463 464#define mmDMA5_QM_CP_FENCE2_CNT_1 0x5A8384465 466#define mmDMA5_QM_CP_FENCE2_CNT_2 0x5A8388467 468#define mmDMA5_QM_CP_FENCE2_CNT_3 0x5A838C469 470#define mmDMA5_QM_CP_FENCE2_CNT_4 0x5A8390471 472#define mmDMA5_QM_CP_FENCE3_CNT_0 0x5A8394473 474#define mmDMA5_QM_CP_FENCE3_CNT_1 0x5A8398475 476#define mmDMA5_QM_CP_FENCE3_CNT_2 0x5A839C477 478#define mmDMA5_QM_CP_FENCE3_CNT_3 0x5A83A0479 480#define mmDMA5_QM_CP_FENCE3_CNT_4 0x5A83A4481 482#define mmDMA5_QM_CP_STS_0 0x5A83A8483 484#define mmDMA5_QM_CP_STS_1 0x5A83AC485 486#define mmDMA5_QM_CP_STS_2 0x5A83B0487 488#define mmDMA5_QM_CP_STS_3 0x5A83B4489 490#define mmDMA5_QM_CP_STS_4 0x5A83B8491 492#define mmDMA5_QM_CP_CURRENT_INST_LO_0 0x5A83BC493 494#define mmDMA5_QM_CP_CURRENT_INST_LO_1 0x5A83C0495 496#define mmDMA5_QM_CP_CURRENT_INST_LO_2 0x5A83C4497 498#define mmDMA5_QM_CP_CURRENT_INST_LO_3 0x5A83C8499 500#define mmDMA5_QM_CP_CURRENT_INST_LO_4 0x5A83CC501 502#define mmDMA5_QM_CP_CURRENT_INST_HI_0 0x5A83D0503 504#define mmDMA5_QM_CP_CURRENT_INST_HI_1 0x5A83D4505 506#define mmDMA5_QM_CP_CURRENT_INST_HI_2 0x5A83D8507 508#define mmDMA5_QM_CP_CURRENT_INST_HI_3 0x5A83DC509 510#define mmDMA5_QM_CP_CURRENT_INST_HI_4 0x5A83E0511 512#define mmDMA5_QM_CP_BARRIER_CFG_0 0x5A83F4513 514#define mmDMA5_QM_CP_BARRIER_CFG_1 0x5A83F8515 516#define mmDMA5_QM_CP_BARRIER_CFG_2 0x5A83FC517 518#define mmDMA5_QM_CP_BARRIER_CFG_3 0x5A8400519 520#define mmDMA5_QM_CP_BARRIER_CFG_4 0x5A8404521 522#define mmDMA5_QM_CP_DBG_0_0 0x5A8408523 524#define mmDMA5_QM_CP_DBG_0_1 0x5A840C525 526#define mmDMA5_QM_CP_DBG_0_2 0x5A8410527 528#define mmDMA5_QM_CP_DBG_0_3 0x5A8414529 530#define mmDMA5_QM_CP_DBG_0_4 0x5A8418531 532#define mmDMA5_QM_CP_ARUSER_31_11_0 0x5A841C533 534#define mmDMA5_QM_CP_ARUSER_31_11_1 0x5A8420535 536#define mmDMA5_QM_CP_ARUSER_31_11_2 0x5A8424537 538#define mmDMA5_QM_CP_ARUSER_31_11_3 0x5A8428539 540#define mmDMA5_QM_CP_ARUSER_31_11_4 0x5A842C541 542#define mmDMA5_QM_CP_AWUSER_31_11_0 0x5A8430543 544#define mmDMA5_QM_CP_AWUSER_31_11_1 0x5A8434545 546#define mmDMA5_QM_CP_AWUSER_31_11_2 0x5A8438547 548#define mmDMA5_QM_CP_AWUSER_31_11_3 0x5A843C549 550#define mmDMA5_QM_CP_AWUSER_31_11_4 0x5A8440551 552#define mmDMA5_QM_ARB_CFG_0 0x5A8A00553 554#define mmDMA5_QM_ARB_CHOISE_Q_PUSH 0x5A8A04555 556#define mmDMA5_QM_ARB_WRR_WEIGHT_0 0x5A8A08557 558#define mmDMA5_QM_ARB_WRR_WEIGHT_1 0x5A8A0C559 560#define mmDMA5_QM_ARB_WRR_WEIGHT_2 0x5A8A10561 562#define mmDMA5_QM_ARB_WRR_WEIGHT_3 0x5A8A14563 564#define mmDMA5_QM_ARB_CFG_1 0x5A8A18565 566#define mmDMA5_QM_ARB_MST_AVAIL_CRED_0 0x5A8A20567 568#define mmDMA5_QM_ARB_MST_AVAIL_CRED_1 0x5A8A24569 570#define mmDMA5_QM_ARB_MST_AVAIL_CRED_2 0x5A8A28571 572#define mmDMA5_QM_ARB_MST_AVAIL_CRED_3 0x5A8A2C573 574#define mmDMA5_QM_ARB_MST_AVAIL_CRED_4 0x5A8A30575 576#define mmDMA5_QM_ARB_MST_AVAIL_CRED_5 0x5A8A34577 578#define mmDMA5_QM_ARB_MST_AVAIL_CRED_6 0x5A8A38579 580#define mmDMA5_QM_ARB_MST_AVAIL_CRED_7 0x5A8A3C581 582#define mmDMA5_QM_ARB_MST_AVAIL_CRED_8 0x5A8A40583 584#define mmDMA5_QM_ARB_MST_AVAIL_CRED_9 0x5A8A44585 586#define mmDMA5_QM_ARB_MST_AVAIL_CRED_10 0x5A8A48587 588#define mmDMA5_QM_ARB_MST_AVAIL_CRED_11 0x5A8A4C589 590#define mmDMA5_QM_ARB_MST_AVAIL_CRED_12 0x5A8A50591 592#define mmDMA5_QM_ARB_MST_AVAIL_CRED_13 0x5A8A54593 594#define mmDMA5_QM_ARB_MST_AVAIL_CRED_14 0x5A8A58595 596#define mmDMA5_QM_ARB_MST_AVAIL_CRED_15 0x5A8A5C597 598#define mmDMA5_QM_ARB_MST_AVAIL_CRED_16 0x5A8A60599 600#define mmDMA5_QM_ARB_MST_AVAIL_CRED_17 0x5A8A64601 602#define mmDMA5_QM_ARB_MST_AVAIL_CRED_18 0x5A8A68603 604#define mmDMA5_QM_ARB_MST_AVAIL_CRED_19 0x5A8A6C605 606#define mmDMA5_QM_ARB_MST_AVAIL_CRED_20 0x5A8A70607 608#define mmDMA5_QM_ARB_MST_AVAIL_CRED_21 0x5A8A74609 610#define mmDMA5_QM_ARB_MST_AVAIL_CRED_22 0x5A8A78611 612#define mmDMA5_QM_ARB_MST_AVAIL_CRED_23 0x5A8A7C613 614#define mmDMA5_QM_ARB_MST_AVAIL_CRED_24 0x5A8A80615 616#define mmDMA5_QM_ARB_MST_AVAIL_CRED_25 0x5A8A84617 618#define mmDMA5_QM_ARB_MST_AVAIL_CRED_26 0x5A8A88619 620#define mmDMA5_QM_ARB_MST_AVAIL_CRED_27 0x5A8A8C621 622#define mmDMA5_QM_ARB_MST_AVAIL_CRED_28 0x5A8A90623 624#define mmDMA5_QM_ARB_MST_AVAIL_CRED_29 0x5A8A94625 626#define mmDMA5_QM_ARB_MST_AVAIL_CRED_30 0x5A8A98627 628#define mmDMA5_QM_ARB_MST_AVAIL_CRED_31 0x5A8A9C629 630#define mmDMA5_QM_ARB_MST_CRED_INC 0x5A8AA0631 632#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5A8AA4633 634#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5A8AA8635 636#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5A8AAC637 638#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5A8AB0639 640#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5A8AB4641 642#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5A8AB8643 644#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5A8ABC645 646#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5A8AC0647 648#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5A8AC4649 650#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5A8AC8651 652#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5A8ACC653 654#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5A8AD0655 656#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5A8AD4657 658#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5A8AD8659 660#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5A8ADC661 662#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5A8AE0663 664#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5A8AE4665 666#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5A8AE8667 668#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5A8AEC669 670#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5A8AF0671 672#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5A8AF4673 674#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5A8AF8675 676#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5A8AFC677 678#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5A8B00679 680#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5A8B04681 682#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5A8B08683 684#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5A8B0C685 686#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5A8B10687 688#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5A8B14689 690#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5A8B18691 692#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5A8B1C693 694#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5A8B20695 696#define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5A8B28697 698#define mmDMA5_QM_ARB_MST_SLAVE_EN 0x5A8B2C699 700#define mmDMA5_QM_ARB_MST_QUIET_PER 0x5A8B34701 702#define mmDMA5_QM_ARB_SLV_CHOISE_WDT 0x5A8B38703 704#define mmDMA5_QM_ARB_SLV_ID 0x5A8B3C705 706#define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT 0x5A8B44707 708#define mmDMA5_QM_ARB_MSG_AWUSER_31_11 0x5A8B48709 710#define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP 0x5A8B4C711 712#define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5A8B50713 714#define mmDMA5_QM_ARB_BASE_LO 0x5A8B54715 716#define mmDMA5_QM_ARB_BASE_HI 0x5A8B58717 718#define mmDMA5_QM_ARB_STATE_STS 0x5A8B80719 720#define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS 0x5A8B84721 722#define mmDMA5_QM_ARB_MSG_STS 0x5A8B88723 724#define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD 0x5A8B8C725 726#define mmDMA5_QM_ARB_ERR_CAUSE 0x5A8B9C727 728#define mmDMA5_QM_ARB_ERR_MSG_EN 0x5A8BA0729 730#define mmDMA5_QM_ARB_ERR_STS_DRP 0x5A8BA8731 732#define mmDMA5_QM_ARB_MST_CRED_STS_0 0x5A8BB0733 734#define mmDMA5_QM_ARB_MST_CRED_STS_1 0x5A8BB4735 736#define mmDMA5_QM_ARB_MST_CRED_STS_2 0x5A8BB8737 738#define mmDMA5_QM_ARB_MST_CRED_STS_3 0x5A8BBC739 740#define mmDMA5_QM_ARB_MST_CRED_STS_4 0x5A8BC0741 742#define mmDMA5_QM_ARB_MST_CRED_STS_5 0x5A8BC4743 744#define mmDMA5_QM_ARB_MST_CRED_STS_6 0x5A8BC8745 746#define mmDMA5_QM_ARB_MST_CRED_STS_7 0x5A8BCC747 748#define mmDMA5_QM_ARB_MST_CRED_STS_8 0x5A8BD0749 750#define mmDMA5_QM_ARB_MST_CRED_STS_9 0x5A8BD4751 752#define mmDMA5_QM_ARB_MST_CRED_STS_10 0x5A8BD8753 754#define mmDMA5_QM_ARB_MST_CRED_STS_11 0x5A8BDC755 756#define mmDMA5_QM_ARB_MST_CRED_STS_12 0x5A8BE0757 758#define mmDMA5_QM_ARB_MST_CRED_STS_13 0x5A8BE4759 760#define mmDMA5_QM_ARB_MST_CRED_STS_14 0x5A8BE8761 762#define mmDMA5_QM_ARB_MST_CRED_STS_15 0x5A8BEC763 764#define mmDMA5_QM_ARB_MST_CRED_STS_16 0x5A8BF0765 766#define mmDMA5_QM_ARB_MST_CRED_STS_17 0x5A8BF4767 768#define mmDMA5_QM_ARB_MST_CRED_STS_18 0x5A8BF8769 770#define mmDMA5_QM_ARB_MST_CRED_STS_19 0x5A8BFC771 772#define mmDMA5_QM_ARB_MST_CRED_STS_20 0x5A8C00773 774#define mmDMA5_QM_ARB_MST_CRED_STS_21 0x5A8C04775 776#define mmDMA5_QM_ARB_MST_CRED_STS_22 0x5A8C08777 778#define mmDMA5_QM_ARB_MST_CRED_STS_23 0x5A8C0C779 780#define mmDMA5_QM_ARB_MST_CRED_STS_24 0x5A8C10781 782#define mmDMA5_QM_ARB_MST_CRED_STS_25 0x5A8C14783 784#define mmDMA5_QM_ARB_MST_CRED_STS_26 0x5A8C18785 786#define mmDMA5_QM_ARB_MST_CRED_STS_27 0x5A8C1C787 788#define mmDMA5_QM_ARB_MST_CRED_STS_28 0x5A8C20789 790#define mmDMA5_QM_ARB_MST_CRED_STS_29 0x5A8C24791 792#define mmDMA5_QM_ARB_MST_CRED_STS_30 0x5A8C28793 794#define mmDMA5_QM_ARB_MST_CRED_STS_31 0x5A8C2C795 796#define mmDMA5_QM_CGM_CFG 0x5A8C70797 798#define mmDMA5_QM_CGM_STS 0x5A8C74799 800#define mmDMA5_QM_CGM_CFG1 0x5A8C78801 802#define mmDMA5_QM_LOCAL_RANGE_BASE 0x5A8C80803 804#define mmDMA5_QM_LOCAL_RANGE_SIZE 0x5A8C84805 806#define mmDMA5_QM_CSMR_STRICT_PRIO_CFG 0x5A8C90807 808#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 0x5A8C94809 810#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 0x5A8C98811 812#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 0x5A8C9C813 814#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 0x5A8CA0815 816#define mmDMA5_QM_GLBL_AXCACHE 0x5A8CA4817 818#define mmDMA5_QM_IND_GW_APB_CFG 0x5A8CB0819 820#define mmDMA5_QM_IND_GW_APB_WDATA 0x5A8CB4821 822#define mmDMA5_QM_IND_GW_APB_RDATA 0x5A8CB8823 824#define mmDMA5_QM_IND_GW_APB_STATUS 0x5A8CBC825 826#define mmDMA5_QM_GLBL_ERR_ADDR_LO 0x5A8CD0827 828#define mmDMA5_QM_GLBL_ERR_ADDR_HI 0x5A8CD4829 830#define mmDMA5_QM_GLBL_ERR_WDATA 0x5A8CD8831 832#define mmDMA5_QM_GLBL_MEM_INIT_BUSY 0x5A8D00833 834#endif /* ASIC_REG_DMA5_QM_REGS_H_ */835