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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA6_QM_REGS_H_14#define ASIC_REG_DMA6_QM_REGS_H_15 16/*17 *****************************************18 * DMA6_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmDMA6_QM_GLBL_CFG0 0x5C800023 24#define mmDMA6_QM_GLBL_CFG1 0x5C800425 26#define mmDMA6_QM_GLBL_PROT 0x5C800827 28#define mmDMA6_QM_GLBL_ERR_CFG 0x5C800C29 30#define mmDMA6_QM_GLBL_SECURE_PROPS_0 0x5C801031 32#define mmDMA6_QM_GLBL_SECURE_PROPS_1 0x5C801433 34#define mmDMA6_QM_GLBL_SECURE_PROPS_2 0x5C801835 36#define mmDMA6_QM_GLBL_SECURE_PROPS_3 0x5C801C37 38#define mmDMA6_QM_GLBL_SECURE_PROPS_4 0x5C802039 40#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 0x5C802441 42#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 0x5C802843 44#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 0x5C802C45 46#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 0x5C803047 48#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 0x5C803449 50#define mmDMA6_QM_GLBL_STS0 0x5C803851 52#define mmDMA6_QM_GLBL_STS1_0 0x5C804053 54#define mmDMA6_QM_GLBL_STS1_1 0x5C804455 56#define mmDMA6_QM_GLBL_STS1_2 0x5C804857 58#define mmDMA6_QM_GLBL_STS1_3 0x5C804C59 60#define mmDMA6_QM_GLBL_STS1_4 0x5C805061 62#define mmDMA6_QM_GLBL_MSG_EN_0 0x5C805463 64#define mmDMA6_QM_GLBL_MSG_EN_1 0x5C805865 66#define mmDMA6_QM_GLBL_MSG_EN_2 0x5C805C67 68#define mmDMA6_QM_GLBL_MSG_EN_3 0x5C806069 70#define mmDMA6_QM_GLBL_MSG_EN_4 0x5C806871 72#define mmDMA6_QM_PQ_BASE_LO_0 0x5C807073 74#define mmDMA6_QM_PQ_BASE_LO_1 0x5C807475 76#define mmDMA6_QM_PQ_BASE_LO_2 0x5C807877 78#define mmDMA6_QM_PQ_BASE_LO_3 0x5C807C79 80#define mmDMA6_QM_PQ_BASE_HI_0 0x5C808081 82#define mmDMA6_QM_PQ_BASE_HI_1 0x5C808483 84#define mmDMA6_QM_PQ_BASE_HI_2 0x5C808885 86#define mmDMA6_QM_PQ_BASE_HI_3 0x5C808C87 88#define mmDMA6_QM_PQ_SIZE_0 0x5C809089 90#define mmDMA6_QM_PQ_SIZE_1 0x5C809491 92#define mmDMA6_QM_PQ_SIZE_2 0x5C809893 94#define mmDMA6_QM_PQ_SIZE_3 0x5C809C95 96#define mmDMA6_QM_PQ_PI_0 0x5C80A097 98#define mmDMA6_QM_PQ_PI_1 0x5C80A499 100#define mmDMA6_QM_PQ_PI_2 0x5C80A8101 102#define mmDMA6_QM_PQ_PI_3 0x5C80AC103 104#define mmDMA6_QM_PQ_CI_0 0x5C80B0105 106#define mmDMA6_QM_PQ_CI_1 0x5C80B4107 108#define mmDMA6_QM_PQ_CI_2 0x5C80B8109 110#define mmDMA6_QM_PQ_CI_3 0x5C80BC111 112#define mmDMA6_QM_PQ_CFG0_0 0x5C80C0113 114#define mmDMA6_QM_PQ_CFG0_1 0x5C80C4115 116#define mmDMA6_QM_PQ_CFG0_2 0x5C80C8117 118#define mmDMA6_QM_PQ_CFG0_3 0x5C80CC119 120#define mmDMA6_QM_PQ_CFG1_0 0x5C80D0121 122#define mmDMA6_QM_PQ_CFG1_1 0x5C80D4123 124#define mmDMA6_QM_PQ_CFG1_2 0x5C80D8125 126#define mmDMA6_QM_PQ_CFG1_3 0x5C80DC127 128#define mmDMA6_QM_PQ_ARUSER_31_11_0 0x5C80E0129 130#define mmDMA6_QM_PQ_ARUSER_31_11_1 0x5C80E4131 132#define mmDMA6_QM_PQ_ARUSER_31_11_2 0x5C80E8133 134#define mmDMA6_QM_PQ_ARUSER_31_11_3 0x5C80EC135 136#define mmDMA6_QM_PQ_STS0_0 0x5C80F0137 138#define mmDMA6_QM_PQ_STS0_1 0x5C80F4139 140#define mmDMA6_QM_PQ_STS0_2 0x5C80F8141 142#define mmDMA6_QM_PQ_STS0_3 0x5C80FC143 144#define mmDMA6_QM_PQ_STS1_0 0x5C8100145 146#define mmDMA6_QM_PQ_STS1_1 0x5C8104147 148#define mmDMA6_QM_PQ_STS1_2 0x5C8108149 150#define mmDMA6_QM_PQ_STS1_3 0x5C810C151 152#define mmDMA6_QM_CQ_CFG0_0 0x5C8110153 154#define mmDMA6_QM_CQ_CFG0_1 0x5C8114155 156#define mmDMA6_QM_CQ_CFG0_2 0x5C8118157 158#define mmDMA6_QM_CQ_CFG0_3 0x5C811C159 160#define mmDMA6_QM_CQ_CFG0_4 0x5C8120161 162#define mmDMA6_QM_CQ_CFG1_0 0x5C8124163 164#define mmDMA6_QM_CQ_CFG1_1 0x5C8128165 166#define mmDMA6_QM_CQ_CFG1_2 0x5C812C167 168#define mmDMA6_QM_CQ_CFG1_3 0x5C8130169 170#define mmDMA6_QM_CQ_CFG1_4 0x5C8134171 172#define mmDMA6_QM_CQ_ARUSER_31_11_0 0x5C8138173 174#define mmDMA6_QM_CQ_ARUSER_31_11_1 0x5C813C175 176#define mmDMA6_QM_CQ_ARUSER_31_11_2 0x5C8140177 178#define mmDMA6_QM_CQ_ARUSER_31_11_3 0x5C8144179 180#define mmDMA6_QM_CQ_ARUSER_31_11_4 0x5C8148181 182#define mmDMA6_QM_CQ_STS0_0 0x5C814C183 184#define mmDMA6_QM_CQ_STS0_1 0x5C8150185 186#define mmDMA6_QM_CQ_STS0_2 0x5C8154187 188#define mmDMA6_QM_CQ_STS0_3 0x5C8158189 190#define mmDMA6_QM_CQ_STS0_4 0x5C815C191 192#define mmDMA6_QM_CQ_STS1_0 0x5C8160193 194#define mmDMA6_QM_CQ_STS1_1 0x5C8164195 196#define mmDMA6_QM_CQ_STS1_2 0x5C8168197 198#define mmDMA6_QM_CQ_STS1_3 0x5C816C199 200#define mmDMA6_QM_CQ_STS1_4 0x5C8170201 202#define mmDMA6_QM_CQ_PTR_LO_0 0x5C8174203 204#define mmDMA6_QM_CQ_PTR_HI_0 0x5C8178205 206#define mmDMA6_QM_CQ_TSIZE_0 0x5C817C207 208#define mmDMA6_QM_CQ_CTL_0 0x5C8180209 210#define mmDMA6_QM_CQ_PTR_LO_1 0x5C8184211 212#define mmDMA6_QM_CQ_PTR_HI_1 0x5C8188213 214#define mmDMA6_QM_CQ_TSIZE_1 0x5C818C215 216#define mmDMA6_QM_CQ_CTL_1 0x5C8190217 218#define mmDMA6_QM_CQ_PTR_LO_2 0x5C8194219 220#define mmDMA6_QM_CQ_PTR_HI_2 0x5C8198221 222#define mmDMA6_QM_CQ_TSIZE_2 0x5C819C223 224#define mmDMA6_QM_CQ_CTL_2 0x5C81A0225 226#define mmDMA6_QM_CQ_PTR_LO_3 0x5C81A4227 228#define mmDMA6_QM_CQ_PTR_HI_3 0x5C81A8229 230#define mmDMA6_QM_CQ_TSIZE_3 0x5C81AC231 232#define mmDMA6_QM_CQ_CTL_3 0x5C81B0233 234#define mmDMA6_QM_CQ_PTR_LO_4 0x5C81B4235 236#define mmDMA6_QM_CQ_PTR_HI_4 0x5C81B8237 238#define mmDMA6_QM_CQ_TSIZE_4 0x5C81BC239 240#define mmDMA6_QM_CQ_CTL_4 0x5C81C0241 242#define mmDMA6_QM_CQ_PTR_LO_STS_0 0x5C81C4243 244#define mmDMA6_QM_CQ_PTR_LO_STS_1 0x5C81C8245 246#define mmDMA6_QM_CQ_PTR_LO_STS_2 0x5C81CC247 248#define mmDMA6_QM_CQ_PTR_LO_STS_3 0x5C81D0249 250#define mmDMA6_QM_CQ_PTR_LO_STS_4 0x5C81D4251 252#define mmDMA6_QM_CQ_PTR_HI_STS_0 0x5C81D8253 254#define mmDMA6_QM_CQ_PTR_HI_STS_1 0x5C81DC255 256#define mmDMA6_QM_CQ_PTR_HI_STS_2 0x5C81E0257 258#define mmDMA6_QM_CQ_PTR_HI_STS_3 0x5C81E4259 260#define mmDMA6_QM_CQ_PTR_HI_STS_4 0x5C81E8261 262#define mmDMA6_QM_CQ_TSIZE_STS_0 0x5C81EC263 264#define mmDMA6_QM_CQ_TSIZE_STS_1 0x5C81F0265 266#define mmDMA6_QM_CQ_TSIZE_STS_2 0x5C81F4267 268#define mmDMA6_QM_CQ_TSIZE_STS_3 0x5C81F8269 270#define mmDMA6_QM_CQ_TSIZE_STS_4 0x5C81FC271 272#define mmDMA6_QM_CQ_CTL_STS_0 0x5C8200273 274#define mmDMA6_QM_CQ_CTL_STS_1 0x5C8204275 276#define mmDMA6_QM_CQ_CTL_STS_2 0x5C8208277 278#define mmDMA6_QM_CQ_CTL_STS_3 0x5C820C279 280#define mmDMA6_QM_CQ_CTL_STS_4 0x5C8210281 282#define mmDMA6_QM_CQ_IFIFO_CNT_0 0x5C8214283 284#define mmDMA6_QM_CQ_IFIFO_CNT_1 0x5C8218285 286#define mmDMA6_QM_CQ_IFIFO_CNT_2 0x5C821C287 288#define mmDMA6_QM_CQ_IFIFO_CNT_3 0x5C8220289 290#define mmDMA6_QM_CQ_IFIFO_CNT_4 0x5C8224291 292#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 0x5C8228293 294#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 0x5C822C295 296#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 0x5C8230297 298#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 0x5C8234299 300#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 0x5C8238301 302#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 0x5C823C303 304#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 0x5C8240305 306#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 0x5C8244307 308#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 0x5C8248309 310#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 0x5C824C311 312#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 0x5C8250313 314#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 0x5C8254315 316#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 0x5C8258317 318#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 0x5C825C319 320#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 0x5C8260321 322#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 0x5C8264323 324#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 0x5C8268325 326#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 0x5C826C327 328#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 0x5C8270329 330#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 0x5C8274331 332#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 0x5C8278333 334#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 0x5C827C335 336#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 0x5C8280337 338#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 0x5C8284339 340#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 0x5C8288341 342#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 0x5C828C343 344#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 0x5C8290345 346#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 0x5C8294347 348#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 0x5C8298349 350#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 0x5C829C351 352#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 0x5C82A0353 354#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 0x5C82A4355 356#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 0x5C82A8357 358#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 0x5C82AC359 360#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 0x5C82B0361 362#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 0x5C82B4363 364#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 0x5C82B8365 366#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 0x5C82BC367 368#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 0x5C82C0369 370#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 0x5C82C4371 372#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 0x5C82C8373 374#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 0x5C82CC375 376#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 0x5C82D0377 378#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 0x5C82D4379 380#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 0x5C82D8381 382#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5C82E0383 384#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5C82E4385 386#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5C82E8387 388#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5C82EC389 390#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5C82F0391 392#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5C82F4393 394#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5C82F8395 396#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5C82FC397 398#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5C8300399 400#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5C8304401 402#define mmDMA6_QM_CP_FENCE0_RDATA_0 0x5C8308403 404#define mmDMA6_QM_CP_FENCE0_RDATA_1 0x5C830C405 406#define mmDMA6_QM_CP_FENCE0_RDATA_2 0x5C8310407 408#define mmDMA6_QM_CP_FENCE0_RDATA_3 0x5C8314409 410#define mmDMA6_QM_CP_FENCE0_RDATA_4 0x5C8318411 412#define mmDMA6_QM_CP_FENCE1_RDATA_0 0x5C831C413 414#define mmDMA6_QM_CP_FENCE1_RDATA_1 0x5C8320415 416#define mmDMA6_QM_CP_FENCE1_RDATA_2 0x5C8324417 418#define mmDMA6_QM_CP_FENCE1_RDATA_3 0x5C8328419 420#define mmDMA6_QM_CP_FENCE1_RDATA_4 0x5C832C421 422#define mmDMA6_QM_CP_FENCE2_RDATA_0 0x5C8330423 424#define mmDMA6_QM_CP_FENCE2_RDATA_1 0x5C8334425 426#define mmDMA6_QM_CP_FENCE2_RDATA_2 0x5C8338427 428#define mmDMA6_QM_CP_FENCE2_RDATA_3 0x5C833C429 430#define mmDMA6_QM_CP_FENCE2_RDATA_4 0x5C8340431 432#define mmDMA6_QM_CP_FENCE3_RDATA_0 0x5C8344433 434#define mmDMA6_QM_CP_FENCE3_RDATA_1 0x5C8348435 436#define mmDMA6_QM_CP_FENCE3_RDATA_2 0x5C834C437 438#define mmDMA6_QM_CP_FENCE3_RDATA_3 0x5C8350439 440#define mmDMA6_QM_CP_FENCE3_RDATA_4 0x5C8354441 442#define mmDMA6_QM_CP_FENCE0_CNT_0 0x5C8358443 444#define mmDMA6_QM_CP_FENCE0_CNT_1 0x5C835C445 446#define mmDMA6_QM_CP_FENCE0_CNT_2 0x5C8360447 448#define mmDMA6_QM_CP_FENCE0_CNT_3 0x5C8364449 450#define mmDMA6_QM_CP_FENCE0_CNT_4 0x5C8368451 452#define mmDMA6_QM_CP_FENCE1_CNT_0 0x5C836C453 454#define mmDMA6_QM_CP_FENCE1_CNT_1 0x5C8370455 456#define mmDMA6_QM_CP_FENCE1_CNT_2 0x5C8374457 458#define mmDMA6_QM_CP_FENCE1_CNT_3 0x5C8378459 460#define mmDMA6_QM_CP_FENCE1_CNT_4 0x5C837C461 462#define mmDMA6_QM_CP_FENCE2_CNT_0 0x5C8380463 464#define mmDMA6_QM_CP_FENCE2_CNT_1 0x5C8384465 466#define mmDMA6_QM_CP_FENCE2_CNT_2 0x5C8388467 468#define mmDMA6_QM_CP_FENCE2_CNT_3 0x5C838C469 470#define mmDMA6_QM_CP_FENCE2_CNT_4 0x5C8390471 472#define mmDMA6_QM_CP_FENCE3_CNT_0 0x5C8394473 474#define mmDMA6_QM_CP_FENCE3_CNT_1 0x5C8398475 476#define mmDMA6_QM_CP_FENCE3_CNT_2 0x5C839C477 478#define mmDMA6_QM_CP_FENCE3_CNT_3 0x5C83A0479 480#define mmDMA6_QM_CP_FENCE3_CNT_4 0x5C83A4481 482#define mmDMA6_QM_CP_STS_0 0x5C83A8483 484#define mmDMA6_QM_CP_STS_1 0x5C83AC485 486#define mmDMA6_QM_CP_STS_2 0x5C83B0487 488#define mmDMA6_QM_CP_STS_3 0x5C83B4489 490#define mmDMA6_QM_CP_STS_4 0x5C83B8491 492#define mmDMA6_QM_CP_CURRENT_INST_LO_0 0x5C83BC493 494#define mmDMA6_QM_CP_CURRENT_INST_LO_1 0x5C83C0495 496#define mmDMA6_QM_CP_CURRENT_INST_LO_2 0x5C83C4497 498#define mmDMA6_QM_CP_CURRENT_INST_LO_3 0x5C83C8499 500#define mmDMA6_QM_CP_CURRENT_INST_LO_4 0x5C83CC501 502#define mmDMA6_QM_CP_CURRENT_INST_HI_0 0x5C83D0503 504#define mmDMA6_QM_CP_CURRENT_INST_HI_1 0x5C83D4505 506#define mmDMA6_QM_CP_CURRENT_INST_HI_2 0x5C83D8507 508#define mmDMA6_QM_CP_CURRENT_INST_HI_3 0x5C83DC509 510#define mmDMA6_QM_CP_CURRENT_INST_HI_4 0x5C83E0511 512#define mmDMA6_QM_CP_BARRIER_CFG_0 0x5C83F4513 514#define mmDMA6_QM_CP_BARRIER_CFG_1 0x5C83F8515 516#define mmDMA6_QM_CP_BARRIER_CFG_2 0x5C83FC517 518#define mmDMA6_QM_CP_BARRIER_CFG_3 0x5C8400519 520#define mmDMA6_QM_CP_BARRIER_CFG_4 0x5C8404521 522#define mmDMA6_QM_CP_DBG_0_0 0x5C8408523 524#define mmDMA6_QM_CP_DBG_0_1 0x5C840C525 526#define mmDMA6_QM_CP_DBG_0_2 0x5C8410527 528#define mmDMA6_QM_CP_DBG_0_3 0x5C8414529 530#define mmDMA6_QM_CP_DBG_0_4 0x5C8418531 532#define mmDMA6_QM_CP_ARUSER_31_11_0 0x5C841C533 534#define mmDMA6_QM_CP_ARUSER_31_11_1 0x5C8420535 536#define mmDMA6_QM_CP_ARUSER_31_11_2 0x5C8424537 538#define mmDMA6_QM_CP_ARUSER_31_11_3 0x5C8428539 540#define mmDMA6_QM_CP_ARUSER_31_11_4 0x5C842C541 542#define mmDMA6_QM_CP_AWUSER_31_11_0 0x5C8430543 544#define mmDMA6_QM_CP_AWUSER_31_11_1 0x5C8434545 546#define mmDMA6_QM_CP_AWUSER_31_11_2 0x5C8438547 548#define mmDMA6_QM_CP_AWUSER_31_11_3 0x5C843C549 550#define mmDMA6_QM_CP_AWUSER_31_11_4 0x5C8440551 552#define mmDMA6_QM_ARB_CFG_0 0x5C8A00553 554#define mmDMA6_QM_ARB_CHOISE_Q_PUSH 0x5C8A04555 556#define mmDMA6_QM_ARB_WRR_WEIGHT_0 0x5C8A08557 558#define mmDMA6_QM_ARB_WRR_WEIGHT_1 0x5C8A0C559 560#define mmDMA6_QM_ARB_WRR_WEIGHT_2 0x5C8A10561 562#define mmDMA6_QM_ARB_WRR_WEIGHT_3 0x5C8A14563 564#define mmDMA6_QM_ARB_CFG_1 0x5C8A18565 566#define mmDMA6_QM_ARB_MST_AVAIL_CRED_0 0x5C8A20567 568#define mmDMA6_QM_ARB_MST_AVAIL_CRED_1 0x5C8A24569 570#define mmDMA6_QM_ARB_MST_AVAIL_CRED_2 0x5C8A28571 572#define mmDMA6_QM_ARB_MST_AVAIL_CRED_3 0x5C8A2C573 574#define mmDMA6_QM_ARB_MST_AVAIL_CRED_4 0x5C8A30575 576#define mmDMA6_QM_ARB_MST_AVAIL_CRED_5 0x5C8A34577 578#define mmDMA6_QM_ARB_MST_AVAIL_CRED_6 0x5C8A38579 580#define mmDMA6_QM_ARB_MST_AVAIL_CRED_7 0x5C8A3C581 582#define mmDMA6_QM_ARB_MST_AVAIL_CRED_8 0x5C8A40583 584#define mmDMA6_QM_ARB_MST_AVAIL_CRED_9 0x5C8A44585 586#define mmDMA6_QM_ARB_MST_AVAIL_CRED_10 0x5C8A48587 588#define mmDMA6_QM_ARB_MST_AVAIL_CRED_11 0x5C8A4C589 590#define mmDMA6_QM_ARB_MST_AVAIL_CRED_12 0x5C8A50591 592#define mmDMA6_QM_ARB_MST_AVAIL_CRED_13 0x5C8A54593 594#define mmDMA6_QM_ARB_MST_AVAIL_CRED_14 0x5C8A58595 596#define mmDMA6_QM_ARB_MST_AVAIL_CRED_15 0x5C8A5C597 598#define mmDMA6_QM_ARB_MST_AVAIL_CRED_16 0x5C8A60599 600#define mmDMA6_QM_ARB_MST_AVAIL_CRED_17 0x5C8A64601 602#define mmDMA6_QM_ARB_MST_AVAIL_CRED_18 0x5C8A68603 604#define mmDMA6_QM_ARB_MST_AVAIL_CRED_19 0x5C8A6C605 606#define mmDMA6_QM_ARB_MST_AVAIL_CRED_20 0x5C8A70607 608#define mmDMA6_QM_ARB_MST_AVAIL_CRED_21 0x5C8A74609 610#define mmDMA6_QM_ARB_MST_AVAIL_CRED_22 0x5C8A78611 612#define mmDMA6_QM_ARB_MST_AVAIL_CRED_23 0x5C8A7C613 614#define mmDMA6_QM_ARB_MST_AVAIL_CRED_24 0x5C8A80615 616#define mmDMA6_QM_ARB_MST_AVAIL_CRED_25 0x5C8A84617 618#define mmDMA6_QM_ARB_MST_AVAIL_CRED_26 0x5C8A88619 620#define mmDMA6_QM_ARB_MST_AVAIL_CRED_27 0x5C8A8C621 622#define mmDMA6_QM_ARB_MST_AVAIL_CRED_28 0x5C8A90623 624#define mmDMA6_QM_ARB_MST_AVAIL_CRED_29 0x5C8A94625 626#define mmDMA6_QM_ARB_MST_AVAIL_CRED_30 0x5C8A98627 628#define mmDMA6_QM_ARB_MST_AVAIL_CRED_31 0x5C8A9C629 630#define mmDMA6_QM_ARB_MST_CRED_INC 0x5C8AA0631 632#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5C8AA4633 634#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5C8AA8635 636#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5C8AAC637 638#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5C8AB0639 640#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5C8AB4641 642#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5C8AB8643 644#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5C8ABC645 646#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5C8AC0647 648#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5C8AC4649 650#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5C8AC8651 652#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5C8ACC653 654#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5C8AD0655 656#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5C8AD4657 658#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5C8AD8659 660#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5C8ADC661 662#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5C8AE0663 664#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5C8AE4665 666#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5C8AE8667 668#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5C8AEC669 670#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5C8AF0671 672#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5C8AF4673 674#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5C8AF8675 676#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5C8AFC677 678#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5C8B00679 680#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5C8B04681 682#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5C8B08683 684#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5C8B0C685 686#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5C8B10687 688#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5C8B14689 690#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5C8B18691 692#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5C8B1C693 694#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5C8B20695 696#define mmDMA6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5C8B28697 698#define mmDMA6_QM_ARB_MST_SLAVE_EN 0x5C8B2C699 700#define mmDMA6_QM_ARB_MST_QUIET_PER 0x5C8B34701 702#define mmDMA6_QM_ARB_SLV_CHOISE_WDT 0x5C8B38703 704#define mmDMA6_QM_ARB_SLV_ID 0x5C8B3C705 706#define mmDMA6_QM_ARB_MSG_MAX_INFLIGHT 0x5C8B44707 708#define mmDMA6_QM_ARB_MSG_AWUSER_31_11 0x5C8B48709 710#define mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP 0x5C8B4C711 712#define mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5C8B50713 714#define mmDMA6_QM_ARB_BASE_LO 0x5C8B54715 716#define mmDMA6_QM_ARB_BASE_HI 0x5C8B58717 718#define mmDMA6_QM_ARB_STATE_STS 0x5C8B80719 720#define mmDMA6_QM_ARB_CHOISE_FULLNESS_STS 0x5C8B84721 722#define mmDMA6_QM_ARB_MSG_STS 0x5C8B88723 724#define mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD 0x5C8B8C725 726#define mmDMA6_QM_ARB_ERR_CAUSE 0x5C8B9C727 728#define mmDMA6_QM_ARB_ERR_MSG_EN 0x5C8BA0729 730#define mmDMA6_QM_ARB_ERR_STS_DRP 0x5C8BA8731 732#define mmDMA6_QM_ARB_MST_CRED_STS_0 0x5C8BB0733 734#define mmDMA6_QM_ARB_MST_CRED_STS_1 0x5C8BB4735 736#define mmDMA6_QM_ARB_MST_CRED_STS_2 0x5C8BB8737 738#define mmDMA6_QM_ARB_MST_CRED_STS_3 0x5C8BBC739 740#define mmDMA6_QM_ARB_MST_CRED_STS_4 0x5C8BC0741 742#define mmDMA6_QM_ARB_MST_CRED_STS_5 0x5C8BC4743 744#define mmDMA6_QM_ARB_MST_CRED_STS_6 0x5C8BC8745 746#define mmDMA6_QM_ARB_MST_CRED_STS_7 0x5C8BCC747 748#define mmDMA6_QM_ARB_MST_CRED_STS_8 0x5C8BD0749 750#define mmDMA6_QM_ARB_MST_CRED_STS_9 0x5C8BD4751 752#define mmDMA6_QM_ARB_MST_CRED_STS_10 0x5C8BD8753 754#define mmDMA6_QM_ARB_MST_CRED_STS_11 0x5C8BDC755 756#define mmDMA6_QM_ARB_MST_CRED_STS_12 0x5C8BE0757 758#define mmDMA6_QM_ARB_MST_CRED_STS_13 0x5C8BE4759 760#define mmDMA6_QM_ARB_MST_CRED_STS_14 0x5C8BE8761 762#define mmDMA6_QM_ARB_MST_CRED_STS_15 0x5C8BEC763 764#define mmDMA6_QM_ARB_MST_CRED_STS_16 0x5C8BF0765 766#define mmDMA6_QM_ARB_MST_CRED_STS_17 0x5C8BF4767 768#define mmDMA6_QM_ARB_MST_CRED_STS_18 0x5C8BF8769 770#define mmDMA6_QM_ARB_MST_CRED_STS_19 0x5C8BFC771 772#define mmDMA6_QM_ARB_MST_CRED_STS_20 0x5C8C00773 774#define mmDMA6_QM_ARB_MST_CRED_STS_21 0x5C8C04775 776#define mmDMA6_QM_ARB_MST_CRED_STS_22 0x5C8C08777 778#define mmDMA6_QM_ARB_MST_CRED_STS_23 0x5C8C0C779 780#define mmDMA6_QM_ARB_MST_CRED_STS_24 0x5C8C10781 782#define mmDMA6_QM_ARB_MST_CRED_STS_25 0x5C8C14783 784#define mmDMA6_QM_ARB_MST_CRED_STS_26 0x5C8C18785 786#define mmDMA6_QM_ARB_MST_CRED_STS_27 0x5C8C1C787 788#define mmDMA6_QM_ARB_MST_CRED_STS_28 0x5C8C20789 790#define mmDMA6_QM_ARB_MST_CRED_STS_29 0x5C8C24791 792#define mmDMA6_QM_ARB_MST_CRED_STS_30 0x5C8C28793 794#define mmDMA6_QM_ARB_MST_CRED_STS_31 0x5C8C2C795 796#define mmDMA6_QM_CGM_CFG 0x5C8C70797 798#define mmDMA6_QM_CGM_STS 0x5C8C74799 800#define mmDMA6_QM_CGM_CFG1 0x5C8C78801 802#define mmDMA6_QM_LOCAL_RANGE_BASE 0x5C8C80803 804#define mmDMA6_QM_LOCAL_RANGE_SIZE 0x5C8C84805 806#define mmDMA6_QM_CSMR_STRICT_PRIO_CFG 0x5C8C90807 808#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 0x5C8C94809 810#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 0x5C8C98811 812#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 0x5C8C9C813 814#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 0x5C8CA0815 816#define mmDMA6_QM_GLBL_AXCACHE 0x5C8CA4817 818#define mmDMA6_QM_IND_GW_APB_CFG 0x5C8CB0819 820#define mmDMA6_QM_IND_GW_APB_WDATA 0x5C8CB4821 822#define mmDMA6_QM_IND_GW_APB_RDATA 0x5C8CB8823 824#define mmDMA6_QM_IND_GW_APB_STATUS 0x5C8CBC825 826#define mmDMA6_QM_GLBL_ERR_ADDR_LO 0x5C8CD0827 828#define mmDMA6_QM_GLBL_ERR_ADDR_HI 0x5C8CD4829 830#define mmDMA6_QM_GLBL_ERR_WDATA 0x5C8CD8831 832#define mmDMA6_QM_GLBL_MEM_INIT_BUSY 0x5C8D00833 834#endif /* ASIC_REG_DMA6_QM_REGS_H_ */835