brintos / linux-shallow public Read only

1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 **       DO NOT EDIT BELOW        **11 ************************************/12 13#ifndef GAUDI_BLOCKS_H_14#define GAUDI_BLOCKS_H_15 16#define mmNIC0_PHY0_BASE                           0x0ull17#define NIC0_PHY0_MAX_OFFSET                       0x9F1318#define mmMME0_ACC_BASE                            0x7FFC020000ull19#define MME0_ACC_MAX_OFFSET                        0x5C0020#define MME0_ACC_SECTION                           0x2000021#define mmMME0_SBAB_BASE                           0x7FFC040000ull22#define MME0_SBAB_MAX_OFFSET                       0x580023#define MME0_SBAB_SECTION                          0x100024#define mmMME0_PRTN_BASE                           0x7FFC041000ull25#define MME0_PRTN_MAX_OFFSET                       0x500026#define MME0_PRTN_SECTION                          0x1F00027#define mmMME0_CTRL_BASE                           0x7FFC060000ull28#define MME0_CTRL_MAX_OFFSET                       0xDA8029#define MME0_CTRL_SECTION                          0x800030#define mmARCH_MME0_CTRL_BASE                      0x7FFC060008ull31#define ARCH_MME0_CTRL_MAX_OFFSET                  0x340032#define ARCH_MME0_CTRL_SECTION                     0x340033#define mmARCH_TENSOR_S_MME0_CTRL_BASE             0x7FFC06003Cull34#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET         0x4C0035#define ARCH_TENSOR_S_MME0_CTRL_SECTION            0x4C0036#define mmARCH_AGU_S_MME0_CTRL_BASE                0x7FFC060088ull37#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET            0x240038#define ARCH_AGU_S_MME0_CTRL_SECTION               0x240039#define mmARCH_TENSOR_L_MME0_CTRL_BASE             0x7FFC0600ACull40#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET         0x4C0041#define ARCH_TENSOR_L_MME0_CTRL_SECTION            0x4C0042#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE          0x7FFC0600F8ull43#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET      0x240044#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION         0x240045#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE         0x7FFC06011Cull46#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET     0x240047#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION        0x240048#define mmARCH_TENSOR_O_MME0_CTRL_BASE             0x7FFC060140ull49#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET         0x4C0050#define ARCH_TENSOR_O_MME0_CTRL_SECTION            0x4C0051#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE          0x7FFC06018Cull52#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET      0x240053#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION         0x240054#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE         0x7FFC0601B0ull55#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET     0x240056#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION        0x240057#define mmARCH_DESC_MME0_CTRL_BASE                 0x7FFC0601D4ull58#define ARCH_DESC_MME0_CTRL_MAX_OFFSET             0x540059#define ARCH_DESC_MME0_CTRL_SECTION                0x234060#define mmSHADOW_0_MME0_CTRL_BASE                  0x7FFC060408ull61#define SHADOW_0_MME0_CTRL_MAX_OFFSET              0x340062#define SHADOW_0_MME0_CTRL_SECTION                 0x340063#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE         0x7FFC06043Cull64#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C0065#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION        0x4C0066#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE            0x7FFC060488ull67#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET        0x240068#define SHADOW_0_AGU_S_MME0_CTRL_SECTION           0x240069#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE         0x7FFC0604ACull70#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C0071#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION        0x4C0072#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC0604F8ull73#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x240074#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION     0x240075#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC06051Cull76#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x240077#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION    0x240078#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE         0x7FFC060540ull79#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C0080#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION        0x4C0081#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC06058Cull82#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x240083#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION     0x240084#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC0605B0ull85#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x240086#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION    0x240087#define mmSHADOW_0_DESC_MME0_CTRL_BASE             0x7FFC0605D4ull88#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET         0x540089#define SHADOW_0_DESC_MME0_CTRL_SECTION            0xB40090#define mmSHADOW_1_MME0_CTRL_BASE                  0x7FFC060688ull91#define SHADOW_1_MME0_CTRL_MAX_OFFSET              0x340092#define SHADOW_1_MME0_CTRL_SECTION                 0x340093#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE         0x7FFC0606BCull94#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C0095#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION        0x4C0096#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE            0x7FFC060708ull97#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET        0x240098#define SHADOW_1_AGU_S_MME0_CTRL_SECTION           0x240099#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE         0x7FFC06072Cull100#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00101#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION        0x4C00102#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC060778ull103#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400104#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION     0x2400105#define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC06079Cull106#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400107#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION    0x2400108#define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE         0x7FFC0607C0ull109#define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C00110#define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION        0x4C00111#define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC06080Cull112#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400113#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION     0x2400114#define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC060830ull115#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400116#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION    0x2400117#define mmSHADOW_1_DESC_MME0_CTRL_BASE             0x7FFC060854ull118#define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET         0x5400119#define SHADOW_1_DESC_MME0_CTRL_SECTION            0xB400120#define mmSHADOW_2_MME0_CTRL_BASE                  0x7FFC060908ull121#define SHADOW_2_MME0_CTRL_MAX_OFFSET              0x3400122#define SHADOW_2_MME0_CTRL_SECTION                 0x3400123#define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE         0x7FFC06093Cull124#define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C00125#define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION        0x4C00126#define mmSHADOW_2_AGU_S_MME0_CTRL_BASE            0x7FFC060988ull127#define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET        0x2400128#define SHADOW_2_AGU_S_MME0_CTRL_SECTION           0x2400129#define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE         0x7FFC0609ACull130#define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00131#define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION        0x4C00132#define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC0609F8ull133#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400134#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION     0x2400135#define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC060A1Cull136#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400137#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION    0x2400138#define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE         0x7FFC060A40ull139#define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C00140#define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION        0x4C00141#define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC060A8Cull142#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400143#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION     0x2400144#define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC060AB0ull145#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400146#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION    0x2400147#define mmSHADOW_2_DESC_MME0_CTRL_BASE             0x7FFC060AD4ull148#define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET         0x5400149#define SHADOW_2_DESC_MME0_CTRL_SECTION            0xB400150#define mmSHADOW_3_MME0_CTRL_BASE                  0x7FFC060B88ull151#define SHADOW_3_MME0_CTRL_MAX_OFFSET              0x3400152#define SHADOW_3_MME0_CTRL_SECTION                 0x3400153#define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE         0x7FFC060BBCull154#define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C00155#define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION        0x4C00156#define mmSHADOW_3_AGU_S_MME0_CTRL_BASE            0x7FFC060C08ull157#define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET        0x2400158#define SHADOW_3_AGU_S_MME0_CTRL_SECTION           0x2400159#define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE         0x7FFC060C2Cull160#define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00161#define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION        0x4C00162#define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC060C78ull163#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400164#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION     0x2400165#define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC060C9Cull166#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400167#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION    0x2400168#define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE         0x7FFC060CC0ull169#define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C00170#define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION        0x4C00171#define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC060D0Cull172#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400173#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION     0x2400174#define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC060D30ull175#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400176#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION    0x2400177#define mmSHADOW_3_DESC_MME0_CTRL_BASE             0x7FFC060D54ull178#define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET         0x5400179#define SHADOW_3_DESC_MME0_CTRL_SECTION            0x72AC180#define mmMME0_QM_BASE                             0x7FFC068000ull181#define MME0_QM_MAX_OFFSET                         0xD040182#define MME0_QM_SECTION                            0x38000183#define mmMME1_ACC_BASE                            0x7FFC0A0000ull184#define MME1_ACC_MAX_OFFSET                        0x5C00185#define MME1_ACC_SECTION                           0x20000186#define mmMME1_SBAB_BASE                           0x7FFC0C0000ull187#define MME1_SBAB_MAX_OFFSET                       0x5800188#define MME1_SBAB_SECTION                          0x1000189#define mmMME1_PRTN_BASE                           0x7FFC0C1000ull190#define MME1_PRTN_MAX_OFFSET                       0x5000191#define MME1_PRTN_SECTION                          0x1F000192#define mmMME1_CTRL_BASE                           0x7FFC0E0000ull193#define MME1_CTRL_MAX_OFFSET                       0xDA80194#define MME1_CTRL_SECTION                          0x8000195#define mmARCH_MME1_CTRL_BASE                      0x7FFC0E0008ull196#define ARCH_MME1_CTRL_MAX_OFFSET                  0x3400197#define ARCH_MME1_CTRL_SECTION                     0x3400198#define mmARCH_TENSOR_S_MME1_CTRL_BASE             0x7FFC0E003Cull199#define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET         0x4C00200#define ARCH_TENSOR_S_MME1_CTRL_SECTION            0x4C00201#define mmARCH_AGU_S_MME1_CTRL_BASE                0x7FFC0E0088ull202#define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET            0x2400203#define ARCH_AGU_S_MME1_CTRL_SECTION               0x2400204#define mmARCH_TENSOR_L_MME1_CTRL_BASE             0x7FFC0E00ACull205#define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET         0x4C00206#define ARCH_TENSOR_L_MME1_CTRL_SECTION            0x4C00207#define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE          0x7FFC0E00F8ull208#define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET      0x2400209#define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION         0x2400210#define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE         0x7FFC0E011Cull211#define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET     0x2400212#define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION        0x2400213#define mmARCH_TENSOR_O_MME1_CTRL_BASE             0x7FFC0E0140ull214#define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET         0x4C00215#define ARCH_TENSOR_O_MME1_CTRL_SECTION            0x4C00216#define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE          0x7FFC0E018Cull217#define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET      0x2400218#define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION         0x2400219#define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE         0x7FFC0E01B0ull220#define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET     0x2400221#define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION        0x2400222#define mmARCH_DESC_MME1_CTRL_BASE                 0x7FFC0E01D4ull223#define ARCH_DESC_MME1_CTRL_MAX_OFFSET             0x5400224#define ARCH_DESC_MME1_CTRL_SECTION                0x2340225#define mmSHADOW_0_MME1_CTRL_BASE                  0x7FFC0E0408ull226#define SHADOW_0_MME1_CTRL_MAX_OFFSET              0x3400227#define SHADOW_0_MME1_CTRL_SECTION                 0x3400228#define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE         0x7FFC0E043Cull229#define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET     0x4C00230#define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION        0x4C00231#define mmSHADOW_0_AGU_S_MME1_CTRL_BASE            0x7FFC0E0488ull232#define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET        0x2400233#define SHADOW_0_AGU_S_MME1_CTRL_SECTION           0x2400234#define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE         0x7FFC0E04ACull235#define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET     0x4C00236#define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION        0x4C00237#define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE      0x7FFC0E04F8ull238#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400239#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION     0x2400240#define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE     0x7FFC0E051Cull241#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400242#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION    0x2400243#define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE         0x7FFC0E0540ull244#define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET     0x4C00245#define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION        0x4C00246#define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE      0x7FFC0E058Cull247#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400248#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION     0x2400249#define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE     0x7FFC0E05B0ull250#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400251#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION    0x2400252#define mmSHADOW_0_DESC_MME1_CTRL_BASE             0x7FFC0E05D4ull253#define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET         0x5400254#define SHADOW_0_DESC_MME1_CTRL_SECTION            0xB400255#define mmSHADOW_1_MME1_CTRL_BASE                  0x7FFC0E0688ull256#define SHADOW_1_MME1_CTRL_MAX_OFFSET              0x3400257#define SHADOW_1_MME1_CTRL_SECTION                 0x3400258#define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE         0x7FFC0E06BCull259#define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET     0x4C00260#define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION        0x4C00261#define mmSHADOW_1_AGU_S_MME1_CTRL_BASE            0x7FFC0E0708ull262#define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET        0x2400263#define SHADOW_1_AGU_S_MME1_CTRL_SECTION           0x2400264#define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE         0x7FFC0E072Cull265#define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET     0x4C00266#define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION        0x4C00267#define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE      0x7FFC0E0778ull268#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400269#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION     0x2400270#define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE     0x7FFC0E079Cull271#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400272#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION    0x2400273#define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE         0x7FFC0E07C0ull274#define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET     0x4C00275#define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION        0x4C00276#define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE      0x7FFC0E080Cull277#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400278#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION     0x2400279#define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE     0x7FFC0E0830ull280#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400281#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION    0x2400282#define mmSHADOW_1_DESC_MME1_CTRL_BASE             0x7FFC0E0854ull283#define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET         0x5400284#define SHADOW_1_DESC_MME1_CTRL_SECTION            0xB400285#define mmSHADOW_2_MME1_CTRL_BASE                  0x7FFC0E0908ull286#define SHADOW_2_MME1_CTRL_MAX_OFFSET              0x3400287#define SHADOW_2_MME1_CTRL_SECTION                 0x3400288#define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE         0x7FFC0E093Cull289#define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET     0x4C00290#define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION        0x4C00291#define mmSHADOW_2_AGU_S_MME1_CTRL_BASE            0x7FFC0E0988ull292#define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET        0x2400293#define SHADOW_2_AGU_S_MME1_CTRL_SECTION           0x2400294#define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE         0x7FFC0E09ACull295#define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET     0x4C00296#define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION        0x4C00297#define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE      0x7FFC0E09F8ull298#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400299#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION     0x2400300#define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE     0x7FFC0E0A1Cull301#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400302#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION    0x2400303#define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE         0x7FFC0E0A40ull304#define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET     0x4C00305#define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION        0x4C00306#define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE      0x7FFC0E0A8Cull307#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400308#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION     0x2400309#define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE     0x7FFC0E0AB0ull310#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400311#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION    0x2400312#define mmSHADOW_2_DESC_MME1_CTRL_BASE             0x7FFC0E0AD4ull313#define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET         0x5400314#define SHADOW_2_DESC_MME1_CTRL_SECTION            0xB400315#define mmSHADOW_3_MME1_CTRL_BASE                  0x7FFC0E0B88ull316#define SHADOW_3_MME1_CTRL_MAX_OFFSET              0x3400317#define SHADOW_3_MME1_CTRL_SECTION                 0x3400318#define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE         0x7FFC0E0BBCull319#define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET     0x4C00320#define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION        0x4C00321#define mmSHADOW_3_AGU_S_MME1_CTRL_BASE            0x7FFC0E0C08ull322#define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET        0x2400323#define SHADOW_3_AGU_S_MME1_CTRL_SECTION           0x2400324#define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE         0x7FFC0E0C2Cull325#define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET     0x4C00326#define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION        0x4C00327#define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE      0x7FFC0E0C78ull328#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400329#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION     0x2400330#define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE     0x7FFC0E0C9Cull331#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400332#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION    0x2400333#define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE         0x7FFC0E0CC0ull334#define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET     0x4C00335#define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION        0x4C00336#define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE      0x7FFC0E0D0Cull337#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET  0x2400338#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION     0x2400339#define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE     0x7FFC0E0D30ull340#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400341#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION    0x2400342#define mmSHADOW_3_DESC_MME1_CTRL_BASE             0x7FFC0E0D54ull343#define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET         0x5400344#define SHADOW_3_DESC_MME1_CTRL_SECTION            0x72AC345#define mmMME1_QM_BASE                             0x7FFC0E8000ull346#define MME1_QM_MAX_OFFSET                         0xD040347#define MME1_QM_SECTION                            0x38000348#define mmMME2_ACC_BASE                            0x7FFC120000ull349#define MME2_ACC_MAX_OFFSET                        0x5C00350#define MME2_ACC_SECTION                           0x20000351#define mmMME2_SBAB_BASE                           0x7FFC140000ull352#define MME2_SBAB_MAX_OFFSET                       0x5800353#define MME2_SBAB_SECTION                          0x1000354#define mmMME2_PRTN_BASE                           0x7FFC141000ull355#define MME2_PRTN_MAX_OFFSET                       0x5000356#define MME2_PRTN_SECTION                          0x1F000357#define mmMME2_CTRL_BASE                           0x7FFC160000ull358#define MME2_CTRL_MAX_OFFSET                       0xDA80359#define MME2_CTRL_SECTION                          0x8000360#define mmARCH_MME2_CTRL_BASE                      0x7FFC160008ull361#define ARCH_MME2_CTRL_MAX_OFFSET                  0x3400362#define ARCH_MME2_CTRL_SECTION                     0x3400363#define mmARCH_TENSOR_S_MME2_CTRL_BASE             0x7FFC16003Cull364#define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET         0x4C00365#define ARCH_TENSOR_S_MME2_CTRL_SECTION            0x4C00366#define mmARCH_AGU_S_MME2_CTRL_BASE                0x7FFC160088ull367#define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET            0x2400368#define ARCH_AGU_S_MME2_CTRL_SECTION               0x2400369#define mmARCH_TENSOR_L_MME2_CTRL_BASE             0x7FFC1600ACull370#define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET         0x4C00371#define ARCH_TENSOR_L_MME2_CTRL_SECTION            0x4C00372#define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE          0x7FFC1600F8ull373#define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET      0x2400374#define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION         0x2400375#define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE         0x7FFC16011Cull376#define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET     0x2400377#define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION        0x2400378#define mmARCH_TENSOR_O_MME2_CTRL_BASE             0x7FFC160140ull379#define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET         0x4C00380#define ARCH_TENSOR_O_MME2_CTRL_SECTION            0x4C00381#define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE          0x7FFC16018Cull382#define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET      0x2400383#define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION         0x2400384#define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE         0x7FFC1601B0ull385#define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET     0x2400386#define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION        0x2400387#define mmARCH_DESC_MME2_CTRL_BASE                 0x7FFC1601D4ull388#define ARCH_DESC_MME2_CTRL_MAX_OFFSET             0x5400389#define ARCH_DESC_MME2_CTRL_SECTION                0x2340390#define mmSHADOW_0_MME2_CTRL_BASE                  0x7FFC160408ull391#define SHADOW_0_MME2_CTRL_MAX_OFFSET              0x3400392#define SHADOW_0_MME2_CTRL_SECTION                 0x3400393#define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE         0x7FFC16043Cull394#define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET     0x4C00395#define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION        0x4C00396#define mmSHADOW_0_AGU_S_MME2_CTRL_BASE            0x7FFC160488ull397#define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET        0x2400398#define SHADOW_0_AGU_S_MME2_CTRL_SECTION           0x2400399#define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE         0x7FFC1604ACull400#define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET     0x4C00401#define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION        0x4C00402#define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE      0x7FFC1604F8ull403#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400404#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION     0x2400405#define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE     0x7FFC16051Cull406#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400407#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION    0x2400408#define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE         0x7FFC160540ull409#define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET     0x4C00410#define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION        0x4C00411#define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE      0x7FFC16058Cull412#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400413#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION     0x2400414#define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE     0x7FFC1605B0ull415#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400416#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION    0x2400417#define mmSHADOW_0_DESC_MME2_CTRL_BASE             0x7FFC1605D4ull418#define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET         0x5400419#define SHADOW_0_DESC_MME2_CTRL_SECTION            0xB400420#define mmSHADOW_1_MME2_CTRL_BASE                  0x7FFC160688ull421#define SHADOW_1_MME2_CTRL_MAX_OFFSET              0x3400422#define SHADOW_1_MME2_CTRL_SECTION                 0x3400423#define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE         0x7FFC1606BCull424#define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET     0x4C00425#define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION        0x4C00426#define mmSHADOW_1_AGU_S_MME2_CTRL_BASE            0x7FFC160708ull427#define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET        0x2400428#define SHADOW_1_AGU_S_MME2_CTRL_SECTION           0x2400429#define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE         0x7FFC16072Cull430#define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET     0x4C00431#define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION        0x4C00432#define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE      0x7FFC160778ull433#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400434#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION     0x2400435#define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE     0x7FFC16079Cull436#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400437#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION    0x2400438#define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE         0x7FFC1607C0ull439#define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET     0x4C00440#define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION        0x4C00441#define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE      0x7FFC16080Cull442#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400443#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION     0x2400444#define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE     0x7FFC160830ull445#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400446#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION    0x2400447#define mmSHADOW_1_DESC_MME2_CTRL_BASE             0x7FFC160854ull448#define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET         0x5400449#define SHADOW_1_DESC_MME2_CTRL_SECTION            0xB400450#define mmSHADOW_2_MME2_CTRL_BASE                  0x7FFC160908ull451#define SHADOW_2_MME2_CTRL_MAX_OFFSET              0x3400452#define SHADOW_2_MME2_CTRL_SECTION                 0x3400453#define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE         0x7FFC16093Cull454#define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET     0x4C00455#define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION        0x4C00456#define mmSHADOW_2_AGU_S_MME2_CTRL_BASE            0x7FFC160988ull457#define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET        0x2400458#define SHADOW_2_AGU_S_MME2_CTRL_SECTION           0x2400459#define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE         0x7FFC1609ACull460#define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET     0x4C00461#define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION        0x4C00462#define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE      0x7FFC1609F8ull463#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400464#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION     0x2400465#define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE     0x7FFC160A1Cull466#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400467#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION    0x2400468#define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE         0x7FFC160A40ull469#define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET     0x4C00470#define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION        0x4C00471#define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE      0x7FFC160A8Cull472#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400473#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION     0x2400474#define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE     0x7FFC160AB0ull475#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400476#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION    0x2400477#define mmSHADOW_2_DESC_MME2_CTRL_BASE             0x7FFC160AD4ull478#define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET         0x5400479#define SHADOW_2_DESC_MME2_CTRL_SECTION            0xB400480#define mmSHADOW_3_MME2_CTRL_BASE                  0x7FFC160B88ull481#define SHADOW_3_MME2_CTRL_MAX_OFFSET              0x3400482#define SHADOW_3_MME2_CTRL_SECTION                 0x3400483#define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE         0x7FFC160BBCull484#define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET     0x4C00485#define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION        0x4C00486#define mmSHADOW_3_AGU_S_MME2_CTRL_BASE            0x7FFC160C08ull487#define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET        0x2400488#define SHADOW_3_AGU_S_MME2_CTRL_SECTION           0x2400489#define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE         0x7FFC160C2Cull490#define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET     0x4C00491#define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION        0x4C00492#define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE      0x7FFC160C78ull493#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400494#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION     0x2400495#define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE     0x7FFC160C9Cull496#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400497#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION    0x2400498#define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE         0x7FFC160CC0ull499#define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET     0x4C00500#define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION        0x4C00501#define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE      0x7FFC160D0Cull502#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET  0x2400503#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION     0x2400504#define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE     0x7FFC160D30ull505#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400506#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION    0x2400507#define mmSHADOW_3_DESC_MME2_CTRL_BASE             0x7FFC160D54ull508#define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET         0x5400509#define SHADOW_3_DESC_MME2_CTRL_SECTION            0x72AC510#define mmMME2_QM_BASE                             0x7FFC168000ull511#define MME2_QM_MAX_OFFSET                         0xD040512#define MME2_QM_SECTION                            0x38000513#define mmMME3_ACC_BASE                            0x7FFC1A0000ull514#define MME3_ACC_MAX_OFFSET                        0x5C00515#define MME3_ACC_SECTION                           0x20000516#define mmMME3_SBAB_BASE                           0x7FFC1C0000ull517#define MME3_SBAB_MAX_OFFSET                       0x5800518#define MME3_SBAB_SECTION                          0x1000519#define mmMME3_PRTN_BASE                           0x7FFC1C1000ull520#define MME3_PRTN_MAX_OFFSET                       0x5000521#define MME3_PRTN_SECTION                          0x1F000522#define mmMME3_CTRL_BASE                           0x7FFC1E0000ull523#define MME3_CTRL_MAX_OFFSET                       0xDA80524#define MME3_CTRL_SECTION                          0x8000525#define mmARCH_MME3_CTRL_BASE                      0x7FFC1E0008ull526#define ARCH_MME3_CTRL_MAX_OFFSET                  0x3400527#define ARCH_MME3_CTRL_SECTION                     0x3400528#define mmARCH_TENSOR_S_MME3_CTRL_BASE             0x7FFC1E003Cull529#define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET         0x4C00530#define ARCH_TENSOR_S_MME3_CTRL_SECTION            0x4C00531#define mmARCH_AGU_S_MME3_CTRL_BASE                0x7FFC1E0088ull532#define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET            0x2400533#define ARCH_AGU_S_MME3_CTRL_SECTION               0x2400534#define mmARCH_TENSOR_L_MME3_CTRL_BASE             0x7FFC1E00ACull535#define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET         0x4C00536#define ARCH_TENSOR_L_MME3_CTRL_SECTION            0x4C00537#define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE          0x7FFC1E00F8ull538#define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET      0x2400539#define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION         0x2400540#define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE         0x7FFC1E011Cull541#define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET     0x2400542#define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION        0x2400543#define mmARCH_TENSOR_O_MME3_CTRL_BASE             0x7FFC1E0140ull544#define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET         0x4C00545#define ARCH_TENSOR_O_MME3_CTRL_SECTION            0x4C00546#define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE          0x7FFC1E018Cull547#define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET      0x2400548#define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION         0x2400549#define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE         0x7FFC1E01B0ull550#define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET     0x2400551#define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION        0x2400552#define mmARCH_DESC_MME3_CTRL_BASE                 0x7FFC1E01D4ull553#define ARCH_DESC_MME3_CTRL_MAX_OFFSET             0x5400554#define ARCH_DESC_MME3_CTRL_SECTION                0x2340555#define mmSHADOW_0_MME3_CTRL_BASE                  0x7FFC1E0408ull556#define SHADOW_0_MME3_CTRL_MAX_OFFSET              0x3400557#define SHADOW_0_MME3_CTRL_SECTION                 0x3400558#define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE         0x7FFC1E043Cull559#define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET     0x4C00560#define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION        0x4C00561#define mmSHADOW_0_AGU_S_MME3_CTRL_BASE            0x7FFC1E0488ull562#define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET        0x2400563#define SHADOW_0_AGU_S_MME3_CTRL_SECTION           0x2400564#define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE         0x7FFC1E04ACull565#define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET     0x4C00566#define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION        0x4C00567#define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE      0x7FFC1E04F8ull568#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400569#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION     0x2400570#define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE     0x7FFC1E051Cull571#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400572#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION    0x2400573#define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE         0x7FFC1E0540ull574#define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET     0x4C00575#define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION        0x4C00576#define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE      0x7FFC1E058Cull577#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400578#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION     0x2400579#define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE     0x7FFC1E05B0ull580#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400581#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION    0x2400582#define mmSHADOW_0_DESC_MME3_CTRL_BASE             0x7FFC1E05D4ull583#define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET         0x5400584#define SHADOW_0_DESC_MME3_CTRL_SECTION            0xB400585#define mmSHADOW_1_MME3_CTRL_BASE                  0x7FFC1E0688ull586#define SHADOW_1_MME3_CTRL_MAX_OFFSET              0x3400587#define SHADOW_1_MME3_CTRL_SECTION                 0x3400588#define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE         0x7FFC1E06BCull589#define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET     0x4C00590#define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION        0x4C00591#define mmSHADOW_1_AGU_S_MME3_CTRL_BASE            0x7FFC1E0708ull592#define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET        0x2400593#define SHADOW_1_AGU_S_MME3_CTRL_SECTION           0x2400594#define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE         0x7FFC1E072Cull595#define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET     0x4C00596#define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION        0x4C00597#define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE      0x7FFC1E0778ull598#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400599#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION     0x2400600#define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE     0x7FFC1E079Cull601#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400602#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION    0x2400603#define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE         0x7FFC1E07C0ull604#define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET     0x4C00605#define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION        0x4C00606#define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE      0x7FFC1E080Cull607#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400608#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION     0x2400609#define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE     0x7FFC1E0830ull610#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400611#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION    0x2400612#define mmSHADOW_1_DESC_MME3_CTRL_BASE             0x7FFC1E0854ull613#define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET         0x5400614#define SHADOW_1_DESC_MME3_CTRL_SECTION            0xB400615#define mmSHADOW_2_MME3_CTRL_BASE                  0x7FFC1E0908ull616#define SHADOW_2_MME3_CTRL_MAX_OFFSET              0x3400617#define SHADOW_2_MME3_CTRL_SECTION                 0x3400618#define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE         0x7FFC1E093Cull619#define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET     0x4C00620#define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION        0x4C00621#define mmSHADOW_2_AGU_S_MME3_CTRL_BASE            0x7FFC1E0988ull622#define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET        0x2400623#define SHADOW_2_AGU_S_MME3_CTRL_SECTION           0x2400624#define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE         0x7FFC1E09ACull625#define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET     0x4C00626#define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION        0x4C00627#define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE      0x7FFC1E09F8ull628#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400629#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION     0x2400630#define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE     0x7FFC1E0A1Cull631#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400632#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION    0x2400633#define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE         0x7FFC1E0A40ull634#define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET     0x4C00635#define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION        0x4C00636#define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE      0x7FFC1E0A8Cull637#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400638#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION     0x2400639#define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE     0x7FFC1E0AB0ull640#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400641#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION    0x2400642#define mmSHADOW_2_DESC_MME3_CTRL_BASE             0x7FFC1E0AD4ull643#define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET         0x5400644#define SHADOW_2_DESC_MME3_CTRL_SECTION            0xB400645#define mmSHADOW_3_MME3_CTRL_BASE                  0x7FFC1E0B88ull646#define SHADOW_3_MME3_CTRL_MAX_OFFSET              0x3400647#define SHADOW_3_MME3_CTRL_SECTION                 0x3400648#define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE         0x7FFC1E0BBCull649#define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET     0x4C00650#define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION        0x4C00651#define mmSHADOW_3_AGU_S_MME3_CTRL_BASE            0x7FFC1E0C08ull652#define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET        0x2400653#define SHADOW_3_AGU_S_MME3_CTRL_SECTION           0x2400654#define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE         0x7FFC1E0C2Cull655#define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET     0x4C00656#define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION        0x4C00657#define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE      0x7FFC1E0C78ull658#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400659#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION     0x2400660#define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE     0x7FFC1E0C9Cull661#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400662#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION    0x2400663#define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE         0x7FFC1E0CC0ull664#define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET     0x4C00665#define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION        0x4C00666#define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE      0x7FFC1E0D0Cull667#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET  0x2400668#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION     0x2400669#define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE     0x7FFC1E0D30ull670#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400671#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION    0x2400672#define mmSHADOW_3_DESC_MME3_CTRL_BASE             0x7FFC1E0D54ull673#define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET         0x5400674#define SHADOW_3_DESC_MME3_CTRL_SECTION            0x72AC675#define mmMME3_QM_BASE                             0x7FFC1E8000ull676#define MME3_QM_MAX_OFFSET                         0xD040677#define MME3_QM_SECTION                            0x18000678#define mmSRAM_Y0_X0_BANK_BASE                     0x7FFC200000ull679#define SRAM_Y0_X0_BANK_MAX_OFFSET                 0x4000680#define SRAM_Y0_X0_BANK_SECTION                    0x1000681#define mmSRAM_Y0_X0_RTR_BASE                      0x7FFC201000ull682#define SRAM_Y0_X0_RTR_MAX_OFFSET                  0x3340683#define SRAM_Y0_X0_RTR_SECTION                     0x7000684#define mmSRAM_Y0_X1_BANK_BASE                     0x7FFC208000ull685#define SRAM_Y0_X1_BANK_MAX_OFFSET                 0x4000686#define SRAM_Y0_X1_BANK_SECTION                    0x1000687#define mmSRAM_Y0_X1_RTR_BASE                      0x7FFC209000ull688#define SRAM_Y0_X1_RTR_MAX_OFFSET                  0x3340689#define SRAM_Y0_X1_RTR_SECTION                     0x7000690#define mmSRAM_Y0_X2_BANK_BASE                     0x7FFC210000ull691#define SRAM_Y0_X2_BANK_MAX_OFFSET                 0x4000692#define SRAM_Y0_X2_BANK_SECTION                    0x1000693#define mmSRAM_Y0_X2_RTR_BASE                      0x7FFC211000ull694#define SRAM_Y0_X2_RTR_MAX_OFFSET                  0x3340695#define SRAM_Y0_X2_RTR_SECTION                     0x7000696#define mmSRAM_Y0_X3_BANK_BASE                     0x7FFC218000ull697#define SRAM_Y0_X3_BANK_MAX_OFFSET                 0x4000698#define SRAM_Y0_X3_BANK_SECTION                    0x1000699#define mmSRAM_Y0_X3_RTR_BASE                      0x7FFC219000ull700#define SRAM_Y0_X3_RTR_MAX_OFFSET                  0x3340701#define SRAM_Y0_X3_RTR_SECTION                     0x7000702#define mmSRAM_Y0_X4_BANK_BASE                     0x7FFC220000ull703#define SRAM_Y0_X4_BANK_MAX_OFFSET                 0x4000704#define SRAM_Y0_X4_BANK_SECTION                    0x1000705#define mmSRAM_Y0_X4_RTR_BASE                      0x7FFC221000ull706#define SRAM_Y0_X4_RTR_MAX_OFFSET                  0x3340707#define SRAM_Y0_X4_RTR_SECTION                     0x7000708#define mmSRAM_Y0_X5_BANK_BASE                     0x7FFC228000ull709#define SRAM_Y0_X5_BANK_MAX_OFFSET                 0x4000710#define SRAM_Y0_X5_BANK_SECTION                    0x1000711#define mmSRAM_Y0_X5_RTR_BASE                      0x7FFC229000ull712#define SRAM_Y0_X5_RTR_MAX_OFFSET                  0x3340713#define SRAM_Y0_X5_RTR_SECTION                     0x7000714#define mmSRAM_Y0_X6_BANK_BASE                     0x7FFC230000ull715#define SRAM_Y0_X6_BANK_MAX_OFFSET                 0x4000716#define SRAM_Y0_X6_BANK_SECTION                    0x1000717#define mmSRAM_Y0_X6_RTR_BASE                      0x7FFC231000ull718#define SRAM_Y0_X6_RTR_MAX_OFFSET                  0x3340719#define SRAM_Y0_X6_RTR_SECTION                     0x7000720#define mmSRAM_Y0_X7_BANK_BASE                     0x7FFC238000ull721#define SRAM_Y0_X7_BANK_MAX_OFFSET                 0x4000722#define SRAM_Y0_X7_BANK_SECTION                    0x1000723#define mmSRAM_Y0_X7_RTR_BASE                      0x7FFC239000ull724#define SRAM_Y0_X7_RTR_MAX_OFFSET                  0x3340725#define SRAM_Y0_X7_RTR_SECTION                     0x7000726#define mmSRAM_Y1_X0_BANK_BASE                     0x7FFC240000ull727#define SRAM_Y1_X0_BANK_MAX_OFFSET                 0x4000728#define SRAM_Y1_X0_BANK_SECTION                    0x1000729#define mmSRAM_Y1_X0_RTR_BASE                      0x7FFC241000ull730#define SRAM_Y1_X0_RTR_MAX_OFFSET                  0x3340731#define SRAM_Y1_X0_RTR_SECTION                     0x7000732#define mmSRAM_Y1_X1_BANK_BASE                     0x7FFC248000ull733#define SRAM_Y1_X1_BANK_MAX_OFFSET                 0x4000734#define SRAM_Y1_X1_BANK_SECTION                    0x1000735#define mmSRAM_Y1_X1_RTR_BASE                      0x7FFC249000ull736#define SRAM_Y1_X1_RTR_MAX_OFFSET                  0x3340737#define SRAM_Y1_X1_RTR_SECTION                     0x7000738#define mmSRAM_Y1_X2_BANK_BASE                     0x7FFC250000ull739#define SRAM_Y1_X2_BANK_MAX_OFFSET                 0x4000740#define SRAM_Y1_X2_BANK_SECTION                    0x1000741#define mmSRAM_Y1_X2_RTR_BASE                      0x7FFC251000ull742#define SRAM_Y1_X2_RTR_MAX_OFFSET                  0x3340743#define SRAM_Y1_X2_RTR_SECTION                     0x7000744#define mmSRAM_Y1_X3_BANK_BASE                     0x7FFC258000ull745#define SRAM_Y1_X3_BANK_MAX_OFFSET                 0x4000746#define SRAM_Y1_X3_BANK_SECTION                    0x1000747#define mmSRAM_Y1_X3_RTR_BASE                      0x7FFC259000ull748#define SRAM_Y1_X3_RTR_MAX_OFFSET                  0x3340749#define SRAM_Y1_X3_RTR_SECTION                     0x7000750#define mmSRAM_Y1_X4_BANK_BASE                     0x7FFC260000ull751#define SRAM_Y1_X4_BANK_MAX_OFFSET                 0x4000752#define SRAM_Y1_X4_BANK_SECTION                    0x1000753#define mmSRAM_Y1_X4_RTR_BASE                      0x7FFC261000ull754#define SRAM_Y1_X4_RTR_MAX_OFFSET                  0x3340755#define SRAM_Y1_X4_RTR_SECTION                     0x7000756#define mmSRAM_Y1_X5_BANK_BASE                     0x7FFC268000ull757#define SRAM_Y1_X5_BANK_MAX_OFFSET                 0x4000758#define SRAM_Y1_X5_BANK_SECTION                    0x1000759#define mmSRAM_Y1_X5_RTR_BASE                      0x7FFC269000ull760#define SRAM_Y1_X5_RTR_MAX_OFFSET                  0x3340761#define SRAM_Y1_X5_RTR_SECTION                     0x7000762#define mmSRAM_Y1_X6_BANK_BASE                     0x7FFC270000ull763#define SRAM_Y1_X6_BANK_MAX_OFFSET                 0x4000764#define SRAM_Y1_X6_BANK_SECTION                    0x1000765#define mmSRAM_Y1_X6_RTR_BASE                      0x7FFC271000ull766#define SRAM_Y1_X6_RTR_MAX_OFFSET                  0x3340767#define SRAM_Y1_X6_RTR_SECTION                     0x7000768#define mmSRAM_Y1_X7_BANK_BASE                     0x7FFC278000ull769#define SRAM_Y1_X7_BANK_MAX_OFFSET                 0x4000770#define SRAM_Y1_X7_BANK_SECTION                    0x1000771#define mmSRAM_Y1_X7_RTR_BASE                      0x7FFC279000ull772#define SRAM_Y1_X7_RTR_MAX_OFFSET                  0x3340773#define SRAM_Y1_X7_RTR_SECTION                     0x7000774#define mmSRAM_Y2_X0_BANK_BASE                     0x7FFC280000ull775#define SRAM_Y2_X0_BANK_MAX_OFFSET                 0x4000776#define SRAM_Y2_X0_BANK_SECTION                    0x1000777#define mmSRAM_Y2_X0_RTR_BASE                      0x7FFC281000ull778#define SRAM_Y2_X0_RTR_MAX_OFFSET                  0x3340779#define SRAM_Y2_X0_RTR_SECTION                     0x7000780#define mmSRAM_Y2_X1_BANK_BASE                     0x7FFC288000ull781#define SRAM_Y2_X1_BANK_MAX_OFFSET                 0x4000782#define SRAM_Y2_X1_BANK_SECTION                    0x1000783#define mmSRAM_Y2_X1_RTR_BASE                      0x7FFC289000ull784#define SRAM_Y2_X1_RTR_MAX_OFFSET                  0x3340785#define SRAM_Y2_X1_RTR_SECTION                     0x7000786#define mmSRAM_Y2_X2_BANK_BASE                     0x7FFC290000ull787#define SRAM_Y2_X2_BANK_MAX_OFFSET                 0x4000788#define SRAM_Y2_X2_BANK_SECTION                    0x1000789#define mmSRAM_Y2_X2_RTR_BASE                      0x7FFC291000ull790#define SRAM_Y2_X2_RTR_MAX_OFFSET                  0x3340791#define SRAM_Y2_X2_RTR_SECTION                     0x7000792#define mmSRAM_Y2_X3_BANK_BASE                     0x7FFC298000ull793#define SRAM_Y2_X3_BANK_MAX_OFFSET                 0x4000794#define SRAM_Y2_X3_BANK_SECTION                    0x1000795#define mmSRAM_Y2_X3_RTR_BASE                      0x7FFC299000ull796#define SRAM_Y2_X3_RTR_MAX_OFFSET                  0x3340797#define SRAM_Y2_X3_RTR_SECTION                     0x7000798#define mmSRAM_Y2_X4_BANK_BASE                     0x7FFC2A0000ull799#define SRAM_Y2_X4_BANK_MAX_OFFSET                 0x4000800#define SRAM_Y2_X4_BANK_SECTION                    0x1000801#define mmSRAM_Y2_X4_RTR_BASE                      0x7FFC2A1000ull802#define SRAM_Y2_X4_RTR_MAX_OFFSET                  0x3340803#define SRAM_Y2_X4_RTR_SECTION                     0x7000804#define mmSRAM_Y2_X5_BANK_BASE                     0x7FFC2A8000ull805#define SRAM_Y2_X5_BANK_MAX_OFFSET                 0x4000806#define SRAM_Y2_X5_BANK_SECTION                    0x1000807#define mmSRAM_Y2_X5_RTR_BASE                      0x7FFC2A9000ull808#define SRAM_Y2_X5_RTR_MAX_OFFSET                  0x3340809#define SRAM_Y2_X5_RTR_SECTION                     0x7000810#define mmSRAM_Y2_X6_BANK_BASE                     0x7FFC2B0000ull811#define SRAM_Y2_X6_BANK_MAX_OFFSET                 0x4000812#define SRAM_Y2_X6_BANK_SECTION                    0x1000813#define mmSRAM_Y2_X6_RTR_BASE                      0x7FFC2B1000ull814#define SRAM_Y2_X6_RTR_MAX_OFFSET                  0x3340815#define SRAM_Y2_X6_RTR_SECTION                     0x7000816#define mmSRAM_Y2_X7_BANK_BASE                     0x7FFC2B8000ull817#define SRAM_Y2_X7_BANK_MAX_OFFSET                 0x4000818#define SRAM_Y2_X7_BANK_SECTION                    0x1000819#define mmSRAM_Y2_X7_RTR_BASE                      0x7FFC2B9000ull820#define SRAM_Y2_X7_RTR_MAX_OFFSET                  0x3340821#define SRAM_Y2_X7_RTR_SECTION                     0x7000822#define mmSRAM_Y3_X0_BANK_BASE                     0x7FFC2C0000ull823#define SRAM_Y3_X0_BANK_MAX_OFFSET                 0x4000824#define SRAM_Y3_X0_BANK_SECTION                    0x1000825#define mmSRAM_Y3_X0_RTR_BASE                      0x7FFC2C1000ull826#define SRAM_Y3_X0_RTR_MAX_OFFSET                  0x3340827#define SRAM_Y3_X0_RTR_SECTION                     0x7000828#define mmSRAM_Y3_X1_BANK_BASE                     0x7FFC2C8000ull829#define SRAM_Y3_X1_BANK_MAX_OFFSET                 0x4000830#define SRAM_Y3_X1_BANK_SECTION                    0x1000831#define mmSRAM_Y3_X1_RTR_BASE                      0x7FFC2C9000ull832#define SRAM_Y3_X1_RTR_MAX_OFFSET                  0x3340833#define SRAM_Y3_X1_RTR_SECTION                     0x7000834#define mmSRAM_Y3_X2_BANK_BASE                     0x7FFC2D0000ull835#define SRAM_Y3_X2_BANK_MAX_OFFSET                 0x4000836#define SRAM_Y3_X2_BANK_SECTION                    0x1000837#define mmSRAM_Y3_X2_RTR_BASE                      0x7FFC2D1000ull838#define SRAM_Y3_X2_RTR_MAX_OFFSET                  0x3340839#define SRAM_Y3_X2_RTR_SECTION                     0x7000840#define mmSRAM_Y3_X3_BANK_BASE                     0x7FFC2D8000ull841#define SRAM_Y3_X3_BANK_MAX_OFFSET                 0x4000842#define SRAM_Y3_X3_BANK_SECTION                    0x1000843#define mmSRAM_Y3_X3_RTR_BASE                      0x7FFC2D9000ull844#define SRAM_Y3_X3_RTR_MAX_OFFSET                  0x3340845#define SRAM_Y3_X3_RTR_SECTION                     0x7000846#define mmSRAM_Y3_X4_BANK_BASE                     0x7FFC2E0000ull847#define SRAM_Y3_X4_BANK_MAX_OFFSET                 0x4000848#define SRAM_Y3_X4_BANK_SECTION                    0x1000849#define mmSRAM_Y3_X4_RTR_BASE                      0x7FFC2E1000ull850#define SRAM_Y3_X4_RTR_MAX_OFFSET                  0x3340851#define SRAM_Y3_X4_RTR_SECTION                     0x7000852#define mmSRAM_Y3_X5_BANK_BASE                     0x7FFC2E8000ull853#define SRAM_Y3_X5_BANK_MAX_OFFSET                 0x4000854#define SRAM_Y3_X5_BANK_SECTION                    0x1000855#define mmSRAM_Y3_X5_RTR_BASE                      0x7FFC2E9000ull856#define SRAM_Y3_X5_RTR_MAX_OFFSET                  0x3340857#define SRAM_Y3_X5_RTR_SECTION                     0x7000858#define mmSRAM_Y3_X6_BANK_BASE                     0x7FFC2F0000ull859#define SRAM_Y3_X6_BANK_MAX_OFFSET                 0x4000860#define SRAM_Y3_X6_BANK_SECTION                    0x1000861#define mmSRAM_Y3_X6_RTR_BASE                      0x7FFC2F1000ull862#define SRAM_Y3_X6_RTR_MAX_OFFSET                  0x3340863#define SRAM_Y3_X6_RTR_SECTION                     0x7000864#define mmSRAM_Y3_X7_BANK_BASE                     0x7FFC2F8000ull865#define SRAM_Y3_X7_BANK_MAX_OFFSET                 0x4000866#define SRAM_Y3_X7_BANK_SECTION                    0x1000867#define mmSRAM_Y3_X7_RTR_BASE                      0x7FFC2F9000ull868#define SRAM_Y3_X7_RTR_MAX_OFFSET                  0x3340869#define SRAM_Y3_X7_RTR_SECTION                     0x7000870#define mmSIF_RTR_0_BASE                           0x7FFC300000ull871#define SIF_RTR_0_MAX_OFFSET                       0x6500872#define SIF_RTR_0_SECTION                          0x6000873#define mmSIF_RTR_CTRL_0_BASE                      0x7FFC306000ull874#define SIF_RTR_CTRL_0_MAX_OFFSET                  0xCC00875#define SIF_RTR_CTRL_0_SECTION                     0xA000876#define mmSIF_RTR_1_BASE                           0x7FFC310000ull877#define SIF_RTR_1_MAX_OFFSET                       0x6500878#define SIF_RTR_1_SECTION                          0x6000879#define mmSIF_RTR_CTRL_1_BASE                      0x7FFC316000ull880#define SIF_RTR_CTRL_1_MAX_OFFSET                  0xCC00881#define SIF_RTR_CTRL_1_SECTION                     0xA000882#define mmSIF_RTR_2_BASE                           0x7FFC320000ull883#define SIF_RTR_2_MAX_OFFSET                       0x6500884#define SIF_RTR_2_SECTION                          0x6000885#define mmSIF_RTR_CTRL_2_BASE                      0x7FFC326000ull886#define SIF_RTR_CTRL_2_MAX_OFFSET                  0xCC00887#define SIF_RTR_CTRL_2_SECTION                     0xA000888#define mmSIF_RTR_3_BASE                           0x7FFC330000ull889#define SIF_RTR_3_MAX_OFFSET                       0x6500890#define SIF_RTR_3_SECTION                          0x6000891#define mmSIF_RTR_CTRL_3_BASE                      0x7FFC336000ull892#define SIF_RTR_CTRL_3_MAX_OFFSET                  0xCC00893#define SIF_RTR_CTRL_3_SECTION                     0xA000894#define mmSIF_RTR_4_BASE                           0x7FFC340000ull895#define SIF_RTR_4_MAX_OFFSET                       0x6500896#define SIF_RTR_4_SECTION                          0x6000897#define mmSIF_RTR_CTRL_4_BASE                      0x7FFC346000ull898#define SIF_RTR_CTRL_4_MAX_OFFSET                  0xCC00899#define SIF_RTR_CTRL_4_SECTION                     0xA000900#define mmSIF_RTR_5_BASE                           0x7FFC350000ull901#define SIF_RTR_5_MAX_OFFSET                       0x6500902#define SIF_RTR_5_SECTION                          0x6000903#define mmSIF_RTR_CTRL_5_BASE                      0x7FFC356000ull904#define SIF_RTR_CTRL_5_MAX_OFFSET                  0xCC00905#define SIF_RTR_CTRL_5_SECTION                     0xA000906#define mmSIF_RTR_6_BASE                           0x7FFC360000ull907#define SIF_RTR_6_MAX_OFFSET                       0x6500908#define SIF_RTR_6_SECTION                          0x6000909#define mmSIF_RTR_CTRL_6_BASE                      0x7FFC366000ull910#define SIF_RTR_CTRL_6_MAX_OFFSET                  0xCC00911#define SIF_RTR_CTRL_6_SECTION                     0xA000912#define mmSIF_RTR_7_BASE                           0x7FFC370000ull913#define SIF_RTR_7_MAX_OFFSET                       0x6500914#define SIF_RTR_7_SECTION                          0x6000915#define mmSIF_RTR_CTRL_7_BASE                      0x7FFC376000ull916#define SIF_RTR_CTRL_7_MAX_OFFSET                  0xCC00917#define SIF_RTR_CTRL_7_SECTION                     0xA000918#define mmNIF_RTR_0_BASE                           0x7FFC380000ull919#define NIF_RTR_0_MAX_OFFSET                       0x6500920#define NIF_RTR_0_SECTION                          0x6000921#define mmNIF_RTR_CTRL_0_BASE                      0x7FFC386000ull922#define NIF_RTR_CTRL_0_MAX_OFFSET                  0xCC00923#define NIF_RTR_CTRL_0_SECTION                     0xA000924#define mmNIF_RTR_1_BASE                           0x7FFC390000ull925#define NIF_RTR_1_MAX_OFFSET                       0x6500926#define NIF_RTR_1_SECTION                          0x6000927#define mmNIF_RTR_CTRL_1_BASE                      0x7FFC396000ull928#define NIF_RTR_CTRL_1_MAX_OFFSET                  0xCC00929#define NIF_RTR_CTRL_1_SECTION                     0xA000930#define mmNIF_RTR_2_BASE                           0x7FFC3A0000ull931#define NIF_RTR_2_MAX_OFFSET                       0x6500932#define NIF_RTR_2_SECTION                          0x6000933#define mmNIF_RTR_CTRL_2_BASE                      0x7FFC3A6000ull934#define NIF_RTR_CTRL_2_MAX_OFFSET                  0xCC00935#define NIF_RTR_CTRL_2_SECTION                     0xA000936#define mmNIF_RTR_3_BASE                           0x7FFC3B0000ull937#define NIF_RTR_3_MAX_OFFSET                       0x6500938#define NIF_RTR_3_SECTION                          0x6000939#define mmNIF_RTR_CTRL_3_BASE                      0x7FFC3B6000ull940#define NIF_RTR_CTRL_3_MAX_OFFSET                  0xCC00941#define NIF_RTR_CTRL_3_SECTION                     0xA000942#define mmNIF_RTR_4_BASE                           0x7FFC3C0000ull943#define NIF_RTR_4_MAX_OFFSET                       0x6500944#define NIF_RTR_4_SECTION                          0x6000945#define mmNIF_RTR_CTRL_4_BASE                      0x7FFC3C6000ull946#define NIF_RTR_CTRL_4_MAX_OFFSET                  0xCC00947#define NIF_RTR_CTRL_4_SECTION                     0xA000948#define mmNIF_RTR_5_BASE                           0x7FFC3D0000ull949#define NIF_RTR_5_MAX_OFFSET                       0x6500950#define NIF_RTR_5_SECTION                          0x6000951#define mmNIF_RTR_CTRL_5_BASE                      0x7FFC3D6000ull952#define NIF_RTR_CTRL_5_MAX_OFFSET                  0xCC00953#define NIF_RTR_CTRL_5_SECTION                     0xA000954#define mmNIF_RTR_6_BASE                           0x7FFC3E0000ull955#define NIF_RTR_6_MAX_OFFSET                       0x6500956#define NIF_RTR_6_SECTION                          0x6000957#define mmNIF_RTR_CTRL_6_BASE                      0x7FFC3E6000ull958#define NIF_RTR_CTRL_6_MAX_OFFSET                  0xCC00959#define NIF_RTR_CTRL_6_SECTION                     0xA000960#define mmNIF_RTR_7_BASE                           0x7FFC3F0000ull961#define NIF_RTR_7_MAX_OFFSET                       0x6500962#define NIF_RTR_7_SECTION                          0x6000963#define mmNIF_RTR_CTRL_7_BASE                      0x7FFC3F6000ull964#define NIF_RTR_CTRL_7_MAX_OFFSET                  0xCC00965#define NIF_RTR_CTRL_7_SECTION                     0x4B000966#define mmCPU_CA53_CFG_BASE                        0x7FFC441000ull967#define CPU_CA53_CFG_MAX_OFFSET                    0x2180968#define CPU_CA53_CFG_SECTION                       0x1000969#define mmCPU_IF_BASE                              0x7FFC442000ull970#define CPU_IF_MAX_OFFSET                          0x43C0971#define CPU_IF_SECTION                             0x2000972#define mmCPU_TIMESTAMP_BASE                       0x7FFC444000ull973#define CPU_TIMESTAMP_MAX_OFFSET                   0x1000974#define CPU_TIMESTAMP_SECTION                      0x3C000975#define mmDMA_IF_W_S_BASE                          0x7FFC480000ull976#define DMA_IF_W_S_MAX_OFFSET                      0x8380977#define DMA_IF_W_S_SECTION                         0x1000978#define mmDMA_IF_W_S_DOWN_CH0_BASE                 0x7FFC481000ull979#define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET             0xCC00980#define DMA_IF_W_S_DOWN_CH0_SECTION                0x1000981#define mmDMA_IF_W_S_DOWN_CH1_BASE                 0x7FFC482000ull982#define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET             0xCC00983#define DMA_IF_W_S_DOWN_CH1_SECTION                0x5000984#define mmDMA_W_PLL_BASE                           0x7FFC487000ull985#define DMA_W_PLL_MAX_OFFSET                       0x5200986#define DMA_W_PLL_SECTION                          0x1000987#define mmIF_W_PLL_BASE                            0x7FFC488000ull988#define IF_W_PLL_MAX_OFFSET                        0x5200989#define IF_W_PLL_SECTION                           0x1000990#define mmDMA_IF_W_S_DOWN_BASE                     0x7FFC489000ull991#define DMA_IF_W_S_DOWN_MAX_OFFSET                 0x1500992#define DMA_IF_W_S_DOWN_SECTION                    0x7000993#define mmSYNC_MNGR_GLBL_W_S_BASE                  0x7FFC490000ull994#define SYNC_MNGR_GLBL_W_S_MAX_OFFSET              0x6C00995#define SYNC_MNGR_GLBL_W_S_SECTION                 0x1000996#define mmSYNC_MNGR_OBJS_W_S_BASE                  0x7FFC491000ull997#define SYNC_MNGR_OBJS_W_S_MAX_OFFSET              0x5C00998#define SYNC_MNGR_OBJS_W_S_SECTION                 0xF000999#define mmDMA_IF_E_S_BASE                          0x7FFC4A0000ull1000#define DMA_IF_E_S_MAX_OFFSET                      0x83801001#define DMA_IF_E_S_SECTION                         0x10001002#define mmDMA_IF_E_S_DOWN_CH0_BASE                 0x7FFC4A1000ull1003#define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET             0xCC001004#define DMA_IF_E_S_DOWN_CH0_SECTION                0x10001005#define mmDMA_IF_E_S_DOWN_CH1_BASE                 0x7FFC4A2000ull1006#define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET             0xCC001007#define DMA_IF_E_S_DOWN_CH1_SECTION                0x50001008#define mmIF_E_PLL_BASE                            0x7FFC4A7000ull1009#define IF_E_PLL_MAX_OFFSET                        0x52001010#define IF_E_PLL_SECTION                           0x10001011#define mmDMA_E_PLL_BASE                           0x7FFC4A8000ull1012#define DMA_E_PLL_MAX_OFFSET                       0x52001013#define DMA_E_PLL_SECTION                          0x10001014#define mmDMA_IF_E_S_DOWN_BASE                     0x7FFC4A9000ull1015#define DMA_IF_E_S_DOWN_MAX_OFFSET                 0x15001016#define DMA_IF_E_S_DOWN_SECTION                    0x70001017#define mmSYNC_MNGR_GLBL_E_S_BASE                  0x7FFC4B0000ull1018#define SYNC_MNGR_GLBL_E_S_MAX_OFFSET              0x6C001019#define SYNC_MNGR_GLBL_E_S_SECTION                 0x10001020#define mmSYNC_MNGR_OBJS_E_S_BASE                  0x7FFC4B1000ull1021#define SYNC_MNGR_OBJS_E_S_MAX_OFFSET              0x5C001022#define SYNC_MNGR_OBJS_E_S_SECTION                 0xF0001023#define mmDMA_IF_W_N_BASE                          0x7FFC4C0000ull1024#define DMA_IF_W_N_MAX_OFFSET                      0x83801025#define DMA_IF_W_N_SECTION                         0x10001026#define mmDMA_IF_W_N_DOWN_CH0_BASE                 0x7FFC4C1000ull1027#define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET             0xCC001028#define DMA_IF_W_N_DOWN_CH0_SECTION                0x10001029#define mmDMA_IF_W_N_DOWN_CH1_BASE                 0x7FFC4C2000ull1030#define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET             0xCC001031#define DMA_IF_W_N_DOWN_CH1_SECTION                0x50001032#define mmMESH_W_PLL_BASE                          0x7FFC4C7000ull1033#define MESH_W_PLL_MAX_OFFSET                      0x52001034#define MESH_W_PLL_SECTION                         0x10001035#define mmSRAM_W_PLL_BASE                          0x7FFC4C8000ull1036#define SRAM_W_PLL_MAX_OFFSET                      0x52001037#define SRAM_W_PLL_SECTION                         0x10001038#define mmDMA_IF_W_N_DOWN_BASE                     0x7FFC4C9000ull1039#define DMA_IF_W_N_DOWN_MAX_OFFSET                 0x15001040#define DMA_IF_W_N_DOWN_SECTION                    0x70001041#define mmSYNC_MNGR_GLBL_W_N_BASE                  0x7FFC4D0000ull1042#define SYNC_MNGR_GLBL_W_N_MAX_OFFSET              0x6C001043#define SYNC_MNGR_GLBL_W_N_SECTION                 0x10001044#define mmSYNC_MNGR_OBJS_W_N_BASE                  0x7FFC4D1000ull1045#define SYNC_MNGR_OBJS_W_N_MAX_OFFSET              0x5C001046#define SYNC_MNGR_OBJS_W_N_SECTION                 0xF0001047#define mmDMA_IF_E_N_BASE                          0x7FFC4E0000ull1048#define DMA_IF_E_N_MAX_OFFSET                      0x83801049#define DMA_IF_E_N_SECTION                         0x10001050#define mmDMA_IF_E_N_DOWN_CH0_BASE                 0x7FFC4E1000ull1051#define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET             0xCC001052#define DMA_IF_E_N_DOWN_CH0_SECTION                0x10001053#define mmDMA_IF_E_N_DOWN_CH1_BASE                 0x7FFC4E2000ull1054#define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET             0xCC001055#define DMA_IF_E_N_DOWN_CH1_SECTION                0x50001056#define mmMESH_E_PLL_BASE                          0x7FFC4E7000ull1057#define MESH_E_PLL_MAX_OFFSET                      0x52001058#define MESH_E_PLL_SECTION                         0x10001059#define mmSRAM_E_PLL_BASE                          0x7FFC4E8000ull1060#define SRAM_E_PLL_MAX_OFFSET                      0x52001061#define SRAM_E_PLL_SECTION                         0x10001062#define mmDMA_IF_E_N_DOWN_BASE                     0x7FFC4E9000ull1063#define DMA_IF_E_N_DOWN_MAX_OFFSET                 0x15001064#define DMA_IF_E_N_DOWN_SECTION                    0x70001065#define mmSYNC_MNGR_GLBL_E_N_BASE                  0x7FFC4F0000ull1066#define SYNC_MNGR_GLBL_E_N_MAX_OFFSET              0x6C001067#define SYNC_MNGR_GLBL_E_N_SECTION                 0x10001068#define mmSYNC_MNGR_OBJS_E_N_BASE                  0x7FFC4F1000ull1069#define SYNC_MNGR_OBJS_E_N_MAX_OFFSET              0x5C001070#define SYNC_MNGR_OBJS_E_N_SECTION                 0xF0001071#define mmDMA0_CORE_BASE                           0x7FFC500000ull1072#define DMA0_CORE_MAX_OFFSET                       0x23C01073#define DMA0_CORE_SECTION                          0x80001074#define mmDMA0_QM_BASE                             0x7FFC508000ull1075#define DMA0_QM_MAX_OFFSET                         0xD0401076#define DMA0_QM_SECTION                            0x180001077#define mmDMA1_CORE_BASE                           0x7FFC520000ull1078#define DMA1_CORE_MAX_OFFSET                       0x23C01079#define DMA1_CORE_SECTION                          0x80001080#define mmDMA1_QM_BASE                             0x7FFC528000ull1081#define DMA1_QM_MAX_OFFSET                         0xD0401082#define DMA1_QM_SECTION                            0x180001083#define mmDMA2_CORE_BASE                           0x7FFC540000ull1084#define DMA2_CORE_MAX_OFFSET                       0x23C01085#define DMA2_CORE_SECTION                          0x80001086#define mmDMA2_QM_BASE                             0x7FFC548000ull1087#define DMA2_QM_MAX_OFFSET                         0xD0401088#define DMA2_QM_SECTION                            0x180001089#define mmDMA3_CORE_BASE                           0x7FFC560000ull1090#define DMA3_CORE_MAX_OFFSET                       0x23C01091#define DMA3_CORE_SECTION                          0x80001092#define mmDMA3_QM_BASE                             0x7FFC568000ull1093#define DMA3_QM_MAX_OFFSET                         0xD0401094#define DMA3_QM_SECTION                            0x180001095#define mmDMA4_CORE_BASE                           0x7FFC580000ull1096#define DMA4_CORE_MAX_OFFSET                       0x23C01097#define DMA4_CORE_SECTION                          0x80001098#define mmDMA4_QM_BASE                             0x7FFC588000ull1099#define DMA4_QM_MAX_OFFSET                         0xD0401100#define DMA4_QM_SECTION                            0x180001101#define mmDMA5_CORE_BASE                           0x7FFC5A0000ull1102#define DMA5_CORE_MAX_OFFSET                       0x23C01103#define DMA5_CORE_SECTION                          0x80001104#define mmDMA5_QM_BASE                             0x7FFC5A8000ull1105#define DMA5_QM_MAX_OFFSET                         0xD0401106#define DMA5_QM_SECTION                            0x180001107#define mmDMA6_CORE_BASE                           0x7FFC5C0000ull1108#define DMA6_CORE_MAX_OFFSET                       0x23C01109#define DMA6_CORE_SECTION                          0x80001110#define mmDMA6_QM_BASE                             0x7FFC5C8000ull1111#define DMA6_QM_MAX_OFFSET                         0xD0401112#define DMA6_QM_SECTION                            0x180001113#define mmDMA7_CORE_BASE                           0x7FFC5E0000ull1114#define DMA7_CORE_MAX_OFFSET                       0x23C01115#define DMA7_CORE_SECTION                          0x80001116#define mmDMA7_QM_BASE                             0x7FFC5E8000ull1117#define DMA7_QM_MAX_OFFSET                         0xD0401118#define DMA7_QM_SECTION                            0x180001119#define mmHBM0_BASE                                0x7FFC600000ull1120#define HBM0_MAX_OFFSET                            0x8F581121#define HBM0_SECTION                               0x800001122#define mmHBM1_BASE                                0x7FFC680000ull1123#define HBM1_MAX_OFFSET                            0x8F581124#define HBM1_SECTION                               0x800001125#define mmHBM2_BASE                                0x7FFC700000ull1126#define HBM2_MAX_OFFSET                            0x8F581127#define HBM2_SECTION                               0x800001128#define mmHBM3_BASE                                0x7FFC780000ull1129#define HBM3_MAX_OFFSET                            0x8F581130#define HBM3_SECTION                               0x800001131#define mmGIC_BASE                                 0x7FFC800000ull1132#define GIC_MAX_OFFSET                             0x100001133#define GIC_SECTION                                0x4010001134#define mmPCIE_WRAP_BASE                           0x7FFCC01000ull1135#define PCIE_WRAP_MAX_OFFSET                       0xDF001136#define PCIE_WRAP_SECTION                          0x10001137#define mmPCIE_DBI_BASE                            0x7FFCC02000ull1138#define PCIE_DBI_MAX_OFFSET                        0xC0401139#define PCIE_DBI_SECTION                           0x20001140#define mmPCIE_CORE_BASE                           0x7FFCC04000ull1141#define PCIE_CORE_MAX_OFFSET                       0x9BC01142#define PCIE_CORE_SECTION                          0x30001143#define mmPCIE_AUX_BASE                            0x7FFCC07000ull1144#define PCIE_AUX_MAX_OFFSET                        0x9C401145#define PCIE_AUX_SECTION                           0x90001146#define mmPCIE_PHY_BASE                            0x7FFCC10000ull1147#define PCIE_PHY_MAX_OFFSET                        0x96401148#define PCIE_PHY_SECTION                           0x10001149#define mmMMU_UP_BASE                              0x7FFCC11000ull1150#define MMU_UP_MAX_OFFSET                          0x70001151#define MMU_UP_SECTION                             0x10001152#define mmSTLB_BASE                                0x7FFCC12000ull1153#define STLB_MAX_OFFSET                            0x88001154#define STLB_SECTION                               0x10001155#define mmPCIE_MSI_BASE                            0x7FFCC13000ull1156#define PCIE_MSI_MAX_OFFSET                        0x80001157#define PCIE_MSI_SECTION                           0x2D0001158#define mmPSOC_I2C_M0_BASE                         0x7FFCC40000ull1159#define PSOC_I2C_M0_MAX_OFFSET                     0x10001160#define PSOC_I2C_M0_SECTION                        0x10001161#define mmPSOC_I2C_M1_BASE                         0x7FFCC41000ull1162#define PSOC_I2C_M1_MAX_OFFSET                     0x10001163#define PSOC_I2C_M1_SECTION                        0x10001164#define mmPSOC_I2C_S_BASE                          0x7FFCC42000ull1165#define PSOC_I2C_S_MAX_OFFSET                      0x10001166#define PSOC_I2C_S_SECTION                         0x10001167#define mmPSOC_SPI_BASE                            0x7FFCC43000ull1168#define PSOC_SPI_MAX_OFFSET                        0x10001169#define PSOC_SPI_SECTION                           0x20001170#define mmPSOC_UART_0_BASE                         0x7FFCC45000ull1171#define PSOC_UART_0_MAX_OFFSET                     0x10001172#define PSOC_UART_0_SECTION                        0x10001173#define mmPSOC_UART_1_BASE                         0x7FFCC46000ull1174#define PSOC_UART_1_MAX_OFFSET                     0x10001175#define PSOC_UART_1_SECTION                        0x10001176#define mmPSOC_TIMER_BASE                          0x7FFCC47000ull1177#define PSOC_TIMER_MAX_OFFSET                      0x10001178#define PSOC_TIMER_SECTION                         0x10001179#define mmPSOC_WDOG_BASE                           0x7FFCC48000ull1180#define PSOC_WDOG_MAX_OFFSET                       0x10001181#define PSOC_WDOG_SECTION                          0x10001182#define mmPSOC_TIMESTAMP_BASE                      0x7FFCC49000ull1183#define PSOC_TIMESTAMP_MAX_OFFSET                  0x10001184#define PSOC_TIMESTAMP_SECTION                     0x10001185#define mmPSOC_EFUSE_BASE                          0x7FFCC4A000ull1186#define PSOC_EFUSE_MAX_OFFSET                      0x30401187#define PSOC_EFUSE_SECTION                         0x10001188#define mmPSOC_GLOBAL_CONF_BASE                    0x7FFCC4B000ull1189#define PSOC_GLOBAL_CONF_MAX_OFFSET                0xCD801190#define PSOC_GLOBAL_CONF_SECTION                   0x10001191#define mmPSOC_GPIO0_BASE                          0x7FFCC4C000ull1192#define PSOC_GPIO0_MAX_OFFSET                      0x10001193#define PSOC_GPIO0_SECTION                         0x10001194#define mmPSOC_GPIO1_BASE                          0x7FFCC4D000ull1195#define PSOC_GPIO1_MAX_OFFSET                      0x10001196#define PSOC_GPIO1_SECTION                         0x10001197#define mmPSOC_BTL_BASE                            0x7FFCC4E000ull1198#define PSOC_BTL_MAX_OFFSET                        0x14801199#define PSOC_BTL_SECTION                           0x10001200#define mmPSOC_CS_TRACE_BASE                       0x7FFCC4F000ull1201#define PSOC_CS_TRACE_MAX_OFFSET                   0x16801202#define PSOC_CS_TRACE_SECTION                      0x10001203#define mmPSOC_GPIO2_BASE                          0x7FFCC50000ull1204#define PSOC_GPIO2_MAX_OFFSET                      0x10001205#define PSOC_GPIO2_SECTION                         0x10001206#define mmPSOC_GPIO3_BASE                          0x7FFCC51000ull1207#define PSOC_GPIO3_MAX_OFFSET                      0x10001208#define PSOC_GPIO3_SECTION                         0x10001209#define mmPSOC_GPIO4_BASE                          0x7FFCC52000ull1210#define PSOC_GPIO4_MAX_OFFSET                      0x10001211#define PSOC_GPIO4_SECTION                         0x10001212#define mmPSOC_DFT_EFUSE_BASE                      0x7FFCC53000ull1213#define PSOC_DFT_EFUSE_MAX_OFFSET                  0x30401214#define PSOC_DFT_EFUSE_SECTION                     0x10001215#define mmPSOC_RPM_0_BASE                          0x7FFCC54000ull1216#define PSOC_RPM_0_MAX_OFFSET                      0x88001217#define PSOC_RPM_0_SECTION                         0x10001218#define mmPSOC_RPM_1_BASE                          0x7FFCC55000ull1219#define PSOC_RPM_1_MAX_OFFSET                      0x88001220#define PSOC_RPM_1_SECTION                         0x10001221#define mmPSOC_RPM_2_BASE                          0x7FFCC56000ull1222#define PSOC_RPM_2_MAX_OFFSET                      0x88001223#define PSOC_RPM_2_SECTION                         0x10001224#define mmPSOC_RPM_3_BASE                          0x7FFCC57000ull1225#define PSOC_RPM_3_MAX_OFFSET                      0x88001226#define PSOC_RPM_3_SECTION                         0x190001227#define mmPSOC_CPU_PLL_BASE                        0x7FFCC70000ull1228#define PSOC_CPU_PLL_MAX_OFFSET                    0x52001229#define PSOC_CPU_PLL_SECTION                       0x10001230#define mmPSOC_MME_PLL_BASE                        0x7FFCC71000ull1231#define PSOC_MME_PLL_MAX_OFFSET                    0x52001232#define PSOC_MME_PLL_SECTION                       0x10001233#define mmPSOC_PCI_PLL_BASE                        0x7FFCC72000ull1234#define PSOC_PCI_PLL_MAX_OFFSET                    0x52001235#define PSOC_PCI_PLL_SECTION                       0x10001236#define mmPSOC_TPC_PLL_BASE                        0x7FFCC73000ull1237#define PSOC_TPC_PLL_MAX_OFFSET                    0x52001238#define PSOC_TPC_PLL_SECTION                       0x10001239#define mmPSOC_HBM_PLL_BASE                        0x7FFCC74000ull1240#define PSOC_HBM_PLL_MAX_OFFSET                    0x52001241#define PSOC_HBM_PLL_SECTION                       0x10001242#define mmPSOC_PM_BASE                             0x7FFCC75000ull1243#define PSOC_PM_MAX_OFFSET                         0x1F001244#define PSOC_PM_SECTION                            0x10001245#define mmPSOC_TS_BASE                             0x7FFCC76000ull1246#define PSOC_TS_MAX_OFFSET                         0xE6401247#define PSOC_TS_SECTION                            0x20001248#define mmPSOC_PWM0_BASE                           0x7FFCC78000ull1249#define PSOC_PWM0_MAX_OFFSET                       0x58001250#define PSOC_PWM0_SECTION                          0x10001251#define mmPSOC_PWM1_BASE                           0x7FFCC79000ull1252#define PSOC_PWM1_MAX_OFFSET                       0x58001253#define PSOC_PWM1_SECTION                          0x10001254#define mmPSOC_PWM2_BASE                           0x7FFCC7A000ull1255#define PSOC_PWM2_MAX_OFFSET                       0x58001256#define PSOC_PWM2_SECTION                          0x10001257#define mmPSOC_PWM3_BASE                           0x7FFCC7B000ull1258#define PSOC_PWM3_MAX_OFFSET                       0x58001259#define PSOC_PWM3_SECTION                          0x10001260#define mmPSOC_GPIO5_BASE                          0x7FFCC7C000ull1261#define PSOC_GPIO5_MAX_OFFSET                      0x10001262#define PSOC_GPIO5_SECTION                         0x10001263#define mmPSOC_GPIO6_BASE                          0x7FFCC7D000ull1264#define PSOC_GPIO6_MAX_OFFSET                      0x10001265#define PSOC_GPIO6_SECTION                         0x30001266#define mmPCIE_PMA_0_BASE                          0x7FFCC80000ull1267#define PCIE_PMA_0_MAX_OFFSET                      0x100031268#define PCIE_PMA_0_SECTION                         0x100001269#define mmPCIE_PMA_1_BASE                          0x7FFCC90000ull1270#define PCIE_PMA_1_MAX_OFFSET                      0x100031271#define PCIE_PMA_1_SECTION                         0x100001272#define mmPCIE_PMA_2_BASE                          0x7FFCCA0000ull1273#define PCIE_PMA_2_MAX_OFFSET                      0x100031274#define PCIE_PMA_2_SECTION                         0x100001275#define mmPCIE_PMA_3_BASE                          0x7FFCCB0000ull1276#define PCIE_PMA_3_MAX_OFFSET                      0x100031277#define PCIE_PMA_3_SECTION                         0x100001278#define mmNIC0_MAC_CH0_BASE                        0x7FFCCC0000ull1279#define NIC0_MAC_CH0_MAX_OFFSET                    0x84001280#define NIC0_MAC_CH0_SECTION                       0x10001281#define mmNIC0_MAC_CH1_BASE                        0x7FFCCC1000ull1282#define NIC0_MAC_CH1_MAX_OFFSET                    0x84001283#define NIC0_MAC_CH1_SECTION                       0x10001284#define mmNIC0_MAC_CH2_BASE                        0x7FFCCC2000ull1285#define NIC0_MAC_CH2_MAX_OFFSET                    0x84001286#define NIC0_MAC_CH2_SECTION                       0x10001287#define mmNIC0_MAC_CH3_BASE                        0x7FFCCC3000ull1288#define NIC0_MAC_CH3_MAX_OFFSET                    0x84001289#define NIC0_MAC_CH3_SECTION                       0x10001290#define mmNIC0_STAT_BASE                           0x7FFCCC4000ull1291#define NIC0_STAT_MAX_OFFSET                       0x4D001292#define NIC0_STAT_SECTION                          0x10001293#define mmNIC0_MAC_XPCS91_BASE                     0x7FFCCC5000ull1294#define NIC0_MAC_XPCS91_MAX_OFFSET                 0x23801295#define NIC0_MAC_XPCS91_SECTION                    0x30001296#define mmNIC0_MAC_CORE_BASE                       0x7FFCCC8000ull1297#define NIC0_MAC_CORE_MAX_OFFSET                   0x54001298#define NIC0_MAC_CORE_SECTION                      0x10001299#define mmNIC0_MAC_AUX_BASE                        0x7FFCCC9000ull1300#define NIC0_MAC_AUX_MAX_OFFSET                    0x30001301#define NIC0_MAC_AUX_SECTION                       0xF0001302#define mmNIC0_PHY_BASE                            0x7FFCCD8000ull1303#define NIC0_PHY_MAX_OFFSET                        0x34001304#define NIC0_PHY_SECTION                           0x80001305#define mmNIC0_QM0_BASE                            0x7FFCCE0000ull1306#define NIC0_QM0_MAX_OFFSET                        0xD0401307#define NIC0_QM0_SECTION                           0x20001308#define mmNIC0_QM1_BASE                            0x7FFCCE2000ull1309#define NIC0_QM1_MAX_OFFSET                        0xD0401310#define NIC0_QM1_SECTION                           0x20001311#define mmNIC0_QPC0_BASE                           0x7FFCCE4000ull1312#define NIC0_QPC0_MAX_OFFSET                       0x71401313#define NIC0_QPC0_SECTION                          0x10001314#define mmNIC0_QPC1_BASE                           0x7FFCCE5000ull1315#define NIC0_QPC1_MAX_OFFSET                       0x71401316#define NIC0_QPC1_SECTION                          0x30001317#define mmNIC0_RXB_BASE                            0x7FFCCE8000ull1318#define NIC0_RXB_MAX_OFFSET                        0x60401319#define NIC0_RXB_SECTION                           0x10001320#define mmNIC0_RXE0_BASE                           0x7FFCCE9000ull1321#define NIC0_RXE0_MAX_OFFSET                       0x2FC01322#define NIC0_RXE0_SECTION                          0x10001323#define mmNIC0_RXE1_BASE                           0x7FFCCEA000ull1324#define NIC0_RXE1_MAX_OFFSET                       0x2FC01325#define NIC0_RXE1_SECTION                          0x10001326#define mmNIC0_RX_GW_BASE                          0x7FFCCEB000ull1327#define NIC0_RX_GW_MAX_OFFSET                      0x45401328#define NIC0_RX_GW_SECTION                         0x50001329#define mmNIC0_TXS0_BASE                           0x7FFCCF0000ull1330#define NIC0_TXS0_MAX_OFFSET                       0x19C01331#define NIC0_TXS0_SECTION                          0x10001332#define mmNIC0_TXS1_BASE                           0x7FFCCF1000ull1333#define NIC0_TXS1_MAX_OFFSET                       0x19C01334#define NIC0_TXS1_SECTION                          0x10001335#define mmNIC0_TXE0_BASE                           0x7FFCCF2000ull1336#define NIC0_TXE0_MAX_OFFSET                       0x20401337#define NIC0_TXE0_SECTION                          0x10001338#define mmNIC0_TXE1_BASE                           0x7FFCCF3000ull1339#define NIC0_TXE1_MAX_OFFSET                       0x20401340#define NIC0_TXE1_SECTION                          0x10001341#define mmNIC0_TXB_BASE                            0x7FFCCF4000ull1342#define NIC0_TXB_MAX_OFFSET                        0xD4001343#define NIC0_TXB_SECTION                           0x10001344#define mmNIC0_TMR_BASE                            0x7FFCCF5000ull1345#define NIC0_TMR_MAX_OFFSET                        0x16001346#define NIC0_TMR_SECTION                           0x10001347#define mmNIC0_TX_GW_BASE                          0x7FFCCF6000ull1348#define NIC0_TX_GW_MAX_OFFSET                      0x14001349#define NIC0_TX_GW_SECTION                         0x20001350#define mmNIC0_TS_BASE                             0x7FFCCF8000ull1351#define NIC0_TS_MAX_OFFSET                         0xE6401352#define NIC0_TS_SECTION                            0x10001353#define mmNIC0_PLL_BASE                            0x7FFCCF9000ull1354#define NIC0_PLL_MAX_OFFSET                        0x52001355#define NIC0_PLL_SECTION                           0x10001356#define mmNIC0_PM_BASE                             0x7FFCCFA000ull1357#define NIC0_PM_MAX_OFFSET                         0x1F001358#define NIC0_PM_SECTION                            0x60001359#define mmNIC1_MAC_CH0_BASE                        0x7FFCD00000ull1360#define NIC1_MAC_CH0_MAX_OFFSET                    0x84001361#define NIC1_MAC_CH0_SECTION                       0x10001362#define mmNIC1_MAC_CH1_BASE                        0x7FFCD01000ull1363#define NIC1_MAC_CH1_MAX_OFFSET                    0x84001364#define NIC1_MAC_CH1_SECTION                       0x10001365#define mmNIC1_MAC_CH2_BASE                        0x7FFCD02000ull1366#define NIC1_MAC_CH2_MAX_OFFSET                    0x84001367#define NIC1_MAC_CH2_SECTION                       0x10001368#define mmNIC1_MAC_CH3_BASE                        0x7FFCD03000ull1369#define NIC1_MAC_CH3_MAX_OFFSET                    0x84001370#define NIC1_MAC_CH3_SECTION                       0x10001371#define mmNIC1_STAT_BASE                           0x7FFCD04000ull1372#define NIC1_STAT_MAX_OFFSET                       0x4D001373#define NIC1_STAT_SECTION                          0x10001374#define mmNIC1_MAC_XPCS91_BASE                     0x7FFCD05000ull1375#define NIC1_MAC_XPCS91_MAX_OFFSET                 0x23801376#define NIC1_MAC_XPCS91_SECTION                    0x30001377#define mmNIC1_MAC_CORE_BASE                       0x7FFCD08000ull1378#define NIC1_MAC_CORE_MAX_OFFSET                   0x54001379#define NIC1_MAC_CORE_SECTION                      0x10001380#define mmNIC1_MAC_AUX_BASE                        0x7FFCD09000ull1381#define NIC1_MAC_AUX_MAX_OFFSET                    0x30001382#define NIC1_MAC_AUX_SECTION                       0xF0001383#define mmNIC1_PHY_BASE                            0x7FFCD18000ull1384#define NIC1_PHY_MAX_OFFSET                        0x34001385#define NIC1_PHY_SECTION                           0x80001386#define mmNIC1_QM0_BASE                            0x7FFCD20000ull1387#define NIC1_QM0_MAX_OFFSET                        0xD0401388#define NIC1_QM0_SECTION                           0x20001389#define mmNIC1_QM1_BASE                            0x7FFCD22000ull1390#define NIC1_QM1_MAX_OFFSET                        0xD0401391#define NIC1_QM1_SECTION                           0x20001392#define mmNIC1_QPC0_BASE                           0x7FFCD24000ull1393#define NIC1_QPC0_MAX_OFFSET                       0x71401394#define NIC1_QPC0_SECTION                          0x10001395#define mmNIC1_QPC1_BASE                           0x7FFCD25000ull1396#define NIC1_QPC1_MAX_OFFSET                       0x71401397#define NIC1_QPC1_SECTION                          0x30001398#define mmNIC1_RXB_BASE                            0x7FFCD28000ull1399#define NIC1_RXB_MAX_OFFSET                        0x60401400#define NIC1_RXB_SECTION                           0x10001401#define mmNIC1_RXE0_BASE                           0x7FFCD29000ull1402#define NIC1_RXE0_MAX_OFFSET                       0x2FC01403#define NIC1_RXE0_SECTION                          0x10001404#define mmNIC1_RXE1_BASE                           0x7FFCD2A000ull1405#define NIC1_RXE1_MAX_OFFSET                       0x2FC01406#define NIC1_RXE1_SECTION                          0x10001407#define mmNIC1_RX_GW_BASE                          0x7FFCD2B000ull1408#define NIC1_RX_GW_MAX_OFFSET                      0x45401409#define NIC1_RX_GW_SECTION                         0x50001410#define mmNIC1_TXS0_BASE                           0x7FFCD30000ull1411#define NIC1_TXS0_MAX_OFFSET                       0x19C01412#define NIC1_TXS0_SECTION                          0x10001413#define mmNIC1_TXS1_BASE                           0x7FFCD31000ull1414#define NIC1_TXS1_MAX_OFFSET                       0x19C01415#define NIC1_TXS1_SECTION                          0x10001416#define mmNIC1_TXE0_BASE                           0x7FFCD32000ull1417#define NIC1_TXE0_MAX_OFFSET                       0x20401418#define NIC1_TXE0_SECTION                          0x10001419#define mmNIC1_TXE1_BASE                           0x7FFCD33000ull1420#define NIC1_TXE1_MAX_OFFSET                       0x20401421#define NIC1_TXE1_SECTION                          0x10001422#define mmNIC1_TXB_BASE                            0x7FFCD34000ull1423#define NIC1_TXB_MAX_OFFSET                        0xD4001424#define NIC1_TXB_SECTION                           0x10001425#define mmNIC1_TMR_BASE                            0x7FFCD35000ull1426#define NIC1_TMR_MAX_OFFSET                        0x16001427#define NIC1_TMR_SECTION                           0x10001428#define mmNIC1_TX_GW_BASE                          0x7FFCD36000ull1429#define NIC1_TX_GW_MAX_OFFSET                      0x14001430#define NIC1_TX_GW_SECTION                         0x20001431#define mmNIC1_TS_BASE                             0x7FFCD38000ull1432#define NIC1_TS_MAX_OFFSET                         0xE6401433#define NIC1_TS_SECTION                            0x10001434#define mmNIC1_PLL_BASE                            0x7FFCD39000ull1435#define NIC1_PLL_MAX_OFFSET                        0x52001436#define NIC1_PLL_SECTION                           0x10001437#define mmNIC1_PM_BASE                             0x7FFCD3A000ull1438#define NIC1_PM_MAX_OFFSET                         0x1F001439#define NIC1_PM_SECTION                            0x60001440#define mmNIC2_MAC_CH0_BASE                        0x7FFCD40000ull1441#define NIC2_MAC_CH0_MAX_OFFSET                    0x84001442#define NIC2_MAC_CH0_SECTION                       0x10001443#define mmNIC2_MAC_CH1_BASE                        0x7FFCD41000ull1444#define NIC2_MAC_CH1_MAX_OFFSET                    0x84001445#define NIC2_MAC_CH1_SECTION                       0x10001446#define mmNIC2_MAC_CH2_BASE                        0x7FFCD42000ull1447#define NIC2_MAC_CH2_MAX_OFFSET                    0x84001448#define NIC2_MAC_CH2_SECTION                       0x10001449#define mmNIC2_MAC_CH3_BASE                        0x7FFCD43000ull1450#define NIC2_MAC_CH3_MAX_OFFSET                    0x84001451#define NIC2_MAC_CH3_SECTION                       0x10001452#define mmNIC2_STAT_BASE                           0x7FFCD44000ull1453#define NIC2_STAT_MAX_OFFSET                       0x4D001454#define NIC2_STAT_SECTION                          0x10001455#define mmNIC2_MAC_XPCS91_BASE                     0x7FFCD45000ull1456#define NIC2_MAC_XPCS91_MAX_OFFSET                 0x23801457#define NIC2_MAC_XPCS91_SECTION                    0x30001458#define mmNIC2_MAC_CORE_BASE                       0x7FFCD48000ull1459#define NIC2_MAC_CORE_MAX_OFFSET                   0x54001460#define NIC2_MAC_CORE_SECTION                      0x10001461#define mmNIC2_MAC_AUX_BASE                        0x7FFCD49000ull1462#define NIC2_MAC_AUX_MAX_OFFSET                    0x30001463#define NIC2_MAC_AUX_SECTION                       0xF0001464#define mmNIC2_PHY_BASE                            0x7FFCD58000ull1465#define NIC2_PHY_MAX_OFFSET                        0x34001466#define NIC2_PHY_SECTION                           0x80001467#define mmNIC2_QM0_BASE                            0x7FFCD60000ull1468#define NIC2_QM0_MAX_OFFSET                        0xD0401469#define NIC2_QM0_SECTION                           0x20001470#define mmNIC2_QM1_BASE                            0x7FFCD62000ull1471#define NIC2_QM1_MAX_OFFSET                        0xD0401472#define NIC2_QM1_SECTION                           0x20001473#define mmNIC2_QPC0_BASE                           0x7FFCD64000ull1474#define NIC2_QPC0_MAX_OFFSET                       0x71401475#define NIC2_QPC0_SECTION                          0x10001476#define mmNIC2_QPC1_BASE                           0x7FFCD65000ull1477#define NIC2_QPC1_MAX_OFFSET                       0x71401478#define NIC2_QPC1_SECTION                          0x30001479#define mmNIC2_RXB_BASE                            0x7FFCD68000ull1480#define NIC2_RXB_MAX_OFFSET                        0x60401481#define NIC2_RXB_SECTION                           0x10001482#define mmNIC2_RXE0_BASE                           0x7FFCD69000ull1483#define NIC2_RXE0_MAX_OFFSET                       0x2FC01484#define NIC2_RXE0_SECTION                          0x10001485#define mmNIC2_RXE1_BASE                           0x7FFCD6A000ull1486#define NIC2_RXE1_MAX_OFFSET                       0x2FC01487#define NIC2_RXE1_SECTION                          0x10001488#define mmNIC2_RX_GW_BASE                          0x7FFCD6B000ull1489#define NIC2_RX_GW_MAX_OFFSET                      0x45401490#define NIC2_RX_GW_SECTION                         0x50001491#define mmNIC2_TXS0_BASE                           0x7FFCD70000ull1492#define NIC2_TXS0_MAX_OFFSET                       0x19C01493#define NIC2_TXS0_SECTION                          0x10001494#define mmNIC2_TXS1_BASE                           0x7FFCD71000ull1495#define NIC2_TXS1_MAX_OFFSET                       0x19C01496#define NIC2_TXS1_SECTION                          0x10001497#define mmNIC2_TXE0_BASE                           0x7FFCD72000ull1498#define NIC2_TXE0_MAX_OFFSET                       0x20401499#define NIC2_TXE0_SECTION                          0x10001500#define mmNIC2_TXE1_BASE                           0x7FFCD73000ull1501#define NIC2_TXE1_MAX_OFFSET                       0x20401502#define NIC2_TXE1_SECTION                          0x10001503#define mmNIC2_TXB_BASE                            0x7FFCD74000ull1504#define NIC2_TXB_MAX_OFFSET                        0xD4001505#define NIC2_TXB_SECTION                           0x10001506#define mmNIC2_TMR_BASE                            0x7FFCD75000ull1507#define NIC2_TMR_MAX_OFFSET                        0x16001508#define NIC2_TMR_SECTION                           0x10001509#define mmNIC2_TX_GW_BASE                          0x7FFCD76000ull1510#define NIC2_TX_GW_MAX_OFFSET                      0x14001511#define NIC2_TX_GW_SECTION                         0x20001512#define mmNIC2_HBM_PLL_BASE                        0x7FFCD78000ull1513#define NIC2_HBM_PLL_MAX_OFFSET                    0x52001514#define NIC2_HBM_PLL_SECTION                       0x10001515#define mmNIC2_MME_PLL_BASE                        0x7FFCD79000ull1516#define NIC2_MME_PLL_MAX_OFFSET                    0x52001517#define NIC2_MME_PLL_SECTION                       0x10001518#define mmNIC2_TPC_PLL_BASE                        0x7FFCD7A000ull1519#define NIC2_TPC_PLL_MAX_OFFSET                    0x52001520#define NIC2_TPC_PLL_SECTION                       0x60001521#define mmNIC3_MAC_CH0_BASE                        0x7FFCD80000ull1522#define NIC3_MAC_CH0_MAX_OFFSET                    0x84001523#define NIC3_MAC_CH0_SECTION                       0x10001524#define mmNIC3_MAC_CH1_BASE                        0x7FFCD81000ull1525#define NIC3_MAC_CH1_MAX_OFFSET                    0x84001526#define NIC3_MAC_CH1_SECTION                       0x10001527#define mmNIC3_MAC_CH2_BASE                        0x7FFCD82000ull1528#define NIC3_MAC_CH2_MAX_OFFSET                    0x84001529#define NIC3_MAC_CH2_SECTION                       0x10001530#define mmNIC3_MAC_CH3_BASE                        0x7FFCD83000ull1531#define NIC3_MAC_CH3_MAX_OFFSET                    0x84001532#define NIC3_MAC_CH3_SECTION                       0x10001533#define mmNIC3_STAT_BASE                           0x7FFCD84000ull1534#define NIC3_STAT_MAX_OFFSET                       0x4D001535#define NIC3_STAT_SECTION                          0x10001536#define mmNIC3_MAC_XPCS91_BASE                     0x7FFCD85000ull1537#define NIC3_MAC_XPCS91_MAX_OFFSET                 0x23801538#define NIC3_MAC_XPCS91_SECTION                    0x30001539#define mmNIC3_MAC_CORE_BASE                       0x7FFCD88000ull1540#define NIC3_MAC_CORE_MAX_OFFSET                   0x54001541#define NIC3_MAC_CORE_SECTION                      0x10001542#define mmNIC3_MAC_AUX_BASE                        0x7FFCD89000ull1543#define NIC3_MAC_AUX_MAX_OFFSET                    0x30001544#define NIC3_MAC_AUX_SECTION                       0xF0001545#define mmNIC3_PHY_BASE                            0x7FFCD98000ull1546#define NIC3_PHY_MAX_OFFSET                        0x34001547#define NIC3_PHY_SECTION                           0x80001548#define mmNIC3_QM0_BASE                            0x7FFCDA0000ull1549#define NIC3_QM0_MAX_OFFSET                        0xD0401550#define NIC3_QM0_SECTION                           0x20001551#define mmNIC3_QM1_BASE                            0x7FFCDA2000ull1552#define NIC3_QM1_MAX_OFFSET                        0xD0401553#define NIC3_QM1_SECTION                           0x20001554#define mmNIC3_QPC0_BASE                           0x7FFCDA4000ull1555#define NIC3_QPC0_MAX_OFFSET                       0x71401556#define NIC3_QPC0_SECTION                          0x10001557#define mmNIC3_QPC1_BASE                           0x7FFCDA5000ull1558#define NIC3_QPC1_MAX_OFFSET                       0x71401559#define NIC3_QPC1_SECTION                          0x30001560#define mmNIC3_RXB_BASE                            0x7FFCDA8000ull1561#define NIC3_RXB_MAX_OFFSET                        0x60401562#define NIC3_RXB_SECTION                           0x10001563#define mmNIC3_RXE0_BASE                           0x7FFCDA9000ull1564#define NIC3_RXE0_MAX_OFFSET                       0x2FC01565#define NIC3_RXE0_SECTION                          0x10001566#define mmNIC3_RXE1_BASE                           0x7FFCDAA000ull1567#define NIC3_RXE1_MAX_OFFSET                       0x2FC01568#define NIC3_RXE1_SECTION                          0x10001569#define mmNIC3_RX_GW_BASE                          0x7FFCDAB000ull1570#define NIC3_RX_GW_MAX_OFFSET                      0x45401571#define NIC3_RX_GW_SECTION                         0x50001572#define mmNIC3_TXS0_BASE                           0x7FFCDB0000ull1573#define NIC3_TXS0_MAX_OFFSET                       0x19C01574#define NIC3_TXS0_SECTION                          0x10001575#define mmNIC3_TXS1_BASE                           0x7FFCDB1000ull1576#define NIC3_TXS1_MAX_OFFSET                       0x19C01577#define NIC3_TXS1_SECTION                          0x10001578#define mmNIC3_TXE0_BASE                           0x7FFCDB2000ull1579#define NIC3_TXE0_MAX_OFFSET                       0x20401580#define NIC3_TXE0_SECTION                          0x10001581#define mmNIC3_TXE1_BASE                           0x7FFCDB3000ull1582#define NIC3_TXE1_MAX_OFFSET                       0x20401583#define NIC3_TXE1_SECTION                          0x10001584#define mmNIC3_TXB_BASE                            0x7FFCDB4000ull1585#define NIC3_TXB_MAX_OFFSET                        0xD4001586#define NIC3_TXB_SECTION                           0x10001587#define mmNIC3_TMR_BASE                            0x7FFCDB5000ull1588#define NIC3_TMR_MAX_OFFSET                        0x16001589#define NIC3_TMR_SECTION                           0x10001590#define mmNIC3_TX_GW_BASE                          0x7FFCDB6000ull1591#define NIC3_TX_GW_MAX_OFFSET                      0x14001592#define NIC3_TX_GW_SECTION                         0x20001593#define mmNIC3_TS_BASE                             0x7FFCDB8000ull1594#define NIC3_TS_MAX_OFFSET                         0xE6401595#define NIC3_TS_SECTION                            0x20001596#define mmNIC3_PM_BASE                             0x7FFCDBA000ull1597#define NIC3_PM_MAX_OFFSET                         0x1F001598#define NIC3_PM_SECTION                            0x60001599#define mmNIC4_MAC_CH0_BASE                        0x7FFCDC0000ull1600#define NIC4_MAC_CH0_MAX_OFFSET                    0x84001601#define NIC4_MAC_CH0_SECTION                       0x10001602#define mmNIC4_MAC_CH1_BASE                        0x7FFCDC1000ull1603#define NIC4_MAC_CH1_MAX_OFFSET                    0x84001604#define NIC4_MAC_CH1_SECTION                       0x10001605#define mmNIC4_MAC_CH2_BASE                        0x7FFCDC2000ull1606#define NIC4_MAC_CH2_MAX_OFFSET                    0x84001607#define NIC4_MAC_CH2_SECTION                       0x10001608#define mmNIC4_MAC_CH3_BASE                        0x7FFCDC3000ull1609#define NIC4_MAC_CH3_MAX_OFFSET                    0x84001610#define NIC4_MAC_CH3_SECTION                       0x10001611#define mmNIC4_STAT_BASE                           0x7FFCDC4000ull1612#define NIC4_STAT_MAX_OFFSET                       0x4D001613#define NIC4_STAT_SECTION                          0x10001614#define mmNIC4_MAC_XPCS91_BASE                     0x7FFCDC5000ull1615#define NIC4_MAC_XPCS91_MAX_OFFSET                 0x23801616#define NIC4_MAC_XPCS91_SECTION                    0x30001617#define mmNIC4_MAC_CORE_BASE                       0x7FFCDC8000ull1618#define NIC4_MAC_CORE_MAX_OFFSET                   0x54001619#define NIC4_MAC_CORE_SECTION                      0x10001620#define mmNIC4_MAC_AUX_BASE                        0x7FFCDC9000ull1621#define NIC4_MAC_AUX_MAX_OFFSET                    0x30001622#define NIC4_MAC_AUX_SECTION                       0xF0001623#define mmNIC4_PHY_BASE                            0x7FFCDD8000ull1624#define NIC4_PHY_MAX_OFFSET                        0x34001625#define NIC4_PHY_SECTION                           0x80001626#define mmNIC4_QM0_BASE                            0x7FFCDE0000ull1627#define NIC4_QM0_MAX_OFFSET                        0xD0401628#define NIC4_QM0_SECTION                           0x20001629#define mmNIC4_QM1_BASE                            0x7FFCDE2000ull1630#define NIC4_QM1_MAX_OFFSET                        0xD0401631#define NIC4_QM1_SECTION                           0x20001632#define mmNIC4_QPC0_BASE                           0x7FFCDE4000ull1633#define NIC4_QPC0_MAX_OFFSET                       0x71401634#define NIC4_QPC0_SECTION                          0x10001635#define mmNIC4_QPC1_BASE                           0x7FFCDE5000ull1636#define NIC4_QPC1_MAX_OFFSET                       0x71401637#define NIC4_QPC1_SECTION                          0x30001638#define mmNIC4_RXB_BASE                            0x7FFCDE8000ull1639#define NIC4_RXB_MAX_OFFSET                        0x60401640#define NIC4_RXB_SECTION                           0x10001641#define mmNIC4_RXE0_BASE                           0x7FFCDE9000ull1642#define NIC4_RXE0_MAX_OFFSET                       0x2FC01643#define NIC4_RXE0_SECTION                          0x10001644#define mmNIC4_RXE1_BASE                           0x7FFCDEA000ull1645#define NIC4_RXE1_MAX_OFFSET                       0x2FC01646#define NIC4_RXE1_SECTION                          0x10001647#define mmNIC4_RX_GW_BASE                          0x7FFCDEB000ull1648#define NIC4_RX_GW_MAX_OFFSET                      0x45401649#define NIC4_RX_GW_SECTION                         0x50001650#define mmNIC4_TXS0_BASE                           0x7FFCDF0000ull1651#define NIC4_TXS0_MAX_OFFSET                       0x19C01652#define NIC4_TXS0_SECTION                          0x10001653#define mmNIC4_TXS1_BASE                           0x7FFCDF1000ull1654#define NIC4_TXS1_MAX_OFFSET                       0x19C01655#define NIC4_TXS1_SECTION                          0x10001656#define mmNIC4_TXE0_BASE                           0x7FFCDF2000ull1657#define NIC4_TXE0_MAX_OFFSET                       0x20401658#define NIC4_TXE0_SECTION                          0x10001659#define mmNIC4_TXE1_BASE                           0x7FFCDF3000ull1660#define NIC4_TXE1_MAX_OFFSET                       0x20401661#define NIC4_TXE1_SECTION                          0x10001662#define mmNIC4_TXB_BASE                            0x7FFCDF4000ull1663#define NIC4_TXB_MAX_OFFSET                        0xD4001664#define NIC4_TXB_SECTION                           0x10001665#define mmNIC4_TMR_BASE                            0x7FFCDF5000ull1666#define NIC4_TMR_MAX_OFFSET                        0x16001667#define NIC4_TMR_SECTION                           0x10001668#define mmNIC4_TX_GW_BASE                          0x7FFCDF6000ull1669#define NIC4_TX_GW_MAX_OFFSET                      0x14001670#define NIC4_TX_GW_SECTION                         0x100001671#define mmTPC0_CFG_BASE                            0x7FFCE06000ull1672#define TPC0_CFG_MAX_OFFSET                        0xE4001673#define TPC0_CFG_SECTION                           0x40001674#define mmKERNEL_TENSOR_0_TPC0_CFG_BASE            0x7FFCE06400ull1675#define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET        0x38001676#define KERNEL_TENSOR_0_TPC0_CFG_SECTION           0x38001677#define mmKERNEL_TENSOR_1_TPC0_CFG_BASE            0x7FFCE06438ull1678#define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET        0x38001679#define KERNEL_TENSOR_1_TPC0_CFG_SECTION           0x38001680#define mmKERNEL_TENSOR_2_TPC0_CFG_BASE            0x7FFCE06470ull1681#define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET        0x38001682#define KERNEL_TENSOR_2_TPC0_CFG_SECTION           0x38001683#define mmKERNEL_TENSOR_3_TPC0_CFG_BASE            0x7FFCE064A8ull1684#define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET        0x38001685#define KERNEL_TENSOR_3_TPC0_CFG_SECTION           0x38001686#define mmKERNEL_TENSOR_4_TPC0_CFG_BASE            0x7FFCE064E0ull1687#define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET        0x38001688#define KERNEL_TENSOR_4_TPC0_CFG_SECTION           0x38001689#define mmKERNEL_TENSOR_5_TPC0_CFG_BASE            0x7FFCE06518ull1690#define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET        0x38001691#define KERNEL_TENSOR_5_TPC0_CFG_SECTION           0x38001692#define mmKERNEL_TENSOR_6_TPC0_CFG_BASE            0x7FFCE06550ull1693#define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET        0x38001694#define KERNEL_TENSOR_6_TPC0_CFG_SECTION           0x38001695#define mmKERNEL_TENSOR_7_TPC0_CFG_BASE            0x7FFCE06588ull1696#define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET        0x38001697#define KERNEL_TENSOR_7_TPC0_CFG_SECTION           0x38001698#define mmKERNEL_TENSOR_8_TPC0_CFG_BASE            0x7FFCE065C0ull1699#define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET        0x38001700#define KERNEL_TENSOR_8_TPC0_CFG_SECTION           0x38001701#define mmKERNEL_TENSOR_9_TPC0_CFG_BASE            0x7FFCE065F8ull1702#define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET        0x38001703#define KERNEL_TENSOR_9_TPC0_CFG_SECTION           0x38001704#define mmKERNEL_TENSOR_10_TPC0_CFG_BASE           0x7FFCE06630ull1705#define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET       0x38001706#define KERNEL_TENSOR_10_TPC0_CFG_SECTION          0x38001707#define mmKERNEL_TENSOR_11_TPC0_CFG_BASE           0x7FFCE06668ull1708#define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET       0x38001709#define KERNEL_TENSOR_11_TPC0_CFG_SECTION          0x38001710#define mmKERNEL_TENSOR_12_TPC0_CFG_BASE           0x7FFCE066A0ull1711#define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET       0x38001712#define KERNEL_TENSOR_12_TPC0_CFG_SECTION          0x38001713#define mmKERNEL_TENSOR_13_TPC0_CFG_BASE           0x7FFCE066D8ull1714#define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET       0x38001715#define KERNEL_TENSOR_13_TPC0_CFG_SECTION          0x38001716#define mmKERNEL_TENSOR_14_TPC0_CFG_BASE           0x7FFCE06710ull1717#define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET       0x38001718#define KERNEL_TENSOR_14_TPC0_CFG_SECTION          0x38001719#define mmKERNEL_TENSOR_15_TPC0_CFG_BASE           0x7FFCE06748ull1720#define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET       0x38001721#define KERNEL_TENSOR_15_TPC0_CFG_SECTION          0x38001722#define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE         0x7FFCE06780ull1723#define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET     0x80001724#define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION        0x80001725#define mmKERNEL_TPC0_CFG_BASE                     0x7FFCE06788ull1726#define KERNEL_TPC0_CFG_MAX_OFFSET                 0xB8001727#define KERNEL_TPC0_CFG_SECTION                    0x27801728#define mmQM_TENSOR_0_TPC0_CFG_BASE                0x7FFCE06A00ull1729#define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET            0x38001730#define QM_TENSOR_0_TPC0_CFG_SECTION               0x38001731#define mmQM_TENSOR_1_TPC0_CFG_BASE                0x7FFCE06A38ull1732#define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET            0x38001733#define QM_TENSOR_1_TPC0_CFG_SECTION               0x38001734#define mmQM_TENSOR_2_TPC0_CFG_BASE                0x7FFCE06A70ull1735#define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET            0x38001736#define QM_TENSOR_2_TPC0_CFG_SECTION               0x38001737#define mmQM_TENSOR_3_TPC0_CFG_BASE                0x7FFCE06AA8ull1738#define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET            0x38001739#define QM_TENSOR_3_TPC0_CFG_SECTION               0x38001740#define mmQM_TENSOR_4_TPC0_CFG_BASE                0x7FFCE06AE0ull1741#define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET            0x38001742#define QM_TENSOR_4_TPC0_CFG_SECTION               0x38001743#define mmQM_TENSOR_5_TPC0_CFG_BASE                0x7FFCE06B18ull1744#define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET            0x38001745#define QM_TENSOR_5_TPC0_CFG_SECTION               0x38001746#define mmQM_TENSOR_6_TPC0_CFG_BASE                0x7FFCE06B50ull1747#define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET            0x38001748#define QM_TENSOR_6_TPC0_CFG_SECTION               0x38001749#define mmQM_TENSOR_7_TPC0_CFG_BASE                0x7FFCE06B88ull1750#define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET            0x38001751#define QM_TENSOR_7_TPC0_CFG_SECTION               0x38001752#define mmQM_TENSOR_8_TPC0_CFG_BASE                0x7FFCE06BC0ull1753#define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET            0x38001754#define QM_TENSOR_8_TPC0_CFG_SECTION               0x38001755#define mmQM_TENSOR_9_TPC0_CFG_BASE                0x7FFCE06BF8ull1756#define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET            0x38001757#define QM_TENSOR_9_TPC0_CFG_SECTION               0x38001758#define mmQM_TENSOR_10_TPC0_CFG_BASE               0x7FFCE06C30ull1759#define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET           0x38001760#define QM_TENSOR_10_TPC0_CFG_SECTION              0x38001761#define mmQM_TENSOR_11_TPC0_CFG_BASE               0x7FFCE06C68ull1762#define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET           0x38001763#define QM_TENSOR_11_TPC0_CFG_SECTION              0x38001764#define mmQM_TENSOR_12_TPC0_CFG_BASE               0x7FFCE06CA0ull1765#define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET           0x38001766#define QM_TENSOR_12_TPC0_CFG_SECTION              0x38001767#define mmQM_TENSOR_13_TPC0_CFG_BASE               0x7FFCE06CD8ull1768#define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET           0x38001769#define QM_TENSOR_13_TPC0_CFG_SECTION              0x38001770#define mmQM_TENSOR_14_TPC0_CFG_BASE               0x7FFCE06D10ull1771#define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET           0x38001772#define QM_TENSOR_14_TPC0_CFG_SECTION              0x38001773#define mmQM_TENSOR_15_TPC0_CFG_BASE               0x7FFCE06D48ull1774#define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET           0x38001775#define QM_TENSOR_15_TPC0_CFG_SECTION              0x38001776#define mmQM_SYNC_OBJECT_TPC0_CFG_BASE             0x7FFCE06D80ull1777#define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET         0x80001778#define QM_SYNC_OBJECT_TPC0_CFG_SECTION            0x80001779#define mmQM_TPC0_CFG_BASE                         0x7FFCE06D88ull1780#define QM_TPC0_CFG_MAX_OFFSET                     0xB8001781#define QM_TPC0_CFG_SECTION                        0x27801782#define mmTPC0_E2E_CRED_BASE                       0x7FFCE07000ull1783#define TPC0_E2E_CRED_MAX_OFFSET                   0x16801784#define TPC0_E2E_CRED_SECTION                      0x10001785#define mmTPC0_QM_BASE                             0x7FFCE08000ull1786#define TPC0_QM_MAX_OFFSET                         0xD0401787#define TPC0_QM_SECTION                            0x3E0001788#define mmTPC1_CFG_BASE                            0x7FFCE46000ull1789#define TPC1_CFG_MAX_OFFSET                        0xE4001790#define TPC1_CFG_SECTION                           0x40001791#define mmKERNEL_TENSOR_0_TPC1_CFG_BASE            0x7FFCE46400ull1792#define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET        0x38001793#define KERNEL_TENSOR_0_TPC1_CFG_SECTION           0x38001794#define mmKERNEL_TENSOR_1_TPC1_CFG_BASE            0x7FFCE46438ull1795#define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET        0x38001796#define KERNEL_TENSOR_1_TPC1_CFG_SECTION           0x38001797#define mmKERNEL_TENSOR_2_TPC1_CFG_BASE            0x7FFCE46470ull1798#define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET        0x38001799#define KERNEL_TENSOR_2_TPC1_CFG_SECTION           0x38001800#define mmKERNEL_TENSOR_3_TPC1_CFG_BASE            0x7FFCE464A8ull1801#define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET        0x38001802#define KERNEL_TENSOR_3_TPC1_CFG_SECTION           0x38001803#define mmKERNEL_TENSOR_4_TPC1_CFG_BASE            0x7FFCE464E0ull1804#define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET        0x38001805#define KERNEL_TENSOR_4_TPC1_CFG_SECTION           0x38001806#define mmKERNEL_TENSOR_5_TPC1_CFG_BASE            0x7FFCE46518ull1807#define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET        0x38001808#define KERNEL_TENSOR_5_TPC1_CFG_SECTION           0x38001809#define mmKERNEL_TENSOR_6_TPC1_CFG_BASE            0x7FFCE46550ull1810#define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET        0x38001811#define KERNEL_TENSOR_6_TPC1_CFG_SECTION           0x38001812#define mmKERNEL_TENSOR_7_TPC1_CFG_BASE            0x7FFCE46588ull1813#define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET        0x38001814#define KERNEL_TENSOR_7_TPC1_CFG_SECTION           0x38001815#define mmKERNEL_TENSOR_8_TPC1_CFG_BASE            0x7FFCE465C0ull1816#define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET        0x38001817#define KERNEL_TENSOR_8_TPC1_CFG_SECTION           0x38001818#define mmKERNEL_TENSOR_9_TPC1_CFG_BASE            0x7FFCE465F8ull1819#define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET        0x38001820#define KERNEL_TENSOR_9_TPC1_CFG_SECTION           0x38001821#define mmKERNEL_TENSOR_10_TPC1_CFG_BASE           0x7FFCE46630ull1822#define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET       0x38001823#define KERNEL_TENSOR_10_TPC1_CFG_SECTION          0x38001824#define mmKERNEL_TENSOR_11_TPC1_CFG_BASE           0x7FFCE46668ull1825#define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET       0x38001826#define KERNEL_TENSOR_11_TPC1_CFG_SECTION          0x38001827#define mmKERNEL_TENSOR_12_TPC1_CFG_BASE           0x7FFCE466A0ull1828#define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET       0x38001829#define KERNEL_TENSOR_12_TPC1_CFG_SECTION          0x38001830#define mmKERNEL_TENSOR_13_TPC1_CFG_BASE           0x7FFCE466D8ull1831#define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET       0x38001832#define KERNEL_TENSOR_13_TPC1_CFG_SECTION          0x38001833#define mmKERNEL_TENSOR_14_TPC1_CFG_BASE           0x7FFCE46710ull1834#define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET       0x38001835#define KERNEL_TENSOR_14_TPC1_CFG_SECTION          0x38001836#define mmKERNEL_TENSOR_15_TPC1_CFG_BASE           0x7FFCE46748ull1837#define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET       0x38001838#define KERNEL_TENSOR_15_TPC1_CFG_SECTION          0x38001839#define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE         0x7FFCE46780ull1840#define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET     0x80001841#define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION        0x80001842#define mmKERNEL_TPC1_CFG_BASE                     0x7FFCE46788ull1843#define KERNEL_TPC1_CFG_MAX_OFFSET                 0xB8001844#define KERNEL_TPC1_CFG_SECTION                    0x27801845#define mmQM_TENSOR_0_TPC1_CFG_BASE                0x7FFCE46A00ull1846#define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET            0x38001847#define QM_TENSOR_0_TPC1_CFG_SECTION               0x38001848#define mmQM_TENSOR_1_TPC1_CFG_BASE                0x7FFCE46A38ull1849#define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET            0x38001850#define QM_TENSOR_1_TPC1_CFG_SECTION               0x38001851#define mmQM_TENSOR_2_TPC1_CFG_BASE                0x7FFCE46A70ull1852#define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET            0x38001853#define QM_TENSOR_2_TPC1_CFG_SECTION               0x38001854#define mmQM_TENSOR_3_TPC1_CFG_BASE                0x7FFCE46AA8ull1855#define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET            0x38001856#define QM_TENSOR_3_TPC1_CFG_SECTION               0x38001857#define mmQM_TENSOR_4_TPC1_CFG_BASE                0x7FFCE46AE0ull1858#define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET            0x38001859#define QM_TENSOR_4_TPC1_CFG_SECTION               0x38001860#define mmQM_TENSOR_5_TPC1_CFG_BASE                0x7FFCE46B18ull1861#define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET            0x38001862#define QM_TENSOR_5_TPC1_CFG_SECTION               0x38001863#define mmQM_TENSOR_6_TPC1_CFG_BASE                0x7FFCE46B50ull1864#define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET            0x38001865#define QM_TENSOR_6_TPC1_CFG_SECTION               0x38001866#define mmQM_TENSOR_7_TPC1_CFG_BASE                0x7FFCE46B88ull1867#define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET            0x38001868#define QM_TENSOR_7_TPC1_CFG_SECTION               0x38001869#define mmQM_TENSOR_8_TPC1_CFG_BASE                0x7FFCE46BC0ull1870#define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET            0x38001871#define QM_TENSOR_8_TPC1_CFG_SECTION               0x38001872#define mmQM_TENSOR_9_TPC1_CFG_BASE                0x7FFCE46BF8ull1873#define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET            0x38001874#define QM_TENSOR_9_TPC1_CFG_SECTION               0x38001875#define mmQM_TENSOR_10_TPC1_CFG_BASE               0x7FFCE46C30ull1876#define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET           0x38001877#define QM_TENSOR_10_TPC1_CFG_SECTION              0x38001878#define mmQM_TENSOR_11_TPC1_CFG_BASE               0x7FFCE46C68ull1879#define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET           0x38001880#define QM_TENSOR_11_TPC1_CFG_SECTION              0x38001881#define mmQM_TENSOR_12_TPC1_CFG_BASE               0x7FFCE46CA0ull1882#define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET           0x38001883#define QM_TENSOR_12_TPC1_CFG_SECTION              0x38001884#define mmQM_TENSOR_13_TPC1_CFG_BASE               0x7FFCE46CD8ull1885#define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET           0x38001886#define QM_TENSOR_13_TPC1_CFG_SECTION              0x38001887#define mmQM_TENSOR_14_TPC1_CFG_BASE               0x7FFCE46D10ull1888#define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET           0x38001889#define QM_TENSOR_14_TPC1_CFG_SECTION              0x38001890#define mmQM_TENSOR_15_TPC1_CFG_BASE               0x7FFCE46D48ull1891#define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET           0x38001892#define QM_TENSOR_15_TPC1_CFG_SECTION              0x38001893#define mmQM_SYNC_OBJECT_TPC1_CFG_BASE             0x7FFCE46D80ull1894#define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET         0x80001895#define QM_SYNC_OBJECT_TPC1_CFG_SECTION            0x80001896#define mmQM_TPC1_CFG_BASE                         0x7FFCE46D88ull1897#define QM_TPC1_CFG_MAX_OFFSET                     0xB8001898#define QM_TPC1_CFG_SECTION                        0x27801899#define mmTPC1_E2E_CRED_BASE                       0x7FFCE47000ull1900#define TPC1_E2E_CRED_MAX_OFFSET                   0x16801901#define TPC1_E2E_CRED_SECTION                      0x10001902#define mmTPC1_QM_BASE                             0x7FFCE48000ull1903#define TPC1_QM_MAX_OFFSET                         0xD0401904#define TPC1_QM_SECTION                            0x3E0001905#define mmTPC2_CFG_BASE                            0x7FFCE86000ull1906#define TPC2_CFG_MAX_OFFSET                        0xE4001907#define TPC2_CFG_SECTION                           0x40001908#define mmKERNEL_TENSOR_0_TPC2_CFG_BASE            0x7FFCE86400ull1909#define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET        0x38001910#define KERNEL_TENSOR_0_TPC2_CFG_SECTION           0x38001911#define mmKERNEL_TENSOR_1_TPC2_CFG_BASE            0x7FFCE86438ull1912#define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET        0x38001913#define KERNEL_TENSOR_1_TPC2_CFG_SECTION           0x38001914#define mmKERNEL_TENSOR_2_TPC2_CFG_BASE            0x7FFCE86470ull1915#define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET        0x38001916#define KERNEL_TENSOR_2_TPC2_CFG_SECTION           0x38001917#define mmKERNEL_TENSOR_3_TPC2_CFG_BASE            0x7FFCE864A8ull1918#define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET        0x38001919#define KERNEL_TENSOR_3_TPC2_CFG_SECTION           0x38001920#define mmKERNEL_TENSOR_4_TPC2_CFG_BASE            0x7FFCE864E0ull1921#define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET        0x38001922#define KERNEL_TENSOR_4_TPC2_CFG_SECTION           0x38001923#define mmKERNEL_TENSOR_5_TPC2_CFG_BASE            0x7FFCE86518ull1924#define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET        0x38001925#define KERNEL_TENSOR_5_TPC2_CFG_SECTION           0x38001926#define mmKERNEL_TENSOR_6_TPC2_CFG_BASE            0x7FFCE86550ull1927#define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET        0x38001928#define KERNEL_TENSOR_6_TPC2_CFG_SECTION           0x38001929#define mmKERNEL_TENSOR_7_TPC2_CFG_BASE            0x7FFCE86588ull1930#define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET        0x38001931#define KERNEL_TENSOR_7_TPC2_CFG_SECTION           0x38001932#define mmKERNEL_TENSOR_8_TPC2_CFG_BASE            0x7FFCE865C0ull1933#define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET        0x38001934#define KERNEL_TENSOR_8_TPC2_CFG_SECTION           0x38001935#define mmKERNEL_TENSOR_9_TPC2_CFG_BASE            0x7FFCE865F8ull1936#define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET        0x38001937#define KERNEL_TENSOR_9_TPC2_CFG_SECTION           0x38001938#define mmKERNEL_TENSOR_10_TPC2_CFG_BASE           0x7FFCE86630ull1939#define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET       0x38001940#define KERNEL_TENSOR_10_TPC2_CFG_SECTION          0x38001941#define mmKERNEL_TENSOR_11_TPC2_CFG_BASE           0x7FFCE86668ull1942#define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET       0x38001943#define KERNEL_TENSOR_11_TPC2_CFG_SECTION          0x38001944#define mmKERNEL_TENSOR_12_TPC2_CFG_BASE           0x7FFCE866A0ull1945#define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET       0x38001946#define KERNEL_TENSOR_12_TPC2_CFG_SECTION          0x38001947#define mmKERNEL_TENSOR_13_TPC2_CFG_BASE           0x7FFCE866D8ull1948#define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET       0x38001949#define KERNEL_TENSOR_13_TPC2_CFG_SECTION          0x38001950#define mmKERNEL_TENSOR_14_TPC2_CFG_BASE           0x7FFCE86710ull1951#define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET       0x38001952#define KERNEL_TENSOR_14_TPC2_CFG_SECTION          0x38001953#define mmKERNEL_TENSOR_15_TPC2_CFG_BASE           0x7FFCE86748ull1954#define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET       0x38001955#define KERNEL_TENSOR_15_TPC2_CFG_SECTION          0x38001956#define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE         0x7FFCE86780ull1957#define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET     0x80001958#define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION        0x80001959#define mmKERNEL_TPC2_CFG_BASE                     0x7FFCE86788ull1960#define KERNEL_TPC2_CFG_MAX_OFFSET                 0xB8001961#define KERNEL_TPC2_CFG_SECTION                    0x27801962#define mmQM_TENSOR_0_TPC2_CFG_BASE                0x7FFCE86A00ull1963#define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET            0x38001964#define QM_TENSOR_0_TPC2_CFG_SECTION               0x38001965#define mmQM_TENSOR_1_TPC2_CFG_BASE                0x7FFCE86A38ull1966#define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET            0x38001967#define QM_TENSOR_1_TPC2_CFG_SECTION               0x38001968#define mmQM_TENSOR_2_TPC2_CFG_BASE                0x7FFCE86A70ull1969#define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET            0x38001970#define QM_TENSOR_2_TPC2_CFG_SECTION               0x38001971#define mmQM_TENSOR_3_TPC2_CFG_BASE                0x7FFCE86AA8ull1972#define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET            0x38001973#define QM_TENSOR_3_TPC2_CFG_SECTION               0x38001974#define mmQM_TENSOR_4_TPC2_CFG_BASE                0x7FFCE86AE0ull1975#define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET            0x38001976#define QM_TENSOR_4_TPC2_CFG_SECTION               0x38001977#define mmQM_TENSOR_5_TPC2_CFG_BASE                0x7FFCE86B18ull1978#define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET            0x38001979#define QM_TENSOR_5_TPC2_CFG_SECTION               0x38001980#define mmQM_TENSOR_6_TPC2_CFG_BASE                0x7FFCE86B50ull1981#define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET            0x38001982#define QM_TENSOR_6_TPC2_CFG_SECTION               0x38001983#define mmQM_TENSOR_7_TPC2_CFG_BASE                0x7FFCE86B88ull1984#define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET            0x38001985#define QM_TENSOR_7_TPC2_CFG_SECTION               0x38001986#define mmQM_TENSOR_8_TPC2_CFG_BASE                0x7FFCE86BC0ull1987#define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET            0x38001988#define QM_TENSOR_8_TPC2_CFG_SECTION               0x38001989#define mmQM_TENSOR_9_TPC2_CFG_BASE                0x7FFCE86BF8ull1990#define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET            0x38001991#define QM_TENSOR_9_TPC2_CFG_SECTION               0x38001992#define mmQM_TENSOR_10_TPC2_CFG_BASE               0x7FFCE86C30ull1993#define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET           0x38001994#define QM_TENSOR_10_TPC2_CFG_SECTION              0x38001995#define mmQM_TENSOR_11_TPC2_CFG_BASE               0x7FFCE86C68ull1996#define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET           0x38001997#define QM_TENSOR_11_TPC2_CFG_SECTION              0x38001998#define mmQM_TENSOR_12_TPC2_CFG_BASE               0x7FFCE86CA0ull1999#define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET           0x38002000#define QM_TENSOR_12_TPC2_CFG_SECTION              0x38002001#define mmQM_TENSOR_13_TPC2_CFG_BASE               0x7FFCE86CD8ull2002#define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET           0x38002003#define QM_TENSOR_13_TPC2_CFG_SECTION              0x38002004#define mmQM_TENSOR_14_TPC2_CFG_BASE               0x7FFCE86D10ull2005#define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET           0x38002006#define QM_TENSOR_14_TPC2_CFG_SECTION              0x38002007#define mmQM_TENSOR_15_TPC2_CFG_BASE               0x7FFCE86D48ull2008#define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET           0x38002009#define QM_TENSOR_15_TPC2_CFG_SECTION              0x38002010#define mmQM_SYNC_OBJECT_TPC2_CFG_BASE             0x7FFCE86D80ull2011#define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET         0x80002012#define QM_SYNC_OBJECT_TPC2_CFG_SECTION            0x80002013#define mmQM_TPC2_CFG_BASE                         0x7FFCE86D88ull2014#define QM_TPC2_CFG_MAX_OFFSET                     0xB8002015#define QM_TPC2_CFG_SECTION                        0x27802016#define mmTPC2_E2E_CRED_BASE                       0x7FFCE87000ull2017#define TPC2_E2E_CRED_MAX_OFFSET                   0x16802018#define TPC2_E2E_CRED_SECTION                      0x10002019#define mmTPC2_QM_BASE                             0x7FFCE88000ull2020#define TPC2_QM_MAX_OFFSET                         0xD0402021#define TPC2_QM_SECTION                            0x3E0002022#define mmTPC3_CFG_BASE                            0x7FFCEC6000ull2023#define TPC3_CFG_MAX_OFFSET                        0xE4002024#define TPC3_CFG_SECTION                           0x40002025#define mmKERNEL_TENSOR_0_TPC3_CFG_BASE            0x7FFCEC6400ull2026#define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET        0x38002027#define KERNEL_TENSOR_0_TPC3_CFG_SECTION           0x38002028#define mmKERNEL_TENSOR_1_TPC3_CFG_BASE            0x7FFCEC6438ull2029#define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET        0x38002030#define KERNEL_TENSOR_1_TPC3_CFG_SECTION           0x38002031#define mmKERNEL_TENSOR_2_TPC3_CFG_BASE            0x7FFCEC6470ull2032#define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET        0x38002033#define KERNEL_TENSOR_2_TPC3_CFG_SECTION           0x38002034#define mmKERNEL_TENSOR_3_TPC3_CFG_BASE            0x7FFCEC64A8ull2035#define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET        0x38002036#define KERNEL_TENSOR_3_TPC3_CFG_SECTION           0x38002037#define mmKERNEL_TENSOR_4_TPC3_CFG_BASE            0x7FFCEC64E0ull2038#define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET        0x38002039#define KERNEL_TENSOR_4_TPC3_CFG_SECTION           0x38002040#define mmKERNEL_TENSOR_5_TPC3_CFG_BASE            0x7FFCEC6518ull2041#define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET        0x38002042#define KERNEL_TENSOR_5_TPC3_CFG_SECTION           0x38002043#define mmKERNEL_TENSOR_6_TPC3_CFG_BASE            0x7FFCEC6550ull2044#define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET        0x38002045#define KERNEL_TENSOR_6_TPC3_CFG_SECTION           0x38002046#define mmKERNEL_TENSOR_7_TPC3_CFG_BASE            0x7FFCEC6588ull2047#define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET        0x38002048#define KERNEL_TENSOR_7_TPC3_CFG_SECTION           0x38002049#define mmKERNEL_TENSOR_8_TPC3_CFG_BASE            0x7FFCEC65C0ull2050#define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET        0x38002051#define KERNEL_TENSOR_8_TPC3_CFG_SECTION           0x38002052#define mmKERNEL_TENSOR_9_TPC3_CFG_BASE            0x7FFCEC65F8ull2053#define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET        0x38002054#define KERNEL_TENSOR_9_TPC3_CFG_SECTION           0x38002055#define mmKERNEL_TENSOR_10_TPC3_CFG_BASE           0x7FFCEC6630ull2056#define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET       0x38002057#define KERNEL_TENSOR_10_TPC3_CFG_SECTION          0x38002058#define mmKERNEL_TENSOR_11_TPC3_CFG_BASE           0x7FFCEC6668ull2059#define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET       0x38002060#define KERNEL_TENSOR_11_TPC3_CFG_SECTION          0x38002061#define mmKERNEL_TENSOR_12_TPC3_CFG_BASE           0x7FFCEC66A0ull2062#define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET       0x38002063#define KERNEL_TENSOR_12_TPC3_CFG_SECTION          0x38002064#define mmKERNEL_TENSOR_13_TPC3_CFG_BASE           0x7FFCEC66D8ull2065#define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET       0x38002066#define KERNEL_TENSOR_13_TPC3_CFG_SECTION          0x38002067#define mmKERNEL_TENSOR_14_TPC3_CFG_BASE           0x7FFCEC6710ull2068#define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET       0x38002069#define KERNEL_TENSOR_14_TPC3_CFG_SECTION          0x38002070#define mmKERNEL_TENSOR_15_TPC3_CFG_BASE           0x7FFCEC6748ull2071#define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET       0x38002072#define KERNEL_TENSOR_15_TPC3_CFG_SECTION          0x38002073#define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE         0x7FFCEC6780ull2074#define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET     0x80002075#define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION        0x80002076#define mmKERNEL_TPC3_CFG_BASE                     0x7FFCEC6788ull2077#define KERNEL_TPC3_CFG_MAX_OFFSET                 0xB8002078#define KERNEL_TPC3_CFG_SECTION                    0x27802079#define mmQM_TENSOR_0_TPC3_CFG_BASE                0x7FFCEC6A00ull2080#define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET            0x38002081#define QM_TENSOR_0_TPC3_CFG_SECTION               0x38002082#define mmQM_TENSOR_1_TPC3_CFG_BASE                0x7FFCEC6A38ull2083#define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET            0x38002084#define QM_TENSOR_1_TPC3_CFG_SECTION               0x38002085#define mmQM_TENSOR_2_TPC3_CFG_BASE                0x7FFCEC6A70ull2086#define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET            0x38002087#define QM_TENSOR_2_TPC3_CFG_SECTION               0x38002088#define mmQM_TENSOR_3_TPC3_CFG_BASE                0x7FFCEC6AA8ull2089#define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET            0x38002090#define QM_TENSOR_3_TPC3_CFG_SECTION               0x38002091#define mmQM_TENSOR_4_TPC3_CFG_BASE                0x7FFCEC6AE0ull2092#define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET            0x38002093#define QM_TENSOR_4_TPC3_CFG_SECTION               0x38002094#define mmQM_TENSOR_5_TPC3_CFG_BASE                0x7FFCEC6B18ull2095#define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET            0x38002096#define QM_TENSOR_5_TPC3_CFG_SECTION               0x38002097#define mmQM_TENSOR_6_TPC3_CFG_BASE                0x7FFCEC6B50ull2098#define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET            0x38002099#define QM_TENSOR_6_TPC3_CFG_SECTION               0x38002100#define mmQM_TENSOR_7_TPC3_CFG_BASE                0x7FFCEC6B88ull2101#define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET            0x38002102#define QM_TENSOR_7_TPC3_CFG_SECTION               0x38002103#define mmQM_TENSOR_8_TPC3_CFG_BASE                0x7FFCEC6BC0ull2104#define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET            0x38002105#define QM_TENSOR_8_TPC3_CFG_SECTION               0x38002106#define mmQM_TENSOR_9_TPC3_CFG_BASE                0x7FFCEC6BF8ull2107#define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET            0x38002108#define QM_TENSOR_9_TPC3_CFG_SECTION               0x38002109#define mmQM_TENSOR_10_TPC3_CFG_BASE               0x7FFCEC6C30ull2110#define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET           0x38002111#define QM_TENSOR_10_TPC3_CFG_SECTION              0x38002112#define mmQM_TENSOR_11_TPC3_CFG_BASE               0x7FFCEC6C68ull2113#define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET           0x38002114#define QM_TENSOR_11_TPC3_CFG_SECTION              0x38002115#define mmQM_TENSOR_12_TPC3_CFG_BASE               0x7FFCEC6CA0ull2116#define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET           0x38002117#define QM_TENSOR_12_TPC3_CFG_SECTION              0x38002118#define mmQM_TENSOR_13_TPC3_CFG_BASE               0x7FFCEC6CD8ull2119#define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET           0x38002120#define QM_TENSOR_13_TPC3_CFG_SECTION              0x38002121#define mmQM_TENSOR_14_TPC3_CFG_BASE               0x7FFCEC6D10ull2122#define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET           0x38002123#define QM_TENSOR_14_TPC3_CFG_SECTION              0x38002124#define mmQM_TENSOR_15_TPC3_CFG_BASE               0x7FFCEC6D48ull2125#define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET           0x38002126#define QM_TENSOR_15_TPC3_CFG_SECTION              0x38002127#define mmQM_SYNC_OBJECT_TPC3_CFG_BASE             0x7FFCEC6D80ull2128#define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET         0x80002129#define QM_SYNC_OBJECT_TPC3_CFG_SECTION            0x80002130#define mmQM_TPC3_CFG_BASE                         0x7FFCEC6D88ull2131#define QM_TPC3_CFG_MAX_OFFSET                     0xB8002132#define QM_TPC3_CFG_SECTION                        0x27802133#define mmTPC3_E2E_CRED_BASE                       0x7FFCEC7000ull2134#define TPC3_E2E_CRED_MAX_OFFSET                   0x16802135#define TPC3_E2E_CRED_SECTION                      0x10002136#define mmTPC3_QM_BASE                             0x7FFCEC8000ull2137#define TPC3_QM_MAX_OFFSET                         0xD0402138#define TPC3_QM_SECTION                            0x3E0002139#define mmTPC4_CFG_BASE                            0x7FFCF06000ull2140#define TPC4_CFG_MAX_OFFSET                        0xE4002141#define TPC4_CFG_SECTION                           0x40002142#define mmKERNEL_TENSOR_0_TPC4_CFG_BASE            0x7FFCF06400ull2143#define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET        0x38002144#define KERNEL_TENSOR_0_TPC4_CFG_SECTION           0x38002145#define mmKERNEL_TENSOR_1_TPC4_CFG_BASE            0x7FFCF06438ull2146#define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET        0x38002147#define KERNEL_TENSOR_1_TPC4_CFG_SECTION           0x38002148#define mmKERNEL_TENSOR_2_TPC4_CFG_BASE            0x7FFCF06470ull2149#define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET        0x38002150#define KERNEL_TENSOR_2_TPC4_CFG_SECTION           0x38002151#define mmKERNEL_TENSOR_3_TPC4_CFG_BASE            0x7FFCF064A8ull2152#define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET        0x38002153#define KERNEL_TENSOR_3_TPC4_CFG_SECTION           0x38002154#define mmKERNEL_TENSOR_4_TPC4_CFG_BASE            0x7FFCF064E0ull2155#define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET        0x38002156#define KERNEL_TENSOR_4_TPC4_CFG_SECTION           0x38002157#define mmKERNEL_TENSOR_5_TPC4_CFG_BASE            0x7FFCF06518ull2158#define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET        0x38002159#define KERNEL_TENSOR_5_TPC4_CFG_SECTION           0x38002160#define mmKERNEL_TENSOR_6_TPC4_CFG_BASE            0x7FFCF06550ull2161#define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET        0x38002162#define KERNEL_TENSOR_6_TPC4_CFG_SECTION           0x38002163#define mmKERNEL_TENSOR_7_TPC4_CFG_BASE            0x7FFCF06588ull2164#define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET        0x38002165#define KERNEL_TENSOR_7_TPC4_CFG_SECTION           0x38002166#define mmKERNEL_TENSOR_8_TPC4_CFG_BASE            0x7FFCF065C0ull2167#define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET        0x38002168#define KERNEL_TENSOR_8_TPC4_CFG_SECTION           0x38002169#define mmKERNEL_TENSOR_9_TPC4_CFG_BASE            0x7FFCF065F8ull2170#define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET        0x38002171#define KERNEL_TENSOR_9_TPC4_CFG_SECTION           0x38002172#define mmKERNEL_TENSOR_10_TPC4_CFG_BASE           0x7FFCF06630ull2173#define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET       0x38002174#define KERNEL_TENSOR_10_TPC4_CFG_SECTION          0x38002175#define mmKERNEL_TENSOR_11_TPC4_CFG_BASE           0x7FFCF06668ull2176#define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET       0x38002177#define KERNEL_TENSOR_11_TPC4_CFG_SECTION          0x38002178#define mmKERNEL_TENSOR_12_TPC4_CFG_BASE           0x7FFCF066A0ull2179#define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET       0x38002180#define KERNEL_TENSOR_12_TPC4_CFG_SECTION          0x38002181#define mmKERNEL_TENSOR_13_TPC4_CFG_BASE           0x7FFCF066D8ull2182#define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET       0x38002183#define KERNEL_TENSOR_13_TPC4_CFG_SECTION          0x38002184#define mmKERNEL_TENSOR_14_TPC4_CFG_BASE           0x7FFCF06710ull2185#define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET       0x38002186#define KERNEL_TENSOR_14_TPC4_CFG_SECTION          0x38002187#define mmKERNEL_TENSOR_15_TPC4_CFG_BASE           0x7FFCF06748ull2188#define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET       0x38002189#define KERNEL_TENSOR_15_TPC4_CFG_SECTION          0x38002190#define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE         0x7FFCF06780ull2191#define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET     0x80002192#define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION        0x80002193#define mmKERNEL_TPC4_CFG_BASE                     0x7FFCF06788ull2194#define KERNEL_TPC4_CFG_MAX_OFFSET                 0xB8002195#define KERNEL_TPC4_CFG_SECTION                    0x27802196#define mmQM_TENSOR_0_TPC4_CFG_BASE                0x7FFCF06A00ull2197#define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET            0x38002198#define QM_TENSOR_0_TPC4_CFG_SECTION               0x38002199#define mmQM_TENSOR_1_TPC4_CFG_BASE                0x7FFCF06A38ull2200#define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET            0x38002201#define QM_TENSOR_1_TPC4_CFG_SECTION               0x38002202#define mmQM_TENSOR_2_TPC4_CFG_BASE                0x7FFCF06A70ull2203#define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET            0x38002204#define QM_TENSOR_2_TPC4_CFG_SECTION               0x38002205#define mmQM_TENSOR_3_TPC4_CFG_BASE                0x7FFCF06AA8ull2206#define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET            0x38002207#define QM_TENSOR_3_TPC4_CFG_SECTION               0x38002208#define mmQM_TENSOR_4_TPC4_CFG_BASE                0x7FFCF06AE0ull2209#define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET            0x38002210#define QM_TENSOR_4_TPC4_CFG_SECTION               0x38002211#define mmQM_TENSOR_5_TPC4_CFG_BASE                0x7FFCF06B18ull2212#define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET            0x38002213#define QM_TENSOR_5_TPC4_CFG_SECTION               0x38002214#define mmQM_TENSOR_6_TPC4_CFG_BASE                0x7FFCF06B50ull2215#define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET            0x38002216#define QM_TENSOR_6_TPC4_CFG_SECTION               0x38002217#define mmQM_TENSOR_7_TPC4_CFG_BASE                0x7FFCF06B88ull2218#define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET            0x38002219#define QM_TENSOR_7_TPC4_CFG_SECTION               0x38002220#define mmQM_TENSOR_8_TPC4_CFG_BASE                0x7FFCF06BC0ull2221#define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET            0x38002222#define QM_TENSOR_8_TPC4_CFG_SECTION               0x38002223#define mmQM_TENSOR_9_TPC4_CFG_BASE                0x7FFCF06BF8ull2224#define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET            0x38002225#define QM_TENSOR_9_TPC4_CFG_SECTION               0x38002226#define mmQM_TENSOR_10_TPC4_CFG_BASE               0x7FFCF06C30ull2227#define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET           0x38002228#define QM_TENSOR_10_TPC4_CFG_SECTION              0x38002229#define mmQM_TENSOR_11_TPC4_CFG_BASE               0x7FFCF06C68ull2230#define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET           0x38002231#define QM_TENSOR_11_TPC4_CFG_SECTION              0x38002232#define mmQM_TENSOR_12_TPC4_CFG_BASE               0x7FFCF06CA0ull2233#define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET           0x38002234#define QM_TENSOR_12_TPC4_CFG_SECTION              0x38002235#define mmQM_TENSOR_13_TPC4_CFG_BASE               0x7FFCF06CD8ull2236#define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET           0x38002237#define QM_TENSOR_13_TPC4_CFG_SECTION              0x38002238#define mmQM_TENSOR_14_TPC4_CFG_BASE               0x7FFCF06D10ull2239#define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET           0x38002240#define QM_TENSOR_14_TPC4_CFG_SECTION              0x38002241#define mmQM_TENSOR_15_TPC4_CFG_BASE               0x7FFCF06D48ull2242#define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET           0x38002243#define QM_TENSOR_15_TPC4_CFG_SECTION              0x38002244#define mmQM_SYNC_OBJECT_TPC4_CFG_BASE             0x7FFCF06D80ull2245#define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET         0x80002246#define QM_SYNC_OBJECT_TPC4_CFG_SECTION            0x80002247#define mmQM_TPC4_CFG_BASE                         0x7FFCF06D88ull2248#define QM_TPC4_CFG_MAX_OFFSET                     0xB8002249#define QM_TPC4_CFG_SECTION                        0x27802250#define mmTPC4_E2E_CRED_BASE                       0x7FFCF07000ull2251#define TPC4_E2E_CRED_MAX_OFFSET                   0x16802252#define TPC4_E2E_CRED_SECTION                      0x10002253#define mmTPC4_QM_BASE                             0x7FFCF08000ull2254#define TPC4_QM_MAX_OFFSET                         0xD0402255#define TPC4_QM_SECTION                            0x3E0002256#define mmTPC5_CFG_BASE                            0x7FFCF46000ull2257#define TPC5_CFG_MAX_OFFSET                        0xE4002258#define TPC5_CFG_SECTION                           0x40002259#define mmKERNEL_TENSOR_0_TPC5_CFG_BASE            0x7FFCF46400ull2260#define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET        0x38002261#define KERNEL_TENSOR_0_TPC5_CFG_SECTION           0x38002262#define mmKERNEL_TENSOR_1_TPC5_CFG_BASE            0x7FFCF46438ull2263#define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET        0x38002264#define KERNEL_TENSOR_1_TPC5_CFG_SECTION           0x38002265#define mmKERNEL_TENSOR_2_TPC5_CFG_BASE            0x7FFCF46470ull2266#define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET        0x38002267#define KERNEL_TENSOR_2_TPC5_CFG_SECTION           0x38002268#define mmKERNEL_TENSOR_3_TPC5_CFG_BASE            0x7FFCF464A8ull2269#define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET        0x38002270#define KERNEL_TENSOR_3_TPC5_CFG_SECTION           0x38002271#define mmKERNEL_TENSOR_4_TPC5_CFG_BASE            0x7FFCF464E0ull2272#define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET        0x38002273#define KERNEL_TENSOR_4_TPC5_CFG_SECTION           0x38002274#define mmKERNEL_TENSOR_5_TPC5_CFG_BASE            0x7FFCF46518ull2275#define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET        0x38002276#define KERNEL_TENSOR_5_TPC5_CFG_SECTION           0x38002277#define mmKERNEL_TENSOR_6_TPC5_CFG_BASE            0x7FFCF46550ull2278#define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET        0x38002279#define KERNEL_TENSOR_6_TPC5_CFG_SECTION           0x38002280#define mmKERNEL_TENSOR_7_TPC5_CFG_BASE            0x7FFCF46588ull2281#define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET        0x38002282#define KERNEL_TENSOR_7_TPC5_CFG_SECTION           0x38002283#define mmKERNEL_TENSOR_8_TPC5_CFG_BASE            0x7FFCF465C0ull2284#define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET        0x38002285#define KERNEL_TENSOR_8_TPC5_CFG_SECTION           0x38002286#define mmKERNEL_TENSOR_9_TPC5_CFG_BASE            0x7FFCF465F8ull2287#define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET        0x38002288#define KERNEL_TENSOR_9_TPC5_CFG_SECTION           0x38002289#define mmKERNEL_TENSOR_10_TPC5_CFG_BASE           0x7FFCF46630ull2290#define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET       0x38002291#define KERNEL_TENSOR_10_TPC5_CFG_SECTION          0x38002292#define mmKERNEL_TENSOR_11_TPC5_CFG_BASE           0x7FFCF46668ull2293#define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET       0x38002294#define KERNEL_TENSOR_11_TPC5_CFG_SECTION          0x38002295#define mmKERNEL_TENSOR_12_TPC5_CFG_BASE           0x7FFCF466A0ull2296#define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET       0x38002297#define KERNEL_TENSOR_12_TPC5_CFG_SECTION          0x38002298#define mmKERNEL_TENSOR_13_TPC5_CFG_BASE           0x7FFCF466D8ull2299#define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET       0x38002300#define KERNEL_TENSOR_13_TPC5_CFG_SECTION          0x38002301#define mmKERNEL_TENSOR_14_TPC5_CFG_BASE           0x7FFCF46710ull2302#define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET       0x38002303#define KERNEL_TENSOR_14_TPC5_CFG_SECTION          0x38002304#define mmKERNEL_TENSOR_15_TPC5_CFG_BASE           0x7FFCF46748ull2305#define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET       0x38002306#define KERNEL_TENSOR_15_TPC5_CFG_SECTION          0x38002307#define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE         0x7FFCF46780ull2308#define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET     0x80002309#define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION        0x80002310#define mmKERNEL_TPC5_CFG_BASE                     0x7FFCF46788ull2311#define KERNEL_TPC5_CFG_MAX_OFFSET                 0xB8002312#define KERNEL_TPC5_CFG_SECTION                    0x27802313#define mmQM_TENSOR_0_TPC5_CFG_BASE                0x7FFCF46A00ull2314#define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET            0x38002315#define QM_TENSOR_0_TPC5_CFG_SECTION               0x38002316#define mmQM_TENSOR_1_TPC5_CFG_BASE                0x7FFCF46A38ull2317#define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET            0x38002318#define QM_TENSOR_1_TPC5_CFG_SECTION               0x38002319#define mmQM_TENSOR_2_TPC5_CFG_BASE                0x7FFCF46A70ull2320#define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET            0x38002321#define QM_TENSOR_2_TPC5_CFG_SECTION               0x38002322#define mmQM_TENSOR_3_TPC5_CFG_BASE                0x7FFCF46AA8ull2323#define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET            0x38002324#define QM_TENSOR_3_TPC5_CFG_SECTION               0x38002325#define mmQM_TENSOR_4_TPC5_CFG_BASE                0x7FFCF46AE0ull2326#define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET            0x38002327#define QM_TENSOR_4_TPC5_CFG_SECTION               0x38002328#define mmQM_TENSOR_5_TPC5_CFG_BASE                0x7FFCF46B18ull2329#define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET            0x38002330#define QM_TENSOR_5_TPC5_CFG_SECTION               0x38002331#define mmQM_TENSOR_6_TPC5_CFG_BASE                0x7FFCF46B50ull2332#define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET            0x38002333#define QM_TENSOR_6_TPC5_CFG_SECTION               0x38002334#define mmQM_TENSOR_7_TPC5_CFG_BASE                0x7FFCF46B88ull2335#define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET            0x38002336#define QM_TENSOR_7_TPC5_CFG_SECTION               0x38002337#define mmQM_TENSOR_8_TPC5_CFG_BASE                0x7FFCF46BC0ull2338#define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET            0x38002339#define QM_TENSOR_8_TPC5_CFG_SECTION               0x38002340#define mmQM_TENSOR_9_TPC5_CFG_BASE                0x7FFCF46BF8ull2341#define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET            0x38002342#define QM_TENSOR_9_TPC5_CFG_SECTION               0x38002343#define mmQM_TENSOR_10_TPC5_CFG_BASE               0x7FFCF46C30ull2344#define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET           0x38002345#define QM_TENSOR_10_TPC5_CFG_SECTION              0x38002346#define mmQM_TENSOR_11_TPC5_CFG_BASE               0x7FFCF46C68ull2347#define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET           0x38002348#define QM_TENSOR_11_TPC5_CFG_SECTION              0x38002349#define mmQM_TENSOR_12_TPC5_CFG_BASE               0x7FFCF46CA0ull2350#define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET           0x38002351#define QM_TENSOR_12_TPC5_CFG_SECTION              0x38002352#define mmQM_TENSOR_13_TPC5_CFG_BASE               0x7FFCF46CD8ull2353#define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET           0x38002354#define QM_TENSOR_13_TPC5_CFG_SECTION              0x38002355#define mmQM_TENSOR_14_TPC5_CFG_BASE               0x7FFCF46D10ull2356#define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET           0x38002357#define QM_TENSOR_14_TPC5_CFG_SECTION              0x38002358#define mmQM_TENSOR_15_TPC5_CFG_BASE               0x7FFCF46D48ull2359#define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET           0x38002360#define QM_TENSOR_15_TPC5_CFG_SECTION              0x38002361#define mmQM_SYNC_OBJECT_TPC5_CFG_BASE             0x7FFCF46D80ull2362#define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET         0x80002363#define QM_SYNC_OBJECT_TPC5_CFG_SECTION            0x80002364#define mmQM_TPC5_CFG_BASE                         0x7FFCF46D88ull2365#define QM_TPC5_CFG_MAX_OFFSET                     0xB8002366#define QM_TPC5_CFG_SECTION                        0x27802367#define mmTPC5_E2E_CRED_BASE                       0x7FFCF47000ull2368#define TPC5_E2E_CRED_MAX_OFFSET                   0x16802369#define TPC5_E2E_CRED_SECTION                      0x10002370#define mmTPC5_QM_BASE                             0x7FFCF48000ull2371#define TPC5_QM_MAX_OFFSET                         0xD0402372#define TPC5_QM_SECTION                            0x3E0002373#define mmTPC6_CFG_BASE                            0x7FFCF86000ull2374#define TPC6_CFG_MAX_OFFSET                        0xE4002375#define TPC6_CFG_SECTION                           0x40002376#define mmKERNEL_TENSOR_0_TPC6_CFG_BASE            0x7FFCF86400ull2377#define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET        0x38002378#define KERNEL_TENSOR_0_TPC6_CFG_SECTION           0x38002379#define mmKERNEL_TENSOR_1_TPC6_CFG_BASE            0x7FFCF86438ull2380#define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET        0x38002381#define KERNEL_TENSOR_1_TPC6_CFG_SECTION           0x38002382#define mmKERNEL_TENSOR_2_TPC6_CFG_BASE            0x7FFCF86470ull2383#define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET        0x38002384#define KERNEL_TENSOR_2_TPC6_CFG_SECTION           0x38002385#define mmKERNEL_TENSOR_3_TPC6_CFG_BASE            0x7FFCF864A8ull2386#define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET        0x38002387#define KERNEL_TENSOR_3_TPC6_CFG_SECTION           0x38002388#define mmKERNEL_TENSOR_4_TPC6_CFG_BASE            0x7FFCF864E0ull2389#define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET        0x38002390#define KERNEL_TENSOR_4_TPC6_CFG_SECTION           0x38002391#define mmKERNEL_TENSOR_5_TPC6_CFG_BASE            0x7FFCF86518ull2392#define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET        0x38002393#define KERNEL_TENSOR_5_TPC6_CFG_SECTION           0x38002394#define mmKERNEL_TENSOR_6_TPC6_CFG_BASE            0x7FFCF86550ull2395#define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET        0x38002396#define KERNEL_TENSOR_6_TPC6_CFG_SECTION           0x38002397#define mmKERNEL_TENSOR_7_TPC6_CFG_BASE            0x7FFCF86588ull2398#define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET        0x38002399#define KERNEL_TENSOR_7_TPC6_CFG_SECTION           0x38002400#define mmKERNEL_TENSOR_8_TPC6_CFG_BASE            0x7FFCF865C0ull2401#define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET        0x38002402#define KERNEL_TENSOR_8_TPC6_CFG_SECTION           0x38002403#define mmKERNEL_TENSOR_9_TPC6_CFG_BASE            0x7FFCF865F8ull2404#define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET        0x38002405#define KERNEL_TENSOR_9_TPC6_CFG_SECTION           0x38002406#define mmKERNEL_TENSOR_10_TPC6_CFG_BASE           0x7FFCF86630ull2407#define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET       0x38002408#define KERNEL_TENSOR_10_TPC6_CFG_SECTION          0x38002409#define mmKERNEL_TENSOR_11_TPC6_CFG_BASE           0x7FFCF86668ull2410#define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET       0x38002411#define KERNEL_TENSOR_11_TPC6_CFG_SECTION          0x38002412#define mmKERNEL_TENSOR_12_TPC6_CFG_BASE           0x7FFCF866A0ull2413#define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET       0x38002414#define KERNEL_TENSOR_12_TPC6_CFG_SECTION          0x38002415#define mmKERNEL_TENSOR_13_TPC6_CFG_BASE           0x7FFCF866D8ull2416#define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET       0x38002417#define KERNEL_TENSOR_13_TPC6_CFG_SECTION          0x38002418#define mmKERNEL_TENSOR_14_TPC6_CFG_BASE           0x7FFCF86710ull2419#define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET       0x38002420#define KERNEL_TENSOR_14_TPC6_CFG_SECTION          0x38002421#define mmKERNEL_TENSOR_15_TPC6_CFG_BASE           0x7FFCF86748ull2422#define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET       0x38002423#define KERNEL_TENSOR_15_TPC6_CFG_SECTION          0x38002424#define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE         0x7FFCF86780ull2425#define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET     0x80002426#define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION        0x80002427#define mmKERNEL_TPC6_CFG_BASE                     0x7FFCF86788ull2428#define KERNEL_TPC6_CFG_MAX_OFFSET                 0xB8002429#define KERNEL_TPC6_CFG_SECTION                    0x27802430#define mmQM_TENSOR_0_TPC6_CFG_BASE                0x7FFCF86A00ull2431#define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET            0x38002432#define QM_TENSOR_0_TPC6_CFG_SECTION               0x38002433#define mmQM_TENSOR_1_TPC6_CFG_BASE                0x7FFCF86A38ull2434#define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET            0x38002435#define QM_TENSOR_1_TPC6_CFG_SECTION               0x38002436#define mmQM_TENSOR_2_TPC6_CFG_BASE                0x7FFCF86A70ull2437#define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET            0x38002438#define QM_TENSOR_2_TPC6_CFG_SECTION               0x38002439#define mmQM_TENSOR_3_TPC6_CFG_BASE                0x7FFCF86AA8ull2440#define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET            0x38002441#define QM_TENSOR_3_TPC6_CFG_SECTION               0x38002442#define mmQM_TENSOR_4_TPC6_CFG_BASE                0x7FFCF86AE0ull2443#define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET            0x38002444#define QM_TENSOR_4_TPC6_CFG_SECTION               0x38002445#define mmQM_TENSOR_5_TPC6_CFG_BASE                0x7FFCF86B18ull2446#define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET            0x38002447#define QM_TENSOR_5_TPC6_CFG_SECTION               0x38002448#define mmQM_TENSOR_6_TPC6_CFG_BASE                0x7FFCF86B50ull2449#define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET            0x38002450#define QM_TENSOR_6_TPC6_CFG_SECTION               0x38002451#define mmQM_TENSOR_7_TPC6_CFG_BASE                0x7FFCF86B88ull2452#define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET            0x38002453#define QM_TENSOR_7_TPC6_CFG_SECTION               0x38002454#define mmQM_TENSOR_8_TPC6_CFG_BASE                0x7FFCF86BC0ull2455#define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET            0x38002456#define QM_TENSOR_8_TPC6_CFG_SECTION               0x38002457#define mmQM_TENSOR_9_TPC6_CFG_BASE                0x7FFCF86BF8ull2458#define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET            0x38002459#define QM_TENSOR_9_TPC6_CFG_SECTION               0x38002460#define mmQM_TENSOR_10_TPC6_CFG_BASE               0x7FFCF86C30ull2461#define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET           0x38002462#define QM_TENSOR_10_TPC6_CFG_SECTION              0x38002463#define mmQM_TENSOR_11_TPC6_CFG_BASE               0x7FFCF86C68ull2464#define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET           0x38002465#define QM_TENSOR_11_TPC6_CFG_SECTION              0x38002466#define mmQM_TENSOR_12_TPC6_CFG_BASE               0x7FFCF86CA0ull2467#define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET           0x38002468#define QM_TENSOR_12_TPC6_CFG_SECTION              0x38002469#define mmQM_TENSOR_13_TPC6_CFG_BASE               0x7FFCF86CD8ull2470#define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET           0x38002471#define QM_TENSOR_13_TPC6_CFG_SECTION              0x38002472#define mmQM_TENSOR_14_TPC6_CFG_BASE               0x7FFCF86D10ull2473#define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET           0x38002474#define QM_TENSOR_14_TPC6_CFG_SECTION              0x38002475#define mmQM_TENSOR_15_TPC6_CFG_BASE               0x7FFCF86D48ull2476#define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET           0x38002477#define QM_TENSOR_15_TPC6_CFG_SECTION              0x38002478#define mmQM_SYNC_OBJECT_TPC6_CFG_BASE             0x7FFCF86D80ull2479#define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET         0x80002480#define QM_SYNC_OBJECT_TPC6_CFG_SECTION            0x80002481#define mmQM_TPC6_CFG_BASE                         0x7FFCF86D88ull2482#define QM_TPC6_CFG_MAX_OFFSET                     0xB8002483#define QM_TPC6_CFG_SECTION                        0x27802484#define mmTPC6_E2E_CRED_BASE                       0x7FFCF87000ull2485#define TPC6_E2E_CRED_MAX_OFFSET                   0x16802486#define TPC6_E2E_CRED_SECTION                      0x10002487#define mmTPC6_QM_BASE                             0x7FFCF88000ull2488#define TPC6_QM_MAX_OFFSET                         0xD0402489#define TPC6_QM_SECTION                            0x3E0002490#define mmTPC7_CFG_BASE                            0x7FFCFC6000ull2491#define TPC7_CFG_MAX_OFFSET                        0xE4002492#define TPC7_CFG_SECTION                           0x40002493#define mmKERNEL_TENSOR_0_TPC7_CFG_BASE            0x7FFCFC6400ull2494#define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET        0x38002495#define KERNEL_TENSOR_0_TPC7_CFG_SECTION           0x38002496#define mmKERNEL_TENSOR_1_TPC7_CFG_BASE            0x7FFCFC6438ull2497#define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET        0x38002498#define KERNEL_TENSOR_1_TPC7_CFG_SECTION           0x38002499#define mmKERNEL_TENSOR_2_TPC7_CFG_BASE            0x7FFCFC6470ull2500#define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET        0x38002501#define KERNEL_TENSOR_2_TPC7_CFG_SECTION           0x38002502#define mmKERNEL_TENSOR_3_TPC7_CFG_BASE            0x7FFCFC64A8ull2503#define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET        0x38002504#define KERNEL_TENSOR_3_TPC7_CFG_SECTION           0x38002505#define mmKERNEL_TENSOR_4_TPC7_CFG_BASE            0x7FFCFC64E0ull2506#define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET        0x38002507#define KERNEL_TENSOR_4_TPC7_CFG_SECTION           0x38002508#define mmKERNEL_TENSOR_5_TPC7_CFG_BASE            0x7FFCFC6518ull2509#define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET        0x38002510#define KERNEL_TENSOR_5_TPC7_CFG_SECTION           0x38002511#define mmKERNEL_TENSOR_6_TPC7_CFG_BASE            0x7FFCFC6550ull2512#define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET        0x38002513#define KERNEL_TENSOR_6_TPC7_CFG_SECTION           0x38002514#define mmKERNEL_TENSOR_7_TPC7_CFG_BASE            0x7FFCFC6588ull2515#define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET        0x38002516#define KERNEL_TENSOR_7_TPC7_CFG_SECTION           0x38002517#define mmKERNEL_TENSOR_8_TPC7_CFG_BASE            0x7FFCFC65C0ull2518#define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET        0x38002519#define KERNEL_TENSOR_8_TPC7_CFG_SECTION           0x38002520#define mmKERNEL_TENSOR_9_TPC7_CFG_BASE            0x7FFCFC65F8ull2521#define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET        0x38002522#define KERNEL_TENSOR_9_TPC7_CFG_SECTION           0x38002523#define mmKERNEL_TENSOR_10_TPC7_CFG_BASE           0x7FFCFC6630ull2524#define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET       0x38002525#define KERNEL_TENSOR_10_TPC7_CFG_SECTION          0x38002526#define mmKERNEL_TENSOR_11_TPC7_CFG_BASE           0x7FFCFC6668ull2527#define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET       0x38002528#define KERNEL_TENSOR_11_TPC7_CFG_SECTION          0x38002529#define mmKERNEL_TENSOR_12_TPC7_CFG_BASE           0x7FFCFC66A0ull2530#define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET       0x38002531#define KERNEL_TENSOR_12_TPC7_CFG_SECTION          0x38002532#define mmKERNEL_TENSOR_13_TPC7_CFG_BASE           0x7FFCFC66D8ull2533#define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET       0x38002534#define KERNEL_TENSOR_13_TPC7_CFG_SECTION          0x38002535#define mmKERNEL_TENSOR_14_TPC7_CFG_BASE           0x7FFCFC6710ull2536#define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET       0x38002537#define KERNEL_TENSOR_14_TPC7_CFG_SECTION          0x38002538#define mmKERNEL_TENSOR_15_TPC7_CFG_BASE           0x7FFCFC6748ull2539#define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET       0x38002540#define KERNEL_TENSOR_15_TPC7_CFG_SECTION          0x38002541#define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE         0x7FFCFC6780ull2542#define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET     0x80002543#define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION        0x80002544#define mmKERNEL_TPC7_CFG_BASE                     0x7FFCFC6788ull2545#define KERNEL_TPC7_CFG_MAX_OFFSET                 0xB8002546#define KERNEL_TPC7_CFG_SECTION                    0x27802547#define mmQM_TENSOR_0_TPC7_CFG_BASE                0x7FFCFC6A00ull2548#define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET            0x38002549#define QM_TENSOR_0_TPC7_CFG_SECTION               0x38002550#define mmQM_TENSOR_1_TPC7_CFG_BASE                0x7FFCFC6A38ull2551#define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET            0x38002552#define QM_TENSOR_1_TPC7_CFG_SECTION               0x38002553#define mmQM_TENSOR_2_TPC7_CFG_BASE                0x7FFCFC6A70ull2554#define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET            0x38002555#define QM_TENSOR_2_TPC7_CFG_SECTION               0x38002556#define mmQM_TENSOR_3_TPC7_CFG_BASE                0x7FFCFC6AA8ull2557#define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET            0x38002558#define QM_TENSOR_3_TPC7_CFG_SECTION               0x38002559#define mmQM_TENSOR_4_TPC7_CFG_BASE                0x7FFCFC6AE0ull2560#define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET            0x38002561#define QM_TENSOR_4_TPC7_CFG_SECTION               0x38002562#define mmQM_TENSOR_5_TPC7_CFG_BASE                0x7FFCFC6B18ull2563#define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET            0x38002564#define QM_TENSOR_5_TPC7_CFG_SECTION               0x38002565#define mmQM_TENSOR_6_TPC7_CFG_BASE                0x7FFCFC6B50ull2566#define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET            0x38002567#define QM_TENSOR_6_TPC7_CFG_SECTION               0x38002568#define mmQM_TENSOR_7_TPC7_CFG_BASE                0x7FFCFC6B88ull2569#define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET            0x38002570#define QM_TENSOR_7_TPC7_CFG_SECTION               0x38002571#define mmQM_TENSOR_8_TPC7_CFG_BASE                0x7FFCFC6BC0ull2572#define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET            0x38002573#define QM_TENSOR_8_TPC7_CFG_SECTION               0x38002574#define mmQM_TENSOR_9_TPC7_CFG_BASE                0x7FFCFC6BF8ull2575#define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET            0x38002576#define QM_TENSOR_9_TPC7_CFG_SECTION               0x38002577#define mmQM_TENSOR_10_TPC7_CFG_BASE               0x7FFCFC6C30ull2578#define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET           0x38002579#define QM_TENSOR_10_TPC7_CFG_SECTION              0x38002580#define mmQM_TENSOR_11_TPC7_CFG_BASE               0x7FFCFC6C68ull2581#define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET           0x38002582#define QM_TENSOR_11_TPC7_CFG_SECTION              0x38002583#define mmQM_TENSOR_12_TPC7_CFG_BASE               0x7FFCFC6CA0ull2584#define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET           0x38002585#define QM_TENSOR_12_TPC7_CFG_SECTION              0x38002586#define mmQM_TENSOR_13_TPC7_CFG_BASE               0x7FFCFC6CD8ull2587#define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET           0x38002588#define QM_TENSOR_13_TPC7_CFG_SECTION              0x38002589#define mmQM_TENSOR_14_TPC7_CFG_BASE               0x7FFCFC6D10ull2590#define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET           0x38002591#define QM_TENSOR_14_TPC7_CFG_SECTION              0x38002592#define mmQM_TENSOR_15_TPC7_CFG_BASE               0x7FFCFC6D48ull2593#define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET           0x38002594#define QM_TENSOR_15_TPC7_CFG_SECTION              0x38002595#define mmQM_SYNC_OBJECT_TPC7_CFG_BASE             0x7FFCFC6D80ull2596#define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET         0x80002597#define QM_SYNC_OBJECT_TPC7_CFG_SECTION            0x80002598#define mmQM_TPC7_CFG_BASE                         0x7FFCFC6D88ull2599#define QM_TPC7_CFG_MAX_OFFSET                     0xB8002600#define QM_TPC7_CFG_SECTION                        0x27802601#define mmTPC7_E2E_CRED_BASE                       0x7FFCFC7000ull2602#define TPC7_E2E_CRED_MAX_OFFSET                   0x16802603#define TPC7_E2E_CRED_SECTION                      0x10002604#define mmTPC7_QM_BASE                             0x7FFCFC8000ull2605#define TPC7_QM_MAX_OFFSET                         0xD0402606#define TPC7_QM_SECTION                            0x10380002607#define mmMME_S_ROM_TABLE_BASE                     0x7FFE000000ull2608#define MME_S_ROM_TABLE_MAX_OFFSET                 0x10002609#define MME_S_ROM_TABLE_SECTION                    0x210002610#define mmMME0_ACC_STM_BASE                        0x7FFE021000ull2611#define MME0_ACC_STM_MAX_OFFSET                    0x10002612#define MME0_ACC_STM_SECTION                       0x10002613#define mmMME0_ACC_CTI_BASE                        0x7FFE022000ull2614#define MME0_ACC_CTI_MAX_OFFSET                    0x10002615#define MME0_ACC_CTI_SECTION                       0x10002616#define mmMME0_ACC_ETF_BASE                        0x7FFE023000ull2617#define MME0_ACC_ETF_MAX_OFFSET                    0x10002618#define MME0_ACC_ETF_SECTION                       0x10002619#define mmMME0_ACC_SPMU_BASE                       0x7FFE024000ull2620#define MME0_ACC_SPMU_MAX_OFFSET                   0x10002621#define MME0_ACC_SPMU_SECTION                      0x10002622#define mmMME0_ACC_CTI0_BASE                       0x7FFE025000ull2623#define MME0_ACC_CTI0_MAX_OFFSET                   0x10002624#define MME0_ACC_CTI0_SECTION                      0x10002625#define mmMME0_ACC_CTI1_BASE                       0x7FFE026000ull2626#define MME0_ACC_CTI1_MAX_OFFSET                   0x10002627#define MME0_ACC_CTI1_SECTION                      0x10002628#define mmMME0_ACC_BMON0_BASE                      0x7FFE027000ull2629#define MME0_ACC_BMON0_MAX_OFFSET                  0x10002630#define MME0_ACC_BMON0_SECTION                     0x90002631#define mmMME0_ACC_FUNNEL_BASE                     0x7FFE030000ull2632#define MME0_ACC_FUNNEL_MAX_OFFSET                 0x10002633#define MME0_ACC_FUNNEL_SECTION                    0x110002634#define mmMME0_SBAB_STM_BASE                       0x7FFE041000ull2635#define MME0_SBAB_STM_MAX_OFFSET                   0x10002636#define MME0_SBAB_STM_SECTION                      0x10002637#define mmMME0_SBAB_CTI_BASE                       0x7FFE042000ull2638#define MME0_SBAB_CTI_MAX_OFFSET                   0x10002639#define MME0_SBAB_CTI_SECTION                      0x10002640#define mmMME0_SBAB_ETF_BASE                       0x7FFE043000ull2641#define MME0_SBAB_ETF_MAX_OFFSET                   0x10002642#define MME0_SBAB_ETF_SECTION                      0x10002643#define mmMME0_SBAB_SPMU_BASE                      0x7FFE044000ull2644#define MME0_SBAB_SPMU_MAX_OFFSET                  0x10002645#define MME0_SBAB_SPMU_SECTION                     0x10002646#define mmMME0_SBAB_CTI0_BASE                      0x7FFE045000ull2647#define MME0_SBAB_CTI0_MAX_OFFSET                  0x10002648#define MME0_SBAB_CTI0_SECTION                     0x10002649#define mmMME0_SBAB_CTI1_BASE                      0x7FFE046000ull2650#define MME0_SBAB_CTI1_MAX_OFFSET                  0x10002651#define MME0_SBAB_CTI1_SECTION                     0x10002652#define mmMME0_SBAB_BMON0_BASE                     0x7FFE047000ull2653#define MME0_SBAB_BMON0_MAX_OFFSET                 0x10002654#define MME0_SBAB_BMON0_SECTION                    0x10002655#define mmMME0_SBAB_BMON1_BASE                     0x7FFE048000ull2656#define MME0_SBAB_BMON1_MAX_OFFSET                 0x10002657#define MME0_SBAB_BMON1_SECTION                    0x190002658#define mmMME0_CTRL_STM_BASE                       0x7FFE061000ull2659#define MME0_CTRL_STM_MAX_OFFSET                   0x10002660#define MME0_CTRL_STM_SECTION                      0x10002661#define mmMME0_CTRL_CTI_BASE                       0x7FFE062000ull2662#define MME0_CTRL_CTI_MAX_OFFSET                   0x10002663#define MME0_CTRL_CTI_SECTION                      0x10002664#define mmMME0_CTRL_ETF_BASE                       0x7FFE063000ull2665#define MME0_CTRL_ETF_MAX_OFFSET                   0x10002666#define MME0_CTRL_ETF_SECTION                      0x10002667#define mmMME0_CTRL_SPMU_BASE                      0x7FFE064000ull2668#define MME0_CTRL_SPMU_MAX_OFFSET                  0x10002669#define MME0_CTRL_SPMU_SECTION                     0x10002670#define mmMME0_CTRL_CTI0_BASE                      0x7FFE065000ull2671#define MME0_CTRL_CTI0_MAX_OFFSET                  0x10002672#define MME0_CTRL_CTI0_SECTION                     0x10002673#define mmMME0_CTRL_CTI1_BASE                      0x7FFE066000ull2674#define MME0_CTRL_CTI1_MAX_OFFSET                  0x10002675#define MME0_CTRL_CTI1_SECTION                     0x10002676#define mmMME0_CTRL_BMON0_BASE                     0x7FFE067000ull2677#define MME0_CTRL_BMON0_MAX_OFFSET                 0x10002678#define MME0_CTRL_BMON0_SECTION                    0x10002679#define mmMME0_CTRL_BMON1_BASE                     0x7FFE068000ull2680#define MME0_CTRL_BMON1_MAX_OFFSET                 0x10002681#define MME0_CTRL_BMON1_SECTION                    0x390002682#define mmMME1_ACC_STM_BASE                        0x7FFE0A1000ull2683#define MME1_ACC_STM_MAX_OFFSET                    0x10002684#define MME1_ACC_STM_SECTION                       0x10002685#define mmMME1_ACC_CTI_BASE                        0x7FFE0A2000ull2686#define MME1_ACC_CTI_MAX_OFFSET                    0x10002687#define MME1_ACC_CTI_SECTION                       0x10002688#define mmMME1_ACC_ETF_BASE                        0x7FFE0A3000ull2689#define MME1_ACC_ETF_MAX_OFFSET                    0x10002690#define MME1_ACC_ETF_SECTION                       0x10002691#define mmMME1_ACC_SPMU_BASE                       0x7FFE0A4000ull2692#define MME1_ACC_SPMU_MAX_OFFSET                   0x10002693#define MME1_ACC_SPMU_SECTION                      0x10002694#define mmMME1_ACC_CTI0_BASE                       0x7FFE0A5000ull2695#define MME1_ACC_CTI0_MAX_OFFSET                   0x10002696#define MME1_ACC_CTI0_SECTION                      0x10002697#define mmMME1_ACC_CTI1_BASE                       0x7FFE0A6000ull2698#define MME1_ACC_CTI1_MAX_OFFSET                   0x10002699#define MME1_ACC_CTI1_SECTION                      0x10002700#define mmMME1_ACC_BMON0_BASE                      0x7FFE0A7000ull2701#define MME1_ACC_BMON0_MAX_OFFSET                  0x10002702#define MME1_ACC_BMON0_SECTION                     0x90002703#define mmMME1_ACC_FUNNEL_BASE                     0x7FFE0B0000ull2704#define MME1_ACC_FUNNEL_MAX_OFFSET                 0x10002705#define MME1_ACC_FUNNEL_SECTION                    0x110002706#define mmMME1_SBAB_STM_BASE                       0x7FFE0C1000ull2707#define MME1_SBAB_STM_MAX_OFFSET                   0x10002708#define MME1_SBAB_STM_SECTION                      0x10002709#define mmMME1_SBAB_CTI_BASE                       0x7FFE0C2000ull2710#define MME1_SBAB_CTI_MAX_OFFSET                   0x10002711#define MME1_SBAB_CTI_SECTION                      0x10002712#define mmMME1_SBAB_ETF_BASE                       0x7FFE0C3000ull2713#define MME1_SBAB_ETF_MAX_OFFSET                   0x10002714#define MME1_SBAB_ETF_SECTION                      0x10002715#define mmMME1_SBAB_SPMU_BASE                      0x7FFE0C4000ull2716#define MME1_SBAB_SPMU_MAX_OFFSET                  0x10002717#define MME1_SBAB_SPMU_SECTION                     0x10002718#define mmMME1_SBAB_CTI0_BASE                      0x7FFE0C5000ull2719#define MME1_SBAB_CTI0_MAX_OFFSET                  0x10002720#define MME1_SBAB_CTI0_SECTION                     0x10002721#define mmMME1_SBAB_CTI1_BASE                      0x7FFE0C6000ull2722#define MME1_SBAB_CTI1_MAX_OFFSET                  0x10002723#define MME1_SBAB_CTI1_SECTION                     0x10002724#define mmMME1_SBAB_BMON0_BASE                     0x7FFE0C7000ull2725#define MME1_SBAB_BMON0_MAX_OFFSET                 0x10002726#define MME1_SBAB_BMON0_SECTION                    0x10002727#define mmMME1_SBAB_BMON1_BASE                     0x7FFE0C8000ull2728#define MME1_SBAB_BMON1_MAX_OFFSET                 0x10002729#define MME1_SBAB_BMON1_SECTION                    0x190002730#define mmMME1_CTRL_STM_BASE                       0x7FFE0E1000ull2731#define MME1_CTRL_STM_MAX_OFFSET                   0x10002732#define MME1_CTRL_STM_SECTION                      0x10002733#define mmMME1_CTRL_CTI_BASE                       0x7FFE0E2000ull2734#define MME1_CTRL_CTI_MAX_OFFSET                   0x10002735#define MME1_CTRL_CTI_SECTION                      0x10002736#define mmMME1_CTRL_ETF_BASE                       0x7FFE0E3000ull2737#define MME1_CTRL_ETF_MAX_OFFSET                   0x10002738#define MME1_CTRL_ETF_SECTION                      0x10002739#define mmMME1_CTRL_SPMU_BASE                      0x7FFE0E4000ull2740#define MME1_CTRL_SPMU_MAX_OFFSET                  0x10002741#define MME1_CTRL_SPMU_SECTION                     0x10002742#define mmMME1_CTRL_CTI0_BASE                      0x7FFE0E5000ull2743#define MME1_CTRL_CTI0_MAX_OFFSET                  0x10002744#define MME1_CTRL_CTI0_SECTION                     0x10002745#define mmMME1_CTRL_CTI1_BASE                      0x7FFE0E6000ull2746#define MME1_CTRL_CTI1_MAX_OFFSET                  0x10002747#define MME1_CTRL_CTI1_SECTION                     0x10002748#define mmMME1_CTRL_BMON0_BASE                     0x7FFE0E7000ull2749#define MME1_CTRL_BMON0_MAX_OFFSET                 0x10002750#define MME1_CTRL_BMON0_SECTION                    0x10002751#define mmMME1_CTRL_BMON1_BASE                     0x7FFE0E8000ull2752#define MME1_CTRL_BMON1_MAX_OFFSET                 0x10002753#define MME1_CTRL_BMON1_SECTION                    0x180002754#define mmMME_N_ROM_TABLE_BASE                     0x7FFE100000ull2755#define MME_N_ROM_TABLE_MAX_OFFSET                 0x10002756#define MME_N_ROM_TABLE_SECTION                    0x210002757#define mmMME2_ACC_STM_BASE                        0x7FFE121000ull2758#define MME2_ACC_STM_MAX_OFFSET                    0x10002759#define MME2_ACC_STM_SECTION                       0x10002760#define mmMME2_ACC_CTI_BASE                        0x7FFE122000ull2761#define MME2_ACC_CTI_MAX_OFFSET                    0x10002762#define MME2_ACC_CTI_SECTION                       0x10002763#define mmMME2_MME2_ACC_ETF_BASE                   0x7FFE123000ull2764#define MME2_MME2_ACC_ETF_MAX_OFFSET               0x10002765#define MME2_MME2_ACC_ETF_SECTION                  0x10002766#define mmMME2_ACC_SPMU_BASE                       0x7FFE124000ull2767#define MME2_ACC_SPMU_MAX_OFFSET                   0x10002768#define MME2_ACC_SPMU_SECTION                      0x10002769#define mmMME2_ACC_CTI0_BASE                       0x7FFE125000ull2770#define MME2_ACC_CTI0_MAX_OFFSET                   0x10002771#define MME2_ACC_CTI0_SECTION                      0x10002772#define mmMME2_ACC_CTI1_BASE                       0x7FFE126000ull2773#define MME2_ACC_CTI1_MAX_OFFSET                   0x10002774#define MME2_ACC_CTI1_SECTION                      0x10002775#define mmMME2_ACC_BMON0_BASE                      0x7FFE127000ull2776#define MME2_ACC_BMON0_MAX_OFFSET                  0x10002777#define MME2_ACC_BMON0_SECTION                     0x90002778#define mmMME2_ACC_FUNNEL_BASE                     0x7FFE130000ull2779#define MME2_ACC_FUNNEL_MAX_OFFSET                 0x10002780#define MME2_ACC_FUNNEL_SECTION                    0x110002781#define mmMME2_SBAB_STM_BASE                       0x7FFE141000ull2782#define MME2_SBAB_STM_MAX_OFFSET                   0x10002783#define MME2_SBAB_STM_SECTION                      0x10002784#define mmMME2_SBAB_CTI_BASE                       0x7FFE142000ull2785#define MME2_SBAB_CTI_MAX_OFFSET                   0x10002786#define MME2_SBAB_CTI_SECTION                      0x10002787#define mmMME2_SBAB_ETF_BASE                       0x7FFE143000ull2788#define MME2_SBAB_ETF_MAX_OFFSET                   0x10002789#define MME2_SBAB_ETF_SECTION                      0x10002790#define mmMME2_SBAB_SPMU_BASE                      0x7FFE144000ull2791#define MME2_SBAB_SPMU_MAX_OFFSET                  0x10002792#define MME2_SBAB_SPMU_SECTION                     0x10002793#define mmMME2_SBAB_CTI0_BASE                      0x7FFE145000ull2794#define MME2_SBAB_CTI0_MAX_OFFSET                  0x10002795#define MME2_SBAB_CTI0_SECTION                     0x10002796#define mmMME2_SBAB_CTI1_BASE                      0x7FFE146000ull2797#define MME2_SBAB_CTI1_MAX_OFFSET                  0x10002798#define MME2_SBAB_CTI1_SECTION                     0x10002799#define mmMME2_SBAB_BMON0_BASE                     0x7FFE147000ull2800#define MME2_SBAB_BMON0_MAX_OFFSET                 0x10002801#define MME2_SBAB_BMON0_SECTION                    0x10002802#define mmMME2_SBAB_BMON1_BASE                     0x7FFE148000ull2803#define MME2_SBAB_BMON1_MAX_OFFSET                 0x10002804#define MME2_SBAB_BMON1_SECTION                    0x190002805#define mmMME2_CTRL_STM_BASE                       0x7FFE161000ull2806#define MME2_CTRL_STM_MAX_OFFSET                   0x10002807#define MME2_CTRL_STM_SECTION                      0x10002808#define mmMME2_CTRL_CTI_BASE                       0x7FFE162000ull2809#define MME2_CTRL_CTI_MAX_OFFSET                   0x10002810#define MME2_CTRL_CTI_SECTION                      0x10002811#define mmMME2_CTRL_ETF_BASE                       0x7FFE163000ull2812#define MME2_CTRL_ETF_MAX_OFFSET                   0x10002813#define MME2_CTRL_ETF_SECTION                      0x10002814#define mmMME2_CTRL_SPMU_BASE                      0x7FFE164000ull2815#define MME2_CTRL_SPMU_MAX_OFFSET                  0x10002816#define MME2_CTRL_SPMU_SECTION                     0x10002817#define mmMME2_CTRL_CTI0_BASE                      0x7FFE165000ull2818#define MME2_CTRL_CTI0_MAX_OFFSET                  0x10002819#define MME2_CTRL_CTI0_SECTION                     0x10002820#define mmMME2_CTRL_CTI1_BASE                      0x7FFE166000ull2821#define MME2_CTRL_CTI1_MAX_OFFSET                  0x10002822#define MME2_CTRL_CTI1_SECTION                     0x10002823#define mmMME2_CTRL_BMON0_BASE                     0x7FFE167000ull2824#define MME2_CTRL_BMON0_MAX_OFFSET                 0x10002825#define MME2_CTRL_BMON0_SECTION                    0x10002826#define mmMME2_CTRL_BMON1_BASE                     0x7FFE168000ull2827#define MME2_CTRL_BMON1_MAX_OFFSET                 0x10002828#define MME2_CTRL_BMON1_SECTION                    0x390002829#define mmMME3_ACC_STM_BASE                        0x7FFE1A1000ull2830#define MME3_ACC_STM_MAX_OFFSET                    0x10002831#define MME3_ACC_STM_SECTION                       0x10002832#define mmMME3_ACC_CTI_BASE                        0x7FFE1A2000ull2833#define MME3_ACC_CTI_MAX_OFFSET                    0x10002834#define MME3_ACC_CTI_SECTION                       0x10002835#define mmMME3_ACC_ETF_BASE                        0x7FFE1A3000ull2836#define MME3_ACC_ETF_MAX_OFFSET                    0x10002837#define MME3_ACC_ETF_SECTION                       0x10002838#define mmMME3_ACC_SPMU_BASE                       0x7FFE1A4000ull2839#define MME3_ACC_SPMU_MAX_OFFSET                   0x10002840#define MME3_ACC_SPMU_SECTION                      0x10002841#define mmMME3_ACC_CTI0_BASE                       0x7FFE1A5000ull2842#define MME3_ACC_CTI0_MAX_OFFSET                   0x10002843#define MME3_ACC_CTI0_SECTION                      0x10002844#define mmMME3_ACC_CTI1_BASE                       0x7FFE1A6000ull2845#define MME3_ACC_CTI1_MAX_OFFSET                   0x10002846#define MME3_ACC_CTI1_SECTION                      0x10002847#define mmMME3_ACC_BMON0_BASE                      0x7FFE1A7000ull2848#define MME3_ACC_BMON0_MAX_OFFSET                  0x10002849#define MME3_ACC_BMON0_SECTION                     0x90002850#define mmMME3_ACC_FUNNEL_BASE                     0x7FFE1B0000ull2851#define MME3_ACC_FUNNEL_MAX_OFFSET                 0x10002852#define MME3_ACC_FUNNEL_SECTION                    0x110002853#define mmMME3_SBAB_STM_BASE                       0x7FFE1C1000ull2854#define MME3_SBAB_STM_MAX_OFFSET                   0x10002855#define MME3_SBAB_STM_SECTION                      0x10002856#define mmMME3_SBAB_CTI_BASE                       0x7FFE1C2000ull2857#define MME3_SBAB_CTI_MAX_OFFSET                   0x10002858#define MME3_SBAB_CTI_SECTION                      0x10002859#define mmMME3_SBAB_ETF_BASE                       0x7FFE1C3000ull2860#define MME3_SBAB_ETF_MAX_OFFSET                   0x10002861#define MME3_SBAB_ETF_SECTION                      0x10002862#define mmMME3_SBAB_SPMU_BASE                      0x7FFE1C4000ull2863#define MME3_SBAB_SPMU_MAX_OFFSET                  0x10002864#define MME3_SBAB_SPMU_SECTION                     0x10002865#define mmMME3_SBAB_CTI0_BASE                      0x7FFE1C5000ull2866#define MME3_SBAB_CTI0_MAX_OFFSET                  0x10002867#define MME3_SBAB_CTI0_SECTION                     0x10002868#define mmMME3_SBAB_CTI1_BASE                      0x7FFE1C6000ull2869#define MME3_SBAB_CTI1_MAX_OFFSET                  0x10002870#define MME3_SBAB_CTI1_SECTION                     0x10002871#define mmMME3_SBAB_BMON0_BASE                     0x7FFE1C7000ull2872#define MME3_SBAB_BMON0_MAX_OFFSET                 0x10002873#define MME3_SBAB_BMON0_SECTION                    0x10002874#define mmMME3_SBAB_BMON1_BASE                     0x7FFE1C8000ull2875#define MME3_SBAB_BMON1_MAX_OFFSET                 0x10002876#define MME3_SBAB_BMON1_SECTION                    0x190002877#define mmMME3_CTRL_STM_BASE                       0x7FFE1E1000ull2878#define MME3_CTRL_STM_MAX_OFFSET                   0x10002879#define MME3_CTRL_STM_SECTION                      0x10002880#define mmMME3_CTRL_CTI_BASE                       0x7FFE1E2000ull2881#define MME3_CTRL_CTI_MAX_OFFSET                   0x10002882#define MME3_CTRL_CTI_SECTION                      0x10002883#define mmMME3_CTRL_ETF_BASE                       0x7FFE1E3000ull2884#define MME3_CTRL_ETF_MAX_OFFSET                   0x10002885#define MME3_CTRL_ETF_SECTION                      0x10002886#define mmMME3_CTRL_SPMU_BASE                      0x7FFE1E4000ull2887#define MME3_CTRL_SPMU_MAX_OFFSET                  0x10002888#define MME3_CTRL_SPMU_SECTION                     0x10002889#define mmMME3_CTRL_CTI0_BASE                      0x7FFE1E5000ull2890#define MME3_CTRL_CTI0_MAX_OFFSET                  0x10002891#define MME3_CTRL_CTI0_SECTION                     0x10002892#define mmMME3_CTRL_CTI1_BASE                      0x7FFE1E6000ull2893#define MME3_CTRL_CTI1_MAX_OFFSET                  0x10002894#define MME3_CTRL_CTI1_SECTION                     0x10002895#define mmMME3_CTRL_BMON0_BASE                     0x7FFE1E7000ull2896#define MME3_CTRL_BMON0_MAX_OFFSET                 0x10002897#define MME3_CTRL_BMON0_SECTION                    0x10002898#define mmMME3_CTRL_BMON1_BASE                     0x7FFE1E8000ull2899#define MME3_CTRL_BMON1_MAX_OFFSET                 0x10002900#define MME3_CTRL_BMON1_SECTION                    0x180002901#define mmIC_ROM_TABLE_BASE                        0x7FFE200000ull2902#define IC_ROM_TABLE_MAX_OFFSET                    0x10002903#define IC_ROM_TABLE_SECTION                       0x10002904#define mmSRAM_Y0_X0_FUNNEL_BASE                   0x7FFE201000ull2905#define SRAM_Y0_X0_FUNNEL_MAX_OFFSET               0x10002906#define SRAM_Y0_X0_FUNNEL_SECTION                  0x80002907#define mmSRAM_Y0_X1_FUNNEL_BASE                   0x7FFE209000ull2908#define SRAM_Y0_X1_FUNNEL_MAX_OFFSET               0x10002909#define SRAM_Y0_X1_FUNNEL_SECTION                  0x80002910#define mmSRAM_Y0_X2_FUNNEL_BASE                   0x7FFE211000ull2911#define SRAM_Y0_X2_FUNNEL_MAX_OFFSET               0x10002912#define SRAM_Y0_X2_FUNNEL_SECTION                  0x80002913#define mmSRAM_Y0_X3_FUNNEL_BASE                   0x7FFE219000ull2914#define SRAM_Y0_X3_FUNNEL_MAX_OFFSET               0x10002915#define SRAM_Y0_X3_FUNNEL_SECTION                  0x80002916#define mmSRAM_Y0_X4_FUNNEL_BASE                   0x7FFE221000ull2917#define SRAM_Y0_X4_FUNNEL_MAX_OFFSET               0x10002918#define SRAM_Y0_X4_FUNNEL_SECTION                  0x80002919#define mmSRAM_Y0_X5_FUNNEL_BASE                   0x7FFE229000ull2920#define SRAM_Y0_X5_FUNNEL_MAX_OFFSET               0x10002921#define SRAM_Y0_X5_FUNNEL_SECTION                  0x80002922#define mmSRAM_Y0_X6_FUNNEL_BASE                   0x7FFE231000ull2923#define SRAM_Y0_X6_FUNNEL_MAX_OFFSET               0x10002924#define SRAM_Y0_X6_FUNNEL_SECTION                  0x80002925#define mmSRAM_Y0_X7_FUNNEL_BASE                   0x7FFE239000ull2926#define SRAM_Y0_X7_FUNNEL_MAX_OFFSET               0x10002927#define SRAM_Y0_X7_FUNNEL_SECTION                  0x80002928#define mmSRAM_Y1_X0_FUNNEL_BASE                   0x7FFE241000ull2929#define SRAM_Y1_X0_FUNNEL_MAX_OFFSET               0x10002930#define SRAM_Y1_X0_FUNNEL_SECTION                  0x80002931#define mmSRAM_Y1_X1_FUNNEL_BASE                   0x7FFE249000ull2932#define SRAM_Y1_X1_FUNNEL_MAX_OFFSET               0x10002933#define SRAM_Y1_X1_FUNNEL_SECTION                  0x80002934#define mmSRAM_Y1_X2_FUNNEL_BASE                   0x7FFE251000ull2935#define SRAM_Y1_X2_FUNNEL_MAX_OFFSET               0x10002936#define SRAM_Y1_X2_FUNNEL_SECTION                  0x80002937#define mmSRAM_Y1_X3_FUNNEL_BASE                   0x7FFE259000ull2938#define SRAM_Y1_X3_FUNNEL_MAX_OFFSET               0x10002939#define SRAM_Y1_X3_FUNNEL_SECTION                  0x80002940#define mmSRAM_Y1_X4_FUNNEL_BASE                   0x7FFE261000ull2941#define SRAM_Y1_X4_FUNNEL_MAX_OFFSET               0x10002942#define SRAM_Y1_X4_FUNNEL_SECTION                  0x80002943#define mmSRAM_Y1_X5_FUNNEL_BASE                   0x7FFE269000ull2944#define SRAM_Y1_X5_FUNNEL_MAX_OFFSET               0x10002945#define SRAM_Y1_X5_FUNNEL_SECTION                  0x80002946#define mmSRAM_Y1_X6_FUNNEL_BASE                   0x7FFE271000ull2947#define SRAM_Y1_X6_FUNNEL_MAX_OFFSET               0x10002948#define SRAM_Y1_X6_FUNNEL_SECTION                  0x80002949#define mmSRAM_Y1_X7_FUNNEL_BASE                   0x7FFE279000ull2950#define SRAM_Y1_X7_FUNNEL_MAX_OFFSET               0x10002951#define SRAM_Y1_X7_FUNNEL_SECTION                  0x80002952#define mmSRAM_Y2_X0_FUNNEL_BASE                   0x7FFE281000ull2953#define SRAM_Y2_X0_FUNNEL_MAX_OFFSET               0x10002954#define SRAM_Y2_X0_FUNNEL_SECTION                  0x80002955#define mmSRAM_Y2_X1_FUNNEL_BASE                   0x7FFE289000ull2956#define SRAM_Y2_X1_FUNNEL_MAX_OFFSET               0x10002957#define SRAM_Y2_X1_FUNNEL_SECTION                  0x80002958#define mmSRAM_Y2_X2_FUNNEL_BASE                   0x7FFE291000ull2959#define SRAM_Y2_X2_FUNNEL_MAX_OFFSET               0x10002960#define SRAM_Y2_X2_FUNNEL_SECTION                  0x80002961#define mmSRAM_Y2_X3_FUNNEL_BASE                   0x7FFE299000ull2962#define SRAM_Y2_X3_FUNNEL_MAX_OFFSET               0x10002963#define SRAM_Y2_X3_FUNNEL_SECTION                  0x80002964#define mmSRAM_Y2_X4_FUNNEL_BASE                   0x7FFE2A1000ull2965#define SRAM_Y2_X4_FUNNEL_MAX_OFFSET               0x10002966#define SRAM_Y2_X4_FUNNEL_SECTION                  0x80002967#define mmSRAM_Y2_X5_FUNNEL_BASE                   0x7FFE2A9000ull2968#define SRAM_Y2_X5_FUNNEL_MAX_OFFSET               0x10002969#define SRAM_Y2_X5_FUNNEL_SECTION                  0x80002970#define mmSRAM_Y2_X6_FUNNEL_BASE                   0x7FFE2B1000ull2971#define SRAM_Y2_X6_FUNNEL_MAX_OFFSET               0x10002972#define SRAM_Y2_X6_FUNNEL_SECTION                  0x80002973#define mmSRAM_Y2_X7_FUNNEL_BASE                   0x7FFE2B9000ull2974#define SRAM_Y2_X7_FUNNEL_MAX_OFFSET               0x10002975#define SRAM_Y2_X7_FUNNEL_SECTION                  0x80002976#define mmSRAM_Y3_X0_FUNNEL_BASE                   0x7FFE2C1000ull2977#define SRAM_Y3_X0_FUNNEL_MAX_OFFSET               0x10002978#define SRAM_Y3_X0_FUNNEL_SECTION                  0x80002979#define mmSRAM_Y3_X1_FUNNEL_BASE                   0x7FFE2C9000ull2980#define SRAM_Y3_X1_FUNNEL_MAX_OFFSET               0x10002981#define SRAM_Y3_X1_FUNNEL_SECTION                  0x80002982#define mmSRAM_Y3_X2_FUNNEL_BASE                   0x7FFE2D1000ull2983#define SRAM_Y3_X2_FUNNEL_MAX_OFFSET               0x10002984#define SRAM_Y3_X2_FUNNEL_SECTION                  0x80002985#define mmSRAM_Y3_X4_FUNNEL_BASE                   0x7FFE2D9000ull2986#define SRAM_Y3_X4_FUNNEL_MAX_OFFSET               0x10002987#define SRAM_Y3_X4_FUNNEL_SECTION                  0x80002988#define mmSRAM_Y3_X3_FUNNEL_BASE                   0x7FFE2E1000ull2989#define SRAM_Y3_X3_FUNNEL_MAX_OFFSET               0x10002990#define SRAM_Y3_X3_FUNNEL_SECTION                  0x80002991#define mmSRAM_Y3_X5_FUNNEL_BASE                   0x7FFE2E9000ull2992#define SRAM_Y3_X5_FUNNEL_MAX_OFFSET               0x10002993#define SRAM_Y3_X5_FUNNEL_SECTION                  0x80002994#define mmSRAM_Y3_X6_FUNNEL_BASE                   0x7FFE2F1000ull2995#define SRAM_Y3_X6_FUNNEL_MAX_OFFSET               0x10002996#define SRAM_Y3_X6_FUNNEL_SECTION                  0x80002997#define mmSRAM_Y3_X7_FUNNEL_BASE                   0x7FFE2F9000ull2998#define SRAM_Y3_X7_FUNNEL_MAX_OFFSET               0x10002999#define SRAM_Y3_X7_FUNNEL_SECTION                  0x70003000#define mmIF_ROM_TABLE_BASE                        0x7FFE300000ull3001#define IF_ROM_TABLE_MAX_OFFSET                    0x10003002#define IF_ROM_TABLE_SECTION                       0x10003003#define mmSIF_FUNNEL_0_BASE                        0x7FFE301000ull3004#define SIF_FUNNEL_0_MAX_OFFSET                    0x10003005#define SIF_FUNNEL_0_SECTION                       0x100003006#define mmSIF_FUNNEL_1_BASE                        0x7FFE311000ull3007#define SIF_FUNNEL_1_MAX_OFFSET                    0x10003008#define SIF_FUNNEL_1_SECTION                       0x100003009#define mmSIF_FUNNEL_2_BASE                        0x7FFE321000ull3010#define SIF_FUNNEL_2_MAX_OFFSET                    0x10003011#define SIF_FUNNEL_2_SECTION                       0x100003012#define mmSIF_FUNNEL_3_BASE                        0x7FFE331000ull3013#define SIF_FUNNEL_3_MAX_OFFSET                    0x10003014#define SIF_FUNNEL_3_SECTION                       0x100003015#define mmSIF_FUNNEL_4_BASE                        0x7FFE341000ull3016#define SIF_FUNNEL_4_MAX_OFFSET                    0x10003017#define SIF_FUNNEL_4_SECTION                       0x100003018#define mmSIF_FUNNEL_5_BASE                        0x7FFE351000ull3019#define SIF_FUNNEL_5_MAX_OFFSET                    0x10003020#define SIF_FUNNEL_5_SECTION                       0x100003021#define mmSIF_FUNNEL_6_BASE                        0x7FFE361000ull3022#define SIF_FUNNEL_6_MAX_OFFSET                    0x10003023#define SIF_FUNNEL_6_SECTION                       0x100003024#define mmSIF_FUNNEL_7_BASE                        0x7FFE371000ull3025#define SIF_FUNNEL_7_MAX_OFFSET                    0x10003026#define SIF_FUNNEL_7_SECTION                       0x100003027#define mmNIF_FUNNEL_0_BASE                        0x7FFE381000ull3028#define NIF_FUNNEL_0_MAX_OFFSET                    0x10003029#define NIF_FUNNEL_0_SECTION                       0x100003030#define mmNIF_FUNNEL_1_BASE                        0x7FFE391000ull3031#define NIF_FUNNEL_1_MAX_OFFSET                    0x10003032#define NIF_FUNNEL_1_SECTION                       0x100003033#define mmNIF_FUNNEL_2_BASE                        0x7FFE3A1000ull3034#define NIF_FUNNEL_2_MAX_OFFSET                    0x10003035#define NIF_FUNNEL_2_SECTION                       0x100003036#define mmNIF_FUNNEL_3_BASE                        0x7FFE3B1000ull3037#define NIF_FUNNEL_3_MAX_OFFSET                    0x10003038#define NIF_FUNNEL_3_SECTION                       0x100003039#define mmNIF_FUNNEL_4_BASE                        0x7FFE3C1000ull3040#define NIF_FUNNEL_4_MAX_OFFSET                    0x10003041#define NIF_FUNNEL_4_SECTION                       0x100003042#define mmNIF_FUNNEL_5_BASE                        0x7FFE3D1000ull3043#define NIF_FUNNEL_5_MAX_OFFSET                    0x10003044#define NIF_FUNNEL_5_SECTION                       0x100003045#define mmNIF_FUNNEL_6_BASE                        0x7FFE3E1000ull3046#define NIF_FUNNEL_6_MAX_OFFSET                    0x10003047#define NIF_FUNNEL_6_SECTION                       0x100003048#define mmNIF_FUNNEL_7_BASE                        0x7FFE3F1000ull3049#define NIF_FUNNEL_7_MAX_OFFSET                    0x10003050#define NIF_FUNNEL_7_SECTION                       0xF0003051#define mmDMA_IF_ROM_TABLE_BASE                    0x7FFE400000ull3052#define DMA_IF_ROM_TABLE_MAX_OFFSET                0x10003053#define DMA_IF_ROM_TABLE_SECTION                   0x10003054#define mmDMA_IF_W_S_STM_BASE                      0x7FFE401000ull3055#define DMA_IF_W_S_STM_MAX_OFFSET                  0x10003056#define DMA_IF_W_S_STM_SECTION                     0x10003057#define mmDMA_IF_W_S_CTI_BASE                      0x7FFE402000ull3058#define DMA_IF_W_S_CTI_MAX_OFFSET                  0x10003059#define DMA_IF_W_S_CTI_SECTION                     0x10003060#define mmDMA_IF_W_S_ETF_BASE                      0x7FFE403000ull3061#define DMA_IF_W_S_ETF_MAX_OFFSET                  0x10003062#define DMA_IF_W_S_ETF_SECTION                     0x20003063#define mmDMA_IF_W_S_BMON0_CTI_BASE                0x7FFE405000ull3064#define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET            0x10003065#define DMA_IF_W_S_BMON0_CTI_SECTION               0x10003066#define mmDMA_IF_W_S_BMON1_CTI_BASE                0x7FFE406000ull3067#define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET            0x10003068#define DMA_IF_W_S_BMON1_CTI_SECTION               0x10003069#define mmDMA_IF_W_S_HBM0_WR_BMON_BASE             0x7FFE407000ull3070#define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET         0x10003071#define DMA_IF_W_S_HBM0_WR_BMON_SECTION            0x10003072#define mmDMA_IF_W_S_HBM0_RD_BMON_BASE             0x7FFE408000ull3073#define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET         0x10003074#define DMA_IF_W_S_HBM0_RD_BMON_SECTION            0x10003075#define mmDMA_IF_W_S_HBM1_WR_BMON_BASE             0x7FFE409000ull3076#define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET         0x10003077#define DMA_IF_W_S_HBM1_WR_BMON_SECTION            0x10003078#define mmDMA_IF_W_S_HBM1_RD_BMON_BASE             0x7FFE40A000ull3079#define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET         0x10003080#define DMA_IF_W_S_HBM1_RD_BMON_SECTION            0x10003081#define mmDMA_IF_W_S_SOB_WR_BMON_BASE              0x7FFE40B000ull3082#define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET          0x10003083#define DMA_IF_W_S_SOB_WR_BMON_SECTION             0x40003084#define mmDMA_IF_W_S_FUNNEL_BASE                   0x7FFE40F000ull3085#define DMA_IF_W_S_FUNNEL_MAX_OFFSET               0x10003086#define DMA_IF_W_S_FUNNEL_SECTION                  0x120003087#define mmDMA_IF_E_S_STM_BASE                      0x7FFE421000ull3088#define DMA_IF_E_S_STM_MAX_OFFSET                  0x10003089#define DMA_IF_E_S_STM_SECTION                     0x10003090#define mmDMA_IF_E_S_CTI_BASE                      0x7FFE422000ull3091#define DMA_IF_E_S_CTI_MAX_OFFSET                  0x10003092#define DMA_IF_E_S_CTI_SECTION                     0x10003093#define mmDMA_IF_E_S_ETF_BASE                      0x7FFE423000ull3094#define DMA_IF_E_S_ETF_MAX_OFFSET                  0x10003095#define DMA_IF_E_S_ETF_SECTION                     0x20003096#define mmDMA_IF_E_S_BMON0_CTI_BASE                0x7FFE425000ull3097#define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET            0x10003098#define DMA_IF_E_S_BMON0_CTI_SECTION               0x10003099#define mmDMA_IF_E_S_BMON1_CTI_BASE                0x7FFE426000ull3100#define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET            0x10003101#define DMA_IF_E_S_BMON1_CTI_SECTION               0x10003102#define mmDMA_IF_E_S_HBM0_WR_BMON_BASE             0x7FFE427000ull3103#define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET         0x10003104#define DMA_IF_E_S_HBM0_WR_BMON_SECTION            0x10003105#define mmDMA_IF_E_S_HBM0_RD_BMON_BASE             0x7FFE428000ull3106#define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET         0x10003107#define DMA_IF_E_S_HBM0_RD_BMON_SECTION            0x10003108#define mmDMA_IF_E_S_HBM1_WR_BMON_BASE             0x7FFE429000ull3109#define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET         0x10003110#define DMA_IF_E_S_HBM1_WR_BMON_SECTION            0x10003111#define mmDMA_IF_E_S_HBM1_RD_BMON_BASE             0x7FFE42A000ull3112#define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET         0x10003113#define DMA_IF_E_S_HBM1_RD_BMON_SECTION            0x10003114#define mmDMA_IF_E_S_SOB_WR_BMON_BASE              0x7FFE42B000ull3115#define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET          0x10003116#define DMA_IF_E_S_SOB_WR_BMON_SECTION             0x40003117#define mmDMA_IF_E_S_FUNNEL_BASE                   0x7FFE42F000ull3118#define DMA_IF_E_S_FUNNEL_MAX_OFFSET               0x10003119#define DMA_IF_E_S_FUNNEL_SECTION                  0x120003120#define mmDMA_IF_W_N_STM_BASE                      0x7FFE441000ull3121#define DMA_IF_W_N_STM_MAX_OFFSET                  0x10003122#define DMA_IF_W_N_STM_SECTION                     0x10003123#define mmDMA_IF_W_N_CTI_BASE                      0x7FFE442000ull3124#define DMA_IF_W_N_CTI_MAX_OFFSET                  0x10003125#define DMA_IF_W_N_CTI_SECTION                     0x10003126#define mmDMA_IF_W_N_ETF_BASE                      0x7FFE443000ull3127#define DMA_IF_W_N_ETF_MAX_OFFSET                  0x10003128#define DMA_IF_W_N_ETF_SECTION                     0x20003129#define mmDMA_IF_W_N_BMON0_CTI_BASE                0x7FFE445000ull3130#define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET            0x10003131#define DMA_IF_W_N_BMON0_CTI_SECTION               0x10003132#define mmDMA_IF_W_N_BMON1_CTI_BASE                0x7FFE446000ull3133#define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET            0x10003134#define DMA_IF_W_N_BMON1_CTI_SECTION               0x10003135#define mmDMA_IF_W_N_HBM0_WR_BMON_BASE             0x7FFE447000ull3136#define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET         0x10003137#define DMA_IF_W_N_HBM0_WR_BMON_SECTION            0x10003138#define mmDMA_IF_W_N_HBM0_RD_BMON_BASE             0x7FFE448000ull3139#define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET         0x10003140#define DMA_IF_W_N_HBM0_RD_BMON_SECTION            0x10003141#define mmDMA_IF_W_N_HBM1_WR_BMON_BASE             0x7FFE449000ull3142#define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET         0x10003143#define DMA_IF_W_N_HBM1_WR_BMON_SECTION            0x10003144#define mmDMA_IF_W_N_HBM1_RD_BMON_BASE             0x7FFE44A000ull3145#define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET         0x10003146#define DMA_IF_W_N_HBM1_RD_BMON_SECTION            0x10003147#define mmDMA_IF_W_N_SOB_WR_BMON_BASE              0x7FFE44B000ull3148#define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET          0x10003149#define DMA_IF_W_N_SOB_WR_BMON_SECTION             0x40003150#define mmDMA_IF_W_N_FUNNEL_BASE                   0x7FFE44F000ull3151#define DMA_IF_W_N_FUNNEL_MAX_OFFSET               0x10003152#define DMA_IF_W_N_FUNNEL_SECTION                  0x120003153#define mmDMA_IF_E_N_STM_BASE                      0x7FFE461000ull3154#define DMA_IF_E_N_STM_MAX_OFFSET                  0x10003155#define DMA_IF_E_N_STM_SECTION                     0x10003156#define mmDMA_IF_E_N_CTI_BASE                      0x7FFE462000ull3157#define DMA_IF_E_N_CTI_MAX_OFFSET                  0x10003158#define DMA_IF_E_N_CTI_SECTION                     0x10003159#define mmDMA_IF_E_N_ETF_BASE                      0x7FFE463000ull3160#define DMA_IF_E_N_ETF_MAX_OFFSET                  0x10003161#define DMA_IF_E_N_ETF_SECTION                     0x20003162#define mmDMA_IF_E_N_BMON0_CTI_BASE                0x7FFE465000ull3163#define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET            0x10003164#define DMA_IF_E_N_BMON0_CTI_SECTION               0x10003165#define mmDMA_IF_E_N_BMON1_CTI_BASE                0x7FFE466000ull3166#define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET            0x10003167#define DMA_IF_E_N_BMON1_CTI_SECTION               0x10003168#define mmDMA_IF_E_N_HBM0_WR_BMON_BASE             0x7FFE467000ull3169#define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET         0x10003170#define DMA_IF_E_N_HBM0_WR_BMON_SECTION            0x10003171#define mmDMA_IF_E_N_HBM0_RD_BMON_BASE             0x7FFE468000ull3172#define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET         0x10003173#define DMA_IF_E_N_HBM0_RD_BMON_SECTION            0x10003174#define mmDMA_IF_E_N_HBM1_WR_BMON_BASE             0x7FFE469000ull3175#define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET         0x10003176#define DMA_IF_E_N_HBM1_WR_BMON_SECTION            0x10003177#define mmDMA_IF_E_N_HBM1_RD_BMON_BASE             0x7FFE46A000ull3178#define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET         0x10003179#define DMA_IF_E_N_HBM1_RD_BMON_SECTION            0x10003180#define mmDMA_IF_E_N_SOB_WR_BMON_BASE              0x7FFE46B000ull3181#define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET          0x10003182#define DMA_IF_E_N_SOB_WR_BMON_SECTION             0x40003183#define mmDMA_IF_E_N_FUNNEL_BASE                   0x7FFE46F000ull3184#define DMA_IF_E_N_FUNNEL_MAX_OFFSET               0x10003185#define DMA_IF_E_N_FUNNEL_SECTION                  0x110003186#define mmCPU_ROM_TABLE_BASE                       0x7FFE480000ull3187#define CPU_ROM_TABLE_MAX_OFFSET                   0x10003188#define CPU_ROM_TABLE_SECTION                      0x10003189#define mmCPU_ETF_0_BASE                           0x7FFE481000ull3190#define CPU_ETF_0_MAX_OFFSET                       0x10003191#define CPU_ETF_0_SECTION                          0x10003192#define mmCPU_ETF_1_BASE                           0x7FFE482000ull3193#define CPU_ETF_1_MAX_OFFSET                       0x10003194#define CPU_ETF_1_SECTION                          0x20003195#define mmCPU_CTI_BASE                             0x7FFE484000ull3196#define CPU_CTI_MAX_OFFSET                         0x10003197#define CPU_CTI_SECTION                            0x10003198#define mmCPU_FUNNEL_BASE                          0x7FFE485000ull3199#define CPU_FUNNEL_MAX_OFFSET                      0x10003200#define CPU_FUNNEL_SECTION                         0x10003201#define mmCPU_STM_BASE                             0x7FFE486000ull3202#define CPU_STM_MAX_OFFSET                         0x10003203#define CPU_STM_SECTION                            0x10003204#define mmCPU_CTI_TRACE_BASE                       0x7FFE487000ull3205#define CPU_CTI_TRACE_MAX_OFFSET                   0x10003206#define CPU_CTI_TRACE_SECTION                      0x10003207#define mmCPU_ETF_TRACE_BASE                       0x7FFE488000ull3208#define CPU_ETF_TRACE_MAX_OFFSET                   0x10003209#define CPU_ETF_TRACE_SECTION                      0x10003210#define mmCPU_WR_BMON_BASE                         0x7FFE489000ull3211#define CPU_WR_BMON_MAX_OFFSET                     0x10003212#define CPU_WR_BMON_SECTION                        0x10003213#define mmCPU_RD_BMON_BASE                         0x7FFE48A000ull3214#define CPU_RD_BMON_MAX_OFFSET                     0x10003215#define CPU_RD_BMON_SECTION                        0x760003216#define mmDMA_ROM_TABLE_BASE                       0x7FFE500000ull3217#define DMA_ROM_TABLE_MAX_OFFSET                   0x10003218#define DMA_ROM_TABLE_SECTION                      0x10003219#define mmDMA_CH_0_CS_STM_BASE                     0x7FFE501000ull3220#define DMA_CH_0_CS_STM_MAX_OFFSET                 0x10003221#define DMA_CH_0_CS_STM_SECTION                    0x10003222#define mmDMA_CH_0_CS_CTI_BASE                     0x7FFE502000ull3223#define DMA_CH_0_CS_CTI_MAX_OFFSET                 0x10003224#define DMA_CH_0_CS_CTI_SECTION                    0x10003225#define mmDMA_CH_0_CS_ETF_BASE                     0x7FFE503000ull3226#define DMA_CH_0_CS_ETF_MAX_OFFSET                 0x10003227#define DMA_CH_0_CS_ETF_SECTION                    0x10003228#define mmDMA_CH_0_CS_SPMU_BASE                    0x7FFE504000ull3229#define DMA_CH_0_CS_SPMU_MAX_OFFSET                0x10003230#define DMA_CH_0_CS_SPMU_SECTION                   0x10003231#define mmDMA_CH_0_BMON_CTI_BASE                   0x7FFE505000ull3232#define DMA_CH_0_BMON_CTI_MAX_OFFSET               0x10003233#define DMA_CH_0_BMON_CTI_SECTION                  0x10003234#define mmDMA_CH_0_USER_CTI_BASE                   0x7FFE506000ull3235#define DMA_CH_0_USER_CTI_MAX_OFFSET               0x10003236#define DMA_CH_0_USER_CTI_SECTION                  0x10003237#define mmDMA_CH_0_BMON_0_BASE                     0x7FFE507000ull3238#define DMA_CH_0_BMON_0_MAX_OFFSET                 0x10003239#define DMA_CH_0_BMON_0_SECTION                    0x10003240#define mmDMA_CH_0_BMON_1_BASE                     0x7FFE508000ull3241#define DMA_CH_0_BMON_1_MAX_OFFSET                 0x10003242#define DMA_CH_0_BMON_1_SECTION                    0x190003243#define mmDMA_CH_1_CS_STM_BASE                     0x7FFE521000ull3244#define DMA_CH_1_CS_STM_MAX_OFFSET                 0x10003245#define DMA_CH_1_CS_STM_SECTION                    0x10003246#define mmDMA_CH_1_CS_CTI_BASE                     0x7FFE522000ull3247#define DMA_CH_1_CS_CTI_MAX_OFFSET                 0x10003248#define DMA_CH_1_CS_CTI_SECTION                    0x10003249#define mmDMA_CH_1_CS_ETF_BASE                     0x7FFE523000ull3250#define DMA_CH_1_CS_ETF_MAX_OFFSET                 0x10003251#define DMA_CH_1_CS_ETF_SECTION                    0x10003252#define mmDMA_CH_1_CS_SPMU_BASE                    0x7FFE524000ull3253#define DMA_CH_1_CS_SPMU_MAX_OFFSET                0x10003254#define DMA_CH_1_CS_SPMU_SECTION                   0x10003255#define mmDMA_CH_1_BMON_CTI_BASE                   0x7FFE525000ull3256#define DMA_CH_1_BMON_CTI_MAX_OFFSET               0x10003257#define DMA_CH_1_BMON_CTI_SECTION                  0x10003258#define mmDMA_CH_1_USER_CTI_BASE                   0x7FFE526000ull3259#define DMA_CH_1_USER_CTI_MAX_OFFSET               0x10003260#define DMA_CH_1_USER_CTI_SECTION                  0x10003261#define mmDMA_CH_1_BMON_0_BASE                     0x7FFE527000ull3262#define DMA_CH_1_BMON_0_MAX_OFFSET                 0x10003263#define DMA_CH_1_BMON_0_SECTION                    0x10003264#define mmDMA_CH_1_BMON_1_BASE                     0x7FFE528000ull3265#define DMA_CH_1_BMON_1_MAX_OFFSET                 0x10003266#define DMA_CH_1_BMON_1_SECTION                    0x190003267#define mmDMA_CH_2_CS_STM_BASE                     0x7FFE541000ull3268#define DMA_CH_2_CS_STM_MAX_OFFSET                 0x10003269#define DMA_CH_2_CS_STM_SECTION                    0x10003270#define mmDMA_CH_2_CS_CTI_BASE                     0x7FFE542000ull3271#define DMA_CH_2_CS_CTI_MAX_OFFSET                 0x10003272#define DMA_CH_2_CS_CTI_SECTION                    0x10003273#define mmDMA_CH_2_CS_ETF_BASE                     0x7FFE543000ull3274#define DMA_CH_2_CS_ETF_MAX_OFFSET                 0x10003275#define DMA_CH_2_CS_ETF_SECTION                    0x10003276#define mmDMA_CH_2_CS_SPMU_BASE                    0x7FFE544000ull3277#define DMA_CH_2_CS_SPMU_MAX_OFFSET                0x10003278#define DMA_CH_2_CS_SPMU_SECTION                   0x10003279#define mmDMA_CH_2_BMON_CTI_BASE                   0x7FFE545000ull3280#define DMA_CH_2_BMON_CTI_MAX_OFFSET               0x10003281#define DMA_CH_2_BMON_CTI_SECTION                  0x10003282#define mmDMA_CH_2_USER_CTI_BASE                   0x7FFE546000ull3283#define DMA_CH_2_USER_CTI_MAX_OFFSET               0x10003284#define DMA_CH_2_USER_CTI_SECTION                  0x10003285#define mmDMA_CH_2_BMON_0_BASE                     0x7FFE547000ull3286#define DMA_CH_2_BMON_0_MAX_OFFSET                 0x10003287#define DMA_CH_2_BMON_0_SECTION                    0x10003288#define mmDMA_CH_2_BMON_1_BASE                     0x7FFE548000ull3289#define DMA_CH_2_BMON_1_MAX_OFFSET                 0x10003290#define DMA_CH_2_BMON_1_SECTION                    0x190003291#define mmDMA_CH_3_CS_STM_BASE                     0x7FFE561000ull3292#define DMA_CH_3_CS_STM_MAX_OFFSET                 0x10003293#define DMA_CH_3_CS_STM_SECTION                    0x10003294#define mmDMA_CH_3_CS_CTI_BASE                     0x7FFE562000ull3295#define DMA_CH_3_CS_CTI_MAX_OFFSET                 0x10003296#define DMA_CH_3_CS_CTI_SECTION                    0x10003297#define mmDMA_CH_3_CS_ETF_BASE                     0x7FFE563000ull3298#define DMA_CH_3_CS_ETF_MAX_OFFSET                 0x10003299#define DMA_CH_3_CS_ETF_SECTION                    0x10003300#define mmDMA_CH_3_CS_SPMU_BASE                    0x7FFE564000ull3301#define DMA_CH_3_CS_SPMU_MAX_OFFSET                0x10003302#define DMA_CH_3_CS_SPMU_SECTION                   0x10003303#define mmDMA_CH_3_BMON_CTI_BASE                   0x7FFE565000ull3304#define DMA_CH_3_BMON_CTI_MAX_OFFSET               0x10003305#define DMA_CH_3_BMON_CTI_SECTION                  0x10003306#define mmDMA_CH_3_USER_CTI_BASE                   0x7FFE566000ull3307#define DMA_CH_3_USER_CTI_MAX_OFFSET               0x10003308#define DMA_CH_3_USER_CTI_SECTION                  0x10003309#define mmDMA_CH_3_BMON_0_BASE                     0x7FFE567000ull3310#define DMA_CH_3_BMON_0_MAX_OFFSET                 0x10003311#define DMA_CH_3_BMON_0_SECTION                    0x10003312#define mmDMA_CH_3_BMON_1_BASE                     0x7FFE568000ull3313#define DMA_CH_3_BMON_1_MAX_OFFSET                 0x10003314#define DMA_CH_3_BMON_1_SECTION                    0x190003315#define mmDMA_CH_4_CS_STM_BASE                     0x7FFE581000ull3316#define DMA_CH_4_CS_STM_MAX_OFFSET                 0x10003317#define DMA_CH_4_CS_STM_SECTION                    0x10003318#define mmDMA_CH_4_CS_CTI_BASE                     0x7FFE582000ull3319#define DMA_CH_4_CS_CTI_MAX_OFFSET                 0x10003320#define DMA_CH_4_CS_CTI_SECTION                    0x10003321#define mmDMA_CH_4_CS_ETF_BASE                     0x7FFE583000ull3322#define DMA_CH_4_CS_ETF_MAX_OFFSET                 0x10003323#define DMA_CH_4_CS_ETF_SECTION                    0x10003324#define mmDMA_CH_4_CS_SPMU_BASE                    0x7FFE584000ull3325#define DMA_CH_4_CS_SPMU_MAX_OFFSET                0x10003326#define DMA_CH_4_CS_SPMU_SECTION                   0x10003327#define mmDMA_CH_4_BMON_CTI_BASE                   0x7FFE585000ull3328#define DMA_CH_4_BMON_CTI_MAX_OFFSET               0x10003329#define DMA_CH_4_BMON_CTI_SECTION                  0x10003330#define mmDMA_CH_4_USER_CTI_BASE                   0x7FFE586000ull3331#define DMA_CH_4_USER_CTI_MAX_OFFSET               0x10003332#define DMA_CH_4_USER_CTI_SECTION                  0x10003333#define mmDMA_CH_4_BMON_0_BASE                     0x7FFE587000ull3334#define DMA_CH_4_BMON_0_MAX_OFFSET                 0x10003335#define DMA_CH_4_BMON_0_SECTION                    0x10003336#define mmDMA_CH_4_BMON_1_BASE                     0x7FFE588000ull3337#define DMA_CH_4_BMON_1_MAX_OFFSET                 0x10003338#define DMA_CH_4_BMON_1_SECTION                    0x190003339#define mmDMA_CH_5_CS_STM_BASE                     0x7FFE5A1000ull3340#define DMA_CH_5_CS_STM_MAX_OFFSET                 0x10003341#define DMA_CH_5_CS_STM_SECTION                    0x10003342#define mmDMA_CH_5_CS_CTI_BASE                     0x7FFE5A2000ull3343#define DMA_CH_5_CS_CTI_MAX_OFFSET                 0x10003344#define DMA_CH_5_CS_CTI_SECTION                    0x10003345#define mmDMA_CH_5_CS_ETF_BASE                     0x7FFE5A3000ull3346#define DMA_CH_5_CS_ETF_MAX_OFFSET                 0x10003347#define DMA_CH_5_CS_ETF_SECTION                    0x10003348#define mmDMA_CH_5_CS_SPMU_BASE                    0x7FFE5A4000ull3349#define DMA_CH_5_CS_SPMU_MAX_OFFSET                0x10003350#define DMA_CH_5_CS_SPMU_SECTION                   0x10003351#define mmDMA_CH_5_BMON_CTI_BASE                   0x7FFE5A5000ull3352#define DMA_CH_5_BMON_CTI_MAX_OFFSET               0x10003353#define DMA_CH_5_BMON_CTI_SECTION                  0x10003354#define mmDMA_CH_5_USER_CTI_BASE                   0x7FFE5A6000ull3355#define DMA_CH_5_USER_CTI_MAX_OFFSET               0x10003356#define DMA_CH_5_USER_CTI_SECTION                  0x10003357#define mmDMA_CH_5_BMON_0_BASE                     0x7FFE5A7000ull3358#define DMA_CH_5_BMON_0_MAX_OFFSET                 0x10003359#define DMA_CH_5_BMON_0_SECTION                    0x10003360#define mmDMA_CH_5_BMON_1_BASE                     0x7FFE5A8000ull3361#define DMA_CH_5_BMON_1_MAX_OFFSET                 0x10003362#define DMA_CH_5_BMON_1_SECTION                    0x190003363#define mmDMA_CH_6_CS_STM_BASE                     0x7FFE5C1000ull3364#define DMA_CH_6_CS_STM_MAX_OFFSET                 0x10003365#define DMA_CH_6_CS_STM_SECTION                    0x10003366#define mmDMA_CH_6_CS_CTI_BASE                     0x7FFE5C2000ull3367#define DMA_CH_6_CS_CTI_MAX_OFFSET                 0x10003368#define DMA_CH_6_CS_CTI_SECTION                    0x10003369#define mmDMA_CH_6_CS_ETF_BASE                     0x7FFE5C3000ull3370#define DMA_CH_6_CS_ETF_MAX_OFFSET                 0x10003371#define DMA_CH_6_CS_ETF_SECTION                    0x10003372#define mmDMA_CH_6_CS_SPMU_BASE                    0x7FFE5C4000ull3373#define DMA_CH_6_CS_SPMU_MAX_OFFSET                0x10003374#define DMA_CH_6_CS_SPMU_SECTION                   0x10003375#define mmDMA_CH_6_BMON_CTI_BASE                   0x7FFE5C5000ull3376#define DMA_CH_6_BMON_CTI_MAX_OFFSET               0x10003377#define DMA_CH_6_BMON_CTI_SECTION                  0x10003378#define mmDMA_CH_6_USER_CTI_BASE                   0x7FFE5C6000ull3379#define DMA_CH_6_USER_CTI_MAX_OFFSET               0x10003380#define DMA_CH_6_USER_CTI_SECTION                  0x10003381#define mmDMA_CH_6_BMON_0_BASE                     0x7FFE5C7000ull3382#define DMA_CH_6_BMON_0_MAX_OFFSET                 0x10003383#define DMA_CH_6_BMON_0_SECTION                    0x10003384#define mmDMA_CH_6_BMON_1_BASE                     0x7FFE5C8000ull3385#define DMA_CH_6_BMON_1_MAX_OFFSET                 0x10003386#define DMA_CH_6_BMON_1_SECTION                    0x190003387#define mmDMA_CH_7_CS_STM_BASE                     0x7FFE5E1000ull3388#define DMA_CH_7_CS_STM_MAX_OFFSET                 0x10003389#define DMA_CH_7_CS_STM_SECTION                    0x10003390#define mmDMA_CH_7_CS_CTI_BASE                     0x7FFE5E2000ull3391#define DMA_CH_7_CS_CTI_MAX_OFFSET                 0x10003392#define DMA_CH_7_CS_CTI_SECTION                    0x10003393#define mmDMA_CH_7_CS_ETF_BASE                     0x7FFE5E3000ull3394#define DMA_CH_7_CS_ETF_MAX_OFFSET                 0x10003395#define DMA_CH_7_CS_ETF_SECTION                    0x10003396#define mmDMA_CH_7_CS_SPMU_BASE                    0x7FFE5E4000ull3397#define DMA_CH_7_CS_SPMU_MAX_OFFSET                0x10003398#define DMA_CH_7_CS_SPMU_SECTION                   0x10003399#define mmDMA_CH_7_BMON_CTI_BASE                   0x7FFE5E5000ull3400#define DMA_CH_7_BMON_CTI_MAX_OFFSET               0x10003401#define DMA_CH_7_BMON_CTI_SECTION                  0x10003402#define mmDMA_CH_7_USER_CTI_BASE                   0x7FFE5E6000ull3403#define DMA_CH_7_USER_CTI_MAX_OFFSET               0x10003404#define DMA_CH_7_USER_CTI_SECTION                  0x10003405#define mmDMA_CH_7_BMON_0_BASE                     0x7FFE5E7000ull3406#define DMA_CH_7_BMON_0_MAX_OFFSET                 0x10003407#define DMA_CH_7_BMON_0_SECTION                    0x10003408#define mmDMA_CH_7_BMON_1_BASE                     0x7FFE5E8000ull3409#define DMA_CH_7_BMON_1_MAX_OFFSET                 0x10003410#define DMA_CH_7_BMON_1_SECTION                    0x180003411#define mmNIC_TPC_FUNNEL_W_S_BASE                  0x7FFE600000ull3412#define NIC_TPC_FUNNEL_W_S_MAX_OFFSET              0x10003413#define NIC_TPC_FUNNEL_W_S_SECTION                 0x800003414#define mmNIC_TPC_FUNNEL_E_S_BASE                  0x7FFE680000ull3415#define NIC_TPC_FUNNEL_E_S_MAX_OFFSET              0x10003416#define NIC_TPC_FUNNEL_E_S_SECTION                 0x800003417#define mmNIC_TPC_FUNNEL_W_N_BASE                  0x7FFE700000ull3418#define NIC_TPC_FUNNEL_W_N_MAX_OFFSET              0x10003419#define NIC_TPC_FUNNEL_W_N_SECTION                 0x800003420#define mmNIC_TPC_FUNNEL_E_N_BASE                  0x7FFE780000ull3421#define NIC_TPC_FUNNEL_E_N_MAX_OFFSET              0x10003422#define NIC_TPC_FUNNEL_E_N_SECTION                 0x800003423#define mmCA53_BASE                                0x7FFE800000ull3424#define CA53_MAX_OFFSET                            0x1410003425#define CA53_SECTION                               0x4000003426#define mmPCI_ROM_TABLE_BASE                       0x7FFEC00000ull3427#define PCI_ROM_TABLE_MAX_OFFSET                   0x10003428#define PCI_ROM_TABLE_SECTION                      0x10003429#define mmPCIE_STM_BASE                            0x7FFEC01000ull3430#define PCIE_STM_MAX_OFFSET                        0x10003431#define PCIE_STM_SECTION                           0x10003432#define mmPCIE_ETF_BASE                            0x7FFEC02000ull3433#define PCIE_ETF_MAX_OFFSET                        0x10003434#define PCIE_ETF_SECTION                           0x10003435#define mmPCIE_CTI_0_BASE                          0x7FFEC03000ull3436#define PCIE_CTI_0_MAX_OFFSET                      0x10003437#define PCIE_CTI_0_SECTION                         0x10003438#define mmPCIE_SPMU_BASE                           0x7FFEC04000ull3439#define PCIE_SPMU_MAX_OFFSET                       0x10003440#define PCIE_SPMU_SECTION                          0x10003441#define mmPCIE_CTI_1_BASE                          0x7FFEC05000ull3442#define PCIE_CTI_1_MAX_OFFSET                      0x10003443#define PCIE_CTI_1_SECTION                         0x10003444#define mmPCIE_FUNNEL_BASE                         0x7FFEC06000ull3445#define PCIE_FUNNEL_MAX_OFFSET                     0x10003446#define PCIE_FUNNEL_SECTION                        0x10003447#define mmPCIE_BMON_MSTR_WR_BASE                   0x7FFEC07000ull3448#define PCIE_BMON_MSTR_WR_MAX_OFFSET               0x10003449#define PCIE_BMON_MSTR_WR_SECTION                  0x10003450#define mmPCIE_BMON_MSTR_RD_BASE                   0x7FFEC08000ull3451#define PCIE_BMON_MSTR_RD_MAX_OFFSET               0x10003452#define PCIE_BMON_MSTR_RD_SECTION                  0x10003453#define mmPCIE_BMON_SLV_WR_BASE                    0x7FFEC09000ull3454#define PCIE_BMON_SLV_WR_MAX_OFFSET                0x10003455#define PCIE_BMON_SLV_WR_SECTION                   0x10003456#define mmPCIE_BMON_SLV_RD_BASE                    0x7FFEC0A000ull3457#define PCIE_BMON_SLV_RD_MAX_OFFSET                0x10003458#define PCIE_BMON_SLV_RD_SECTION                   0x70003459#define mmMMU_CS_STM_BASE                          0x7FFEC11000ull3460#define MMU_CS_STM_MAX_OFFSET                      0x10003461#define MMU_CS_STM_SECTION                         0x10003462#define mmMMU_CS_CTI_BASE                          0x7FFEC12000ull3463#define MMU_CS_CTI_MAX_OFFSET                      0x10003464#define MMU_CS_CTI_SECTION                         0x10003465#define mmMMU_CS_ETF_BASE                          0x7FFEC13000ull3466#define MMU_CS_ETF_MAX_OFFSET                      0x10003467#define MMU_CS_ETF_SECTION                         0x10003468#define mmMMU_CS_SPMU_BASE                         0x7FFEC14000ull3469#define MMU_CS_SPMU_MAX_OFFSET                     0x10003470#define MMU_CS_SPMU_SECTION                        0x10003471#define mmMMU_BMON_CTI_BASE                        0x7FFEC15000ull3472#define MMU_BMON_CTI_MAX_OFFSET                    0x10003473#define MMU_BMON_CTI_SECTION                       0x10003474#define mmMMU_USER_CTI_BASE                        0x7FFEC16000ull3475#define MMU_USER_CTI_MAX_OFFSET                    0x10003476#define MMU_USER_CTI_SECTION                       0x10003477#define mmMMU_BMON_0_BASE                          0x7FFEC17000ull3478#define MMU_BMON_0_MAX_OFFSET                      0x10003479#define MMU_BMON_0_SECTION                         0x10003480#define mmMMU_BMON_1_BASE                          0x7FFEC18000ull3481#define MMU_BMON_1_MAX_OFFSET                      0x10003482#define MMU_BMON_1_SECTION                         0x280003483#define mmPSOC_CTI_BASE                            0x7FFEC40000ull3484#define PSOC_CTI_MAX_OFFSET                        0x10003485#define PSOC_CTI_SECTION                           0x10003486#define mmPSOC_STM_BASE                            0x7FFEC41000ull3487#define PSOC_STM_MAX_OFFSET                        0x10003488#define PSOC_STM_SECTION                           0x10003489#define mmPSOC_FUNNEL_BASE                         0x7FFEC42000ull3490#define PSOC_FUNNEL_MAX_OFFSET                     0x10003491#define PSOC_FUNNEL_SECTION                        0x10003492#define mmPSOC_ETR_BASE                            0x7FFEC43000ull3493#define PSOC_ETR_MAX_OFFSET                        0x10003494#define PSOC_ETR_SECTION                           0x10003495#define mmPSOC_ETF_BASE                            0x7FFEC44000ull3496#define PSOC_ETF_MAX_OFFSET                        0x10003497#define PSOC_ETF_SECTION                           0x10003498#define mmPSOC_TS_CTI_BASE                         0x7FFEC45000ull3499#define PSOC_TS_CTI_MAX_OFFSET                     0x10003500#define PSOC_TS_CTI_SECTION                        0xB0003501#define mmTOP_ROM_TABLE_BASE                       0x7FFEC50000ull3502#define TOP_ROM_TABLE_MAX_OFFSET                   0x10003503#define TOP_ROM_TABLE_SECTION                      0x700003504#define mmNIC0_ROM_TABLE_BASE                      0x7FFECC0000ull3505#define NIC0_ROM_TABLE_MAX_OFFSET                  0x10003506#define NIC0_ROM_TABLE_SECTION                     0x10003507#define mmSTM_0_NIC0_DBG_BASE                      0x7FFECC1000ull3508#define STM_0_NIC0_DBG_MAX_OFFSET                  0x210003509#define STM_0_NIC0_DBG_SECTION                     0x10003510#define mmCTI_0_NIC0_DBG_BASE                      0x7FFECC2000ull3511#define CTI_0_NIC0_DBG_MAX_OFFSET                  0x10003512#define CTI_0_NIC0_DBG_SECTION                     0x10003513#define mmETF_0_NIC0_DBG_BASE                      0x7FFECC3000ull3514#define ETF_0_NIC0_DBG_MAX_OFFSET                  0x10003515#define ETF_0_NIC0_DBG_SECTION                     0x10003516#define mmSPMU_0_NIC0_DBG_BASE                     0x7FFECC4000ull3517#define SPMU_0_NIC0_DBG_MAX_OFFSET                 0x10003518#define SPMU_0_NIC0_DBG_SECTION                    0x20003519#define mmUSER_CTI_0_NIC0_DBG_BASE                 0x7FFECC6000ull3520#define USER_CTI_0_NIC0_DBG_MAX_OFFSET             0x10003521#define USER_CTI_0_NIC0_DBG_SECTION                0xB0003522#define mmSTM_1_NIC0_DBG_BASE                      0x7FFECD1000ull3523#define STM_1_NIC0_DBG_MAX_OFFSET                  0x10003524#define STM_1_NIC0_DBG_SECTION                     0x10003525#define mmCTI_1_NIC0_DBG_BASE                      0x7FFECD2000ull3526#define CTI_1_NIC0_DBG_MAX_OFFSET                  0x10003527#define CTI_1_NIC0_DBG_SECTION                     0x10003528#define mmETF_1_NIC0_DBG_BASE                      0x7FFECD3000ull3529#define ETF_1_NIC0_DBG_MAX_OFFSET                  0x10003530#define ETF_1_NIC0_DBG_SECTION                     0x10003531#define mmSPMU_1_NIC0_DBG_BASE                     0x7FFECD4000ull3532#define SPMU_1_NIC0_DBG_MAX_OFFSET                 0x10003533#define SPMU_1_NIC0_DBG_SECTION                    0x10003534#define mmBMON_CTI_NIC0_DBG_BASE                   0x7FFECD5000ull3535#define BMON_CTI_NIC0_DBG_MAX_OFFSET               0x10003536#define BMON_CTI_NIC0_DBG_SECTION                  0x10003537#define mmUSER_CTI_1_NIC0_DBG_BASE                 0x7FFECD6000ull3538#define USER_CTI_1_NIC0_DBG_MAX_OFFSET             0x10003539#define USER_CTI_1_NIC0_DBG_SECTION                0x10003540#define mmBMON0_NIC0_DBG_BASE                      0x7FFECD7000ull3541#define BMON0_NIC0_DBG_MAX_OFFSET                  0x10003542#define BMON0_NIC0_DBG_SECTION                     0x10003543#define mmBMON1_NIC0_DBG_BASE                      0x7FFECD8000ull3544#define BMON1_NIC0_DBG_MAX_OFFSET                  0x10003545#define BMON1_NIC0_DBG_SECTION                     0x10003546#define mmBMON2_NIC0_DBG_BASE                      0x7FFECD9000ull3547#define BMON2_NIC0_DBG_MAX_OFFSET                  0x10003548#define BMON2_NIC0_DBG_SECTION                     0x10003549#define mmBMON3_NIC0_DBG_BASE                      0x7FFECDA000ull3550#define BMON3_NIC0_DBG_MAX_OFFSET                  0x10003551#define BMON3_NIC0_DBG_SECTION                     0x10003552#define mmBMON4_NIC0_DBG_BASE                      0x7FFECDB000ull3553#define BMON4_NIC0_DBG_MAX_OFFSET                  0x10003554#define BMON4_NIC0_DBG_SECTION                     0x60003555#define mmFUNNEL_NIC0_DBG_BASE                     0x7FFECE1000ull3556#define FUNNEL_NIC0_DBG_MAX_OFFSET                 0x10003557#define FUNNEL_NIC0_DBG_SECTION                    0x1F0003558#define mmNIC1_ROM_TABLE_BASE                      0x7FFED00000ull3559#define NIC1_ROM_TABLE_MAX_OFFSET                  0x10003560#define NIC1_ROM_TABLE_SECTION                     0x10003561#define mmSTM_0_NIC1_DBG_BASE                      0x7FFED01000ull3562#define STM_0_NIC1_DBG_MAX_OFFSET                  0x210003563#define STM_0_NIC1_DBG_SECTION                     0x10003564#define mmCTI_0_NIC1_DBG_BASE                      0x7FFED02000ull3565#define CTI_0_NIC1_DBG_MAX_OFFSET                  0x10003566#define CTI_0_NIC1_DBG_SECTION                     0x10003567#define mmETF_0_NIC1_DBG_BASE                      0x7FFED03000ull3568#define ETF_0_NIC1_DBG_MAX_OFFSET                  0x10003569#define ETF_0_NIC1_DBG_SECTION                     0x10003570#define mmSPMU_0_NIC1_DBG_BASE                     0x7FFED04000ull3571#define SPMU_0_NIC1_DBG_MAX_OFFSET                 0x10003572#define SPMU_0_NIC1_DBG_SECTION                    0x20003573#define mmUSER_CTI_0_NIC1_DBG_BASE                 0x7FFED06000ull3574#define USER_CTI_0_NIC1_DBG_MAX_OFFSET             0x10003575#define USER_CTI_0_NIC1_DBG_SECTION                0xB0003576#define mmSTM_1_NIC1_DBG_BASE                      0x7FFED11000ull3577#define STM_1_NIC1_DBG_MAX_OFFSET                  0x10003578#define STM_1_NIC1_DBG_SECTION                     0x10003579#define mmCTI_1_NIC1_DBG_BASE                      0x7FFED12000ull3580#define CTI_1_NIC1_DBG_MAX_OFFSET                  0x10003581#define CTI_1_NIC1_DBG_SECTION                     0x10003582#define mmETF_1_NIC1_DBG_BASE                      0x7FFED13000ull3583#define ETF_1_NIC1_DBG_MAX_OFFSET                  0x10003584#define ETF_1_NIC1_DBG_SECTION                     0x10003585#define mmSPMU_1_NIC1_DBG_BASE                     0x7FFED14000ull3586#define SPMU_1_NIC1_DBG_MAX_OFFSET                 0x10003587#define SPMU_1_NIC1_DBG_SECTION                    0x10003588#define mmBMON_CTI_NIC1_DBG_BASE                   0x7FFED15000ull3589#define BMON_CTI_NIC1_DBG_MAX_OFFSET               0x10003590#define BMON_CTI_NIC1_DBG_SECTION                  0x10003591#define mmUSER_CTI_1_NIC1_DBG_BASE                 0x7FFED16000ull3592#define USER_CTI_1_NIC1_DBG_MAX_OFFSET             0x10003593#define USER_CTI_1_NIC1_DBG_SECTION                0x10003594#define mmBMON0_NIC1_DBG_BASE                      0x7FFED17000ull3595#define BMON0_NIC1_DBG_MAX_OFFSET                  0x10003596#define BMON0_NIC1_DBG_SECTION                     0x10003597#define mmBMON1_NIC1_DBG_BASE                      0x7FFED18000ull3598#define BMON1_NIC1_DBG_MAX_OFFSET                  0x10003599#define BMON1_NIC1_DBG_SECTION                     0x10003600#define mmBMON2_NIC1_DBG_BASE                      0x7FFED19000ull3601#define BMON2_NIC1_DBG_MAX_OFFSET                  0x10003602#define BMON2_NIC1_DBG_SECTION                     0x10003603#define mmBMON3_NIC1_DBG_BASE                      0x7FFED1A000ull3604#define BMON3_NIC1_DBG_MAX_OFFSET                  0x10003605#define BMON3_NIC1_DBG_SECTION                     0x10003606#define mmBMON4_NIC1_DBG_BASE                      0x7FFED1B000ull3607#define BMON4_NIC1_DBG_MAX_OFFSET                  0x10003608#define BMON4_NIC1_DBG_SECTION                     0x60003609#define mmFUNNEL_NIC1_DBG_BASE                     0x7FFED21000ull3610#define FUNNEL_NIC1_DBG_MAX_OFFSET                 0x10003611#define FUNNEL_NIC1_DBG_SECTION                    0x1F0003612#define mmNIC2_ROM_TABLE_BASE                      0x7FFED40000ull3613#define NIC2_ROM_TABLE_MAX_OFFSET                  0x10003614#define NIC2_ROM_TABLE_SECTION                     0x10003615#define mmSTM_0_NIC2_DBG_BASE                      0x7FFED41000ull3616#define STM_0_NIC2_DBG_MAX_OFFSET                  0x210003617#define STM_0_NIC2_DBG_SECTION                     0x10003618#define mmCTI_0_NIC2_DBG_BASE                      0x7FFED42000ull3619#define CTI_0_NIC2_DBG_MAX_OFFSET                  0x10003620#define CTI_0_NIC2_DBG_SECTION                     0x10003621#define mmETF_0_NIC2_DBG_BASE                      0x7FFED43000ull3622#define ETF_0_NIC2_DBG_MAX_OFFSET                  0x10003623#define ETF_0_NIC2_DBG_SECTION                     0x10003624#define mmSPMU_0_NIC2_DBG_BASE                     0x7FFED44000ull3625#define SPMU_0_NIC2_DBG_MAX_OFFSET                 0x10003626#define SPMU_0_NIC2_DBG_SECTION                    0x20003627#define mmUSER_CTI_0_NIC2_DBG_BASE                 0x7FFED46000ull3628#define USER_CTI_0_NIC2_DBG_MAX_OFFSET             0x10003629#define USER_CTI_0_NIC2_DBG_SECTION                0xB0003630#define mmSTM_1_NIC2_DBG_BASE                      0x7FFED51000ull3631#define STM_1_NIC2_DBG_MAX_OFFSET                  0x10003632#define STM_1_NIC2_DBG_SECTION                     0x10003633#define mmCTI_1_NIC2_DBG_BASE                      0x7FFED52000ull3634#define CTI_1_NIC2_DBG_MAX_OFFSET                  0x10003635#define CTI_1_NIC2_DBG_SECTION                     0x10003636#define mmETF_1_NIC2_DBG_BASE                      0x7FFED53000ull3637#define ETF_1_NIC2_DBG_MAX_OFFSET                  0x10003638#define ETF_1_NIC2_DBG_SECTION                     0x10003639#define mmSPMU_1_NIC2_DBG_BASE                     0x7FFED54000ull3640#define SPMU_1_NIC2_DBG_MAX_OFFSET                 0x10003641#define SPMU_1_NIC2_DBG_SECTION                    0x10003642#define mmBMON_CTI_NIC2_DBG_BASE                   0x7FFED55000ull3643#define BMON_CTI_NIC2_DBG_MAX_OFFSET               0x10003644#define BMON_CTI_NIC2_DBG_SECTION                  0x10003645#define mmUSER_CTI_1_NIC2_DBG_BASE                 0x7FFED56000ull3646#define USER_CTI_1_NIC2_DBG_MAX_OFFSET             0x10003647#define USER_CTI_1_NIC2_DBG_SECTION                0x10003648#define mmBMON0_NIC2_DBG_BASE                      0x7FFED57000ull3649#define BMON0_NIC2_DBG_MAX_OFFSET                  0x10003650#define BMON0_NIC2_DBG_SECTION                     0x10003651#define mmBMON1_NIC2_DBG_BASE                      0x7FFED58000ull3652#define BMON1_NIC2_DBG_MAX_OFFSET                  0x10003653#define BMON1_NIC2_DBG_SECTION                     0x10003654#define mmBMON2_NIC2_DBG_BASE                      0x7FFED59000ull3655#define BMON2_NIC2_DBG_MAX_OFFSET                  0x10003656#define BMON2_NIC2_DBG_SECTION                     0x10003657#define mmBMON3_NIC2_DBG_BASE                      0x7FFED5A000ull3658#define BMON3_NIC2_DBG_MAX_OFFSET                  0x10003659#define BMON3_NIC2_DBG_SECTION                     0x10003660#define mmBMON4_NIC2_DBG_BASE                      0x7FFED5B000ull3661#define BMON4_NIC2_DBG_MAX_OFFSET                  0x10003662#define BMON4_NIC2_DBG_SECTION                     0x60003663#define mmFUNNEL_NIC2_DBG_BASE                     0x7FFED61000ull3664#define FUNNEL_NIC2_DBG_MAX_OFFSET                 0x10003665#define FUNNEL_NIC2_DBG_SECTION                    0x1F0003666#define mmNIC3_ROM_TABLE_BASE                      0x7FFED80000ull3667#define NIC3_ROM_TABLE_MAX_OFFSET                  0x10003668#define NIC3_ROM_TABLE_SECTION                     0x10003669#define mmSTM_0_NIC3_DBG_BASE                      0x7FFED81000ull3670#define STM_0_NIC3_DBG_MAX_OFFSET                  0x210003671#define STM_0_NIC3_DBG_SECTION                     0x10003672#define mmCTI_0_NIC3_DBG_BASE                      0x7FFED82000ull3673#define CTI_0_NIC3_DBG_MAX_OFFSET                  0x10003674#define CTI_0_NIC3_DBG_SECTION                     0x10003675#define mmETF_0_NIC3_DBG_BASE                      0x7FFED83000ull3676#define ETF_0_NIC3_DBG_MAX_OFFSET                  0x10003677#define ETF_0_NIC3_DBG_SECTION                     0x10003678#define mmSPMU_0_NIC3_DBG_BASE                     0x7FFED84000ull3679#define SPMU_0_NIC3_DBG_MAX_OFFSET                 0x10003680#define SPMU_0_NIC3_DBG_SECTION                    0x20003681#define mmUSER_CTI_0_NIC3_DBG_BASE                 0x7FFED86000ull3682#define USER_CTI_0_NIC3_DBG_MAX_OFFSET             0x10003683#define USER_CTI_0_NIC3_DBG_SECTION                0xB0003684#define mmSTM_1_NIC3_DBG_BASE                      0x7FFED91000ull3685#define STM_1_NIC3_DBG_MAX_OFFSET                  0x10003686#define STM_1_NIC3_DBG_SECTION                     0x10003687#define mmCTI_1_NIC3_DBG_BASE                      0x7FFED92000ull3688#define CTI_1_NIC3_DBG_MAX_OFFSET                  0x10003689#define CTI_1_NIC3_DBG_SECTION                     0x10003690#define mmETF_1_NIC3_DBG_BASE                      0x7FFED93000ull3691#define ETF_1_NIC3_DBG_MAX_OFFSET                  0x10003692#define ETF_1_NIC3_DBG_SECTION                     0x10003693#define mmSPMU_1_NIC3_DBG_BASE                     0x7FFED94000ull3694#define SPMU_1_NIC3_DBG_MAX_OFFSET                 0x10003695#define SPMU_1_NIC3_DBG_SECTION                    0x10003696#define mmBMON_CTI_NIC3_DBG_BASE                   0x7FFED95000ull3697#define BMON_CTI_NIC3_DBG_MAX_OFFSET               0x10003698#define BMON_CTI_NIC3_DBG_SECTION                  0x10003699#define mmUSER_CTI_1_NIC3_DBG_BASE                 0x7FFED96000ull3700#define USER_CTI_1_NIC3_DBG_MAX_OFFSET             0x10003701#define USER_CTI_1_NIC3_DBG_SECTION                0x10003702#define mmBMON0_NIC3_DBG_BASE                      0x7FFED97000ull3703#define BMON0_NIC3_DBG_MAX_OFFSET                  0x10003704#define BMON0_NIC3_DBG_SECTION                     0x10003705#define mmBMON1_NIC3_DBG_BASE                      0x7FFED98000ull3706#define BMON1_NIC3_DBG_MAX_OFFSET                  0x10003707#define BMON1_NIC3_DBG_SECTION                     0x10003708#define mmBMON2_NIC3_DBG_BASE                      0x7FFED99000ull3709#define BMON2_NIC3_DBG_MAX_OFFSET                  0x10003710#define BMON2_NIC3_DBG_SECTION                     0x10003711#define mmBMON3_NIC3_DBG_BASE                      0x7FFED9A000ull3712#define BMON3_NIC3_DBG_MAX_OFFSET                  0x10003713#define BMON3_NIC3_DBG_SECTION                     0x10003714#define mmBMON4_NIC3_DBG_BASE                      0x7FFED9B000ull3715#define BMON4_NIC3_DBG_MAX_OFFSET                  0x10003716#define BMON4_NIC3_DBG_SECTION                     0x60003717#define mmFUNNEL_NIC3_DBG_BASE                     0x7FFEDA1000ull3718#define FUNNEL_NIC3_DBG_MAX_OFFSET                 0x10003719#define FUNNEL_NIC3_DBG_SECTION                    0x1F0003720#define mmNIC4_ROM_TABLE_BASE                      0x7FFEDC0000ull3721#define NIC4_ROM_TABLE_MAX_OFFSET                  0x10003722#define NIC4_ROM_TABLE_SECTION                     0x10003723#define mmSTM_0_NIC4_DBG_BASE                      0x7FFEDC1000ull3724#define STM_0_NIC4_DBG_MAX_OFFSET                  0x210003725#define STM_0_NIC4_DBG_SECTION                     0x10003726#define mmCTI_0_NIC4_DBG_BASE                      0x7FFEDC2000ull3727#define CTI_0_NIC4_DBG_MAX_OFFSET                  0x10003728#define CTI_0_NIC4_DBG_SECTION                     0x10003729#define mmETF_0_NIC4_DBG_BASE                      0x7FFEDC3000ull3730#define ETF_0_NIC4_DBG_MAX_OFFSET                  0x10003731#define ETF_0_NIC4_DBG_SECTION                     0x10003732#define mmSPMU_0_NIC4_DBG_BASE                     0x7FFEDC4000ull3733#define SPMU_0_NIC4_DBG_MAX_OFFSET                 0x10003734#define SPMU_0_NIC4_DBG_SECTION                    0x20003735#define mmUSER_CTI_0_NIC4_DBG_BASE                 0x7FFEDC6000ull3736#define USER_CTI_0_NIC4_DBG_MAX_OFFSET             0x10003737#define USER_CTI_0_NIC4_DBG_SECTION                0xB0003738#define mmSTM_1_NIC4_DBG_BASE                      0x7FFEDD1000ull3739#define STM_1_NIC4_DBG_MAX_OFFSET                  0x10003740#define STM_1_NIC4_DBG_SECTION                     0x10003741#define mmCTI_1_NIC4_DBG_BASE                      0x7FFEDD2000ull3742#define CTI_1_NIC4_DBG_MAX_OFFSET                  0x10003743#define CTI_1_NIC4_DBG_SECTION                     0x10003744#define mmETF_1_NIC4_DBG_BASE                      0x7FFEDD3000ull3745#define ETF_1_NIC4_DBG_MAX_OFFSET                  0x10003746#define ETF_1_NIC4_DBG_SECTION                     0x10003747#define mmSPMU_1_NIC4_DBG_BASE                     0x7FFEDD4000ull3748#define SPMU_1_NIC4_DBG_MAX_OFFSET                 0x10003749#define SPMU_1_NIC4_DBG_SECTION                    0x10003750#define mmBMON_CTI_NIC4_DBG_BASE                   0x7FFEDD5000ull3751#define BMON_CTI_NIC4_DBG_MAX_OFFSET               0x10003752#define BMON_CTI_NIC4_DBG_SECTION                  0x10003753#define mmUSER_CTI_1_NIC4_DBG_BASE                 0x7FFEDD6000ull3754#define USER_CTI_1_NIC4_DBG_MAX_OFFSET             0x10003755#define USER_CTI_1_NIC4_DBG_SECTION                0x10003756#define mmBMON0_NIC4_DBG_BASE                      0x7FFEDD7000ull3757#define BMON0_NIC4_DBG_MAX_OFFSET                  0x10003758#define BMON0_NIC4_DBG_SECTION                     0x10003759#define mmBMON1_NIC4_DBG_BASE                      0x7FFEDD8000ull3760#define BMON1_NIC4_DBG_MAX_OFFSET                  0x10003761#define BMON1_NIC4_DBG_SECTION                     0x10003762#define mmBMON2_NIC4_DBG_BASE                      0x7FFEDD9000ull3763#define BMON2_NIC4_DBG_MAX_OFFSET                  0x10003764#define BMON2_NIC4_DBG_SECTION                     0x10003765#define mmBMON3_NIC4_DBG_BASE                      0x7FFEDDA000ull3766#define BMON3_NIC4_DBG_MAX_OFFSET                  0x10003767#define BMON3_NIC4_DBG_SECTION                     0x10003768#define mmBMON4_NIC4_DBG_BASE                      0x7FFEDDB000ull3769#define BMON4_NIC4_DBG_MAX_OFFSET                  0x10003770#define BMON4_NIC4_DBG_SECTION                     0x60003771#define mmFUNNEL_NIC4_DBG_BASE                     0x7FFEDE1000ull3772#define FUNNEL_NIC4_DBG_MAX_OFFSET                 0x10003773#define FUNNEL_NIC4_DBG_SECTION                    0x21F0003774#define mmTPC0_ROM_TABLE_BASE                      0x7FFF000000ull3775#define TPC0_ROM_TABLE_MAX_OFFSET                  0x10003776#define TPC0_ROM_TABLE_SECTION                     0x10003777#define mmTPC0_EML_SPMU_BASE                       0x7FFF001000ull3778#define TPC0_EML_SPMU_MAX_OFFSET                   0x10003779#define TPC0_EML_SPMU_SECTION                      0x10003780#define mmTPC0_EML_ETF_BASE                        0x7FFF002000ull3781#define TPC0_EML_ETF_MAX_OFFSET                    0x10003782#define TPC0_EML_ETF_SECTION                       0x10003783#define mmTPC0_EML_STM_BASE                        0x7FFF003000ull3784#define TPC0_EML_STM_MAX_OFFSET                    0x10003785#define TPC0_EML_STM_SECTION                       0x20003786#define mmTPC0_EML_CTI_BASE                        0x7FFF005000ull3787#define TPC0_EML_CTI_MAX_OFFSET                    0x10003788#define TPC0_EML_CTI_SECTION                       0x10003789#define mmTPC0_EML_FUNNEL_BASE                     0x7FFF006000ull3790#define TPC0_EML_FUNNEL_MAX_OFFSET                 0x10003791#define TPC0_EML_FUNNEL_SECTION                    0x10003792#define mmTPC0_EML_BUSMON_0_BASE                   0x7FFF007000ull3793#define TPC0_EML_BUSMON_0_MAX_OFFSET               0x10003794#define TPC0_EML_BUSMON_0_SECTION                  0x10003795#define mmTPC0_EML_BUSMON_1_BASE                   0x7FFF008000ull3796#define TPC0_EML_BUSMON_1_MAX_OFFSET               0x10003797#define TPC0_EML_BUSMON_1_SECTION                  0x10003798#define mmTPC0_EML_BUSMON_2_BASE                   0x7FFF009000ull3799#define TPC0_EML_BUSMON_2_MAX_OFFSET               0x10003800#define TPC0_EML_BUSMON_2_SECTION                  0x10003801#define mmTPC0_EML_BUSMON_3_BASE                   0x7FFF00A000ull3802#define TPC0_EML_BUSMON_3_MAX_OFFSET               0x10003803#define TPC0_EML_BUSMON_3_SECTION                  0x360003804#define mmTPC0_EML_CFG_BASE                        0x7FFF040000ull3805#define TPC0_EML_CFG_MAX_OFFSET                    0x33803806#define TPC0_EML_CFG_SECTION                       0x10003807#define mmTPC0_EML_TPC_CFG_BASE                    0x7FFF041000ull3808#define TPC0_EML_TPC_CFG_MAX_OFFSET                0xE4003809#define TPC0_EML_TPC_CFG_SECTION                   0x40003810#define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE    0x7FFF041400ull3811#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003812#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION   0x38003813#define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE    0x7FFF041438ull3814#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003815#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION   0x38003816#define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE    0x7FFF041470ull3817#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003818#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION   0x38003819#define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE    0x7FFF0414A8ull3820#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003821#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION   0x38003822#define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE    0x7FFF0414E0ull3823#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003824#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION   0x38003825#define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE    0x7FFF041518ull3826#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003827#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION   0x38003828#define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE    0x7FFF041550ull3829#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003830#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION   0x38003831#define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE    0x7FFF041588ull3832#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003833#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION   0x38003834#define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE    0x7FFF0415C0ull3835#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003836#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION   0x38003837#define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE    0x7FFF0415F8ull3838#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003839#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION   0x38003840#define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE   0x7FFF041630ull3841#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003842#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION  0x38003843#define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE   0x7FFF041668ull3844#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003845#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION  0x38003846#define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE   0x7FFF0416A0ull3847#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003848#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION  0x38003849#define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE   0x7FFF0416D8ull3850#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003851#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION  0x38003852#define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE   0x7FFF041710ull3853#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003854#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION  0x38003855#define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE   0x7FFF041748ull3856#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x38003857#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION  0x38003858#define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull3859#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x80003860#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x80003861#define mmKERNEL_TPC0_EML_TPC_CFG_BASE             0x7FFF041788ull3862#define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET         0xB8003863#define KERNEL_TPC0_EML_TPC_CFG_SECTION            0x27803864#define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE        0x7FFF041A00ull3865#define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003866#define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION       0x38003867#define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE        0x7FFF041A38ull3868#define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003869#define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION       0x38003870#define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE        0x7FFF041A70ull3871#define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003872#define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION       0x38003873#define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE        0x7FFF041AA8ull3874#define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003875#define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION       0x38003876#define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE        0x7FFF041AE0ull3877#define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003878#define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION       0x38003879#define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE        0x7FFF041B18ull3880#define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003881#define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION       0x38003882#define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE        0x7FFF041B50ull3883#define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003884#define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION       0x38003885#define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE        0x7FFF041B88ull3886#define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003887#define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION       0x38003888#define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE        0x7FFF041BC0ull3889#define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003890#define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION       0x38003891#define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE        0x7FFF041BF8ull3892#define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET    0x38003893#define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION       0x38003894#define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE       0x7FFF041C30ull3895#define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET   0x38003896#define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION      0x38003897#define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE       0x7FFF041C68ull3898#define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET   0x38003899#define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION      0x38003900#define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE       0x7FFF041CA0ull3901#define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET   0x38003902#define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION      0x38003903#define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE       0x7FFF041CD8ull3904#define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET   0x38003905#define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION      0x38003906#define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE       0x7FFF041D10ull3907#define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET   0x38003908#define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION      0x38003909#define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE       0x7FFF041D48ull3910#define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET   0x38003911#define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION      0x38003912#define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE     0x7FFF041D80ull3913#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x80003914#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION    0x80003915#define mmQM_TPC0_EML_TPC_CFG_BASE                 0x7FFF041D88ull3916#define QM_TPC0_EML_TPC_CFG_MAX_OFFSET             0xB8003917#define QM_TPC0_EML_TPC_CFG_SECTION                0x27803918#define mmTPC0_EML_TPC_QM_BASE                     0x7FFF042000ull3919#define TPC0_EML_TPC_QM_MAX_OFFSET                 0xD0403920#define TPC0_EML_TPC_QM_SECTION                    0x1BD0003921#define mmTPC0_EML_CS_BASE                         0x7FFF1FF000ull3922#define TPC0_EML_CS_MAX_OFFSET                     0x10003923#define TPC0_EML_CS_SECTION                        0x10003924#define mmTPC1_ROM_TABLE_BASE                      0x7FFF200000ull3925#define TPC1_ROM_TABLE_MAX_OFFSET                  0x10003926#define TPC1_ROM_TABLE_SECTION                     0x10003927#define mmTPC1_EML_SPMU_BASE                       0x7FFF201000ull3928#define TPC1_EML_SPMU_MAX_OFFSET                   0x10003929#define TPC1_EML_SPMU_SECTION                      0x10003930#define mmTPC1_EML_ETF_BASE                        0x7FFF202000ull3931#define TPC1_EML_ETF_MAX_OFFSET                    0x10003932#define TPC1_EML_ETF_SECTION                       0x10003933#define mmTPC1_EML_STM_BASE                        0x7FFF203000ull3934#define TPC1_EML_STM_MAX_OFFSET                    0x10003935#define TPC1_EML_STM_SECTION                       0x20003936#define mmTPC1_EML_CTI_BASE                        0x7FFF205000ull3937#define TPC1_EML_CTI_MAX_OFFSET                    0x10003938#define TPC1_EML_CTI_SECTION                       0x10003939#define mmTPC1_EML_FUNNEL_BASE                     0x7FFF206000ull3940#define TPC1_EML_FUNNEL_MAX_OFFSET                 0x10003941#define TPC1_EML_FUNNEL_SECTION                    0x10003942#define mmTPC1_EML_BUSMON_0_BASE                   0x7FFF207000ull3943#define TPC1_EML_BUSMON_0_MAX_OFFSET               0x10003944#define TPC1_EML_BUSMON_0_SECTION                  0x10003945#define mmTPC1_EML_BUSMON_1_BASE                   0x7FFF208000ull3946#define TPC1_EML_BUSMON_1_MAX_OFFSET               0x10003947#define TPC1_EML_BUSMON_1_SECTION                  0x10003948#define mmTPC1_EML_BUSMON_2_BASE                   0x7FFF209000ull3949#define TPC1_EML_BUSMON_2_MAX_OFFSET               0x10003950#define TPC1_EML_BUSMON_2_SECTION                  0x10003951#define mmTPC1_EML_BUSMON_3_BASE                   0x7FFF20A000ull3952#define TPC1_EML_BUSMON_3_MAX_OFFSET               0x10003953#define TPC1_EML_BUSMON_3_SECTION                  0x360003954#define mmTPC1_EML_CFG_BASE                        0x7FFF240000ull3955#define TPC1_EML_CFG_MAX_OFFSET                    0x33803956#define TPC1_EML_CFG_SECTION                       0x10003957#define mmTPC1_EML_TPC_CFG_BASE                    0x7FFF241000ull3958#define TPC1_EML_TPC_CFG_MAX_OFFSET                0xE4003959#define TPC1_EML_TPC_CFG_SECTION                   0x40003960#define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE    0x7FFF241400ull3961#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003962#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION   0x38003963#define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE    0x7FFF241438ull3964#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003965#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION   0x38003966#define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE    0x7FFF241470ull3967#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003968#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION   0x38003969#define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE    0x7FFF2414A8ull3970#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003971#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION   0x38003972#define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE    0x7FFF2414E0ull3973#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003974#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION   0x38003975#define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE    0x7FFF241518ull3976#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003977#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION   0x38003978#define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE    0x7FFF241550ull3979#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003980#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION   0x38003981#define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE    0x7FFF241588ull3982#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003983#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION   0x38003984#define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE    0x7FFF2415C0ull3985#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003986#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION   0x38003987#define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE    0x7FFF2415F8ull3988#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003989#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION   0x38003990#define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE   0x7FFF241630ull3991#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003992#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION  0x38003993#define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE   0x7FFF241668ull3994#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003995#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION  0x38003996#define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE   0x7FFF2416A0ull3997#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38003998#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION  0x38003999#define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE   0x7FFF2416D8ull4000#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38004001#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION  0x38004002#define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE   0x7FFF241710ull4003#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38004004#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION  0x38004005#define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE   0x7FFF241748ull4006#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x38004007#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION  0x38004008#define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull4009#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x80004010#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x80004011#define mmKERNEL_TPC1_EML_TPC_CFG_BASE             0x7FFF241788ull4012#define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET         0xB8004013#define KERNEL_TPC1_EML_TPC_CFG_SECTION            0x27804014#define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE        0x7FFF241A00ull4015#define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004016#define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION       0x38004017#define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE        0x7FFF241A38ull4018#define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004019#define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION       0x38004020#define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE        0x7FFF241A70ull4021#define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004022#define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION       0x38004023#define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE        0x7FFF241AA8ull4024#define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004025#define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION       0x38004026#define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE        0x7FFF241AE0ull4027#define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004028#define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION       0x38004029#define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE        0x7FFF241B18ull4030#define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004031#define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION       0x38004032#define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE        0x7FFF241B50ull4033#define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004034#define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION       0x38004035#define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE        0x7FFF241B88ull4036#define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004037#define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION       0x38004038#define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE        0x7FFF241BC0ull4039#define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004040#define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION       0x38004041#define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE        0x7FFF241BF8ull4042#define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET    0x38004043#define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION       0x38004044#define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE       0x7FFF241C30ull4045#define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET   0x38004046#define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION      0x38004047#define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE       0x7FFF241C68ull4048#define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET   0x38004049#define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION      0x38004050#define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE       0x7FFF241CA0ull4051#define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET   0x38004052#define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION      0x38004053#define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE       0x7FFF241CD8ull4054#define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET   0x38004055#define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION      0x38004056#define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE       0x7FFF241D10ull4057#define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET   0x38004058#define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION      0x38004059#define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE       0x7FFF241D48ull4060#define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET   0x38004061#define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION      0x38004062#define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE     0x7FFF241D80ull4063#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x80004064#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION    0x80004065#define mmQM_TPC1_EML_TPC_CFG_BASE                 0x7FFF241D88ull4066#define QM_TPC1_EML_TPC_CFG_MAX_OFFSET             0xB8004067#define QM_TPC1_EML_TPC_CFG_SECTION                0x27804068#define mmTPC1_EML_TPC_QM_BASE                     0x7FFF242000ull4069#define TPC1_EML_TPC_QM_MAX_OFFSET                 0xD0404070#define TPC1_EML_TPC_QM_SECTION                    0x1BD0004071#define mmTPC1_EML_CS_BASE                         0x7FFF3FF000ull4072#define TPC1_EML_CS_MAX_OFFSET                     0x10004073#define TPC1_EML_CS_SECTION                        0x10004074#define mmTPC2_ROM_TABLE_BASE                      0x7FFF400000ull4075#define TPC2_ROM_TABLE_MAX_OFFSET                  0x10004076#define TPC2_ROM_TABLE_SECTION                     0x10004077#define mmTPC2_EML_SPMU_BASE                       0x7FFF401000ull4078#define TPC2_EML_SPMU_MAX_OFFSET                   0x10004079#define TPC2_EML_SPMU_SECTION                      0x10004080#define mmTPC2_EML_ETF_BASE                        0x7FFF402000ull4081#define TPC2_EML_ETF_MAX_OFFSET                    0x10004082#define TPC2_EML_ETF_SECTION                       0x10004083#define mmTPC2_EML_STM_BASE                        0x7FFF403000ull4084#define TPC2_EML_STM_MAX_OFFSET                    0x10004085#define TPC2_EML_STM_SECTION                       0x20004086#define mmTPC2_EML_CTI_BASE                        0x7FFF405000ull4087#define TPC2_EML_CTI_MAX_OFFSET                    0x10004088#define TPC2_EML_CTI_SECTION                       0x10004089#define mmTPC2_EML_FUNNEL_BASE                     0x7FFF406000ull4090#define TPC2_EML_FUNNEL_MAX_OFFSET                 0x10004091#define TPC2_EML_FUNNEL_SECTION                    0x10004092#define mmTPC2_EML_BUSMON_0_BASE                   0x7FFF407000ull4093#define TPC2_EML_BUSMON_0_MAX_OFFSET               0x10004094#define TPC2_EML_BUSMON_0_SECTION                  0x10004095#define mmTPC2_EML_BUSMON_1_BASE                   0x7FFF408000ull4096#define TPC2_EML_BUSMON_1_MAX_OFFSET               0x10004097#define TPC2_EML_BUSMON_1_SECTION                  0x10004098#define mmTPC2_EML_BUSMON_2_BASE                   0x7FFF409000ull4099#define TPC2_EML_BUSMON_2_MAX_OFFSET               0x10004100#define TPC2_EML_BUSMON_2_SECTION                  0x10004101#define mmTPC2_EML_BUSMON_3_BASE                   0x7FFF40A000ull4102#define TPC2_EML_BUSMON_3_MAX_OFFSET               0x10004103#define TPC2_EML_BUSMON_3_SECTION                  0x360004104#define mmTPC2_EML_CFG_BASE                        0x7FFF440000ull4105#define TPC2_EML_CFG_MAX_OFFSET                    0x33804106#define TPC2_EML_CFG_SECTION                       0x10004107#define mmTPC2_EML_TPC_CFG_BASE                    0x7FFF441000ull4108#define TPC2_EML_TPC_CFG_MAX_OFFSET                0xE4004109#define TPC2_EML_TPC_CFG_SECTION                   0x40004110#define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE    0x7FFF441400ull4111#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004112#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION   0x38004113#define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE    0x7FFF441438ull4114#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004115#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION   0x38004116#define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE    0x7FFF441470ull4117#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004118#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION   0x38004119#define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE    0x7FFF4414A8ull4120#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004121#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION   0x38004122#define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE    0x7FFF4414E0ull4123#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004124#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION   0x38004125#define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE    0x7FFF441518ull4126#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004127#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION   0x38004128#define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE    0x7FFF441550ull4129#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004130#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION   0x38004131#define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE    0x7FFF441588ull4132#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004133#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION   0x38004134#define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE    0x7FFF4415C0ull4135#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004136#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION   0x38004137#define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE    0x7FFF4415F8ull4138#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004139#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION   0x38004140#define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE   0x7FFF441630ull4141#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004142#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION  0x38004143#define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE   0x7FFF441668ull4144#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004145#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION  0x38004146#define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE   0x7FFF4416A0ull4147#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004148#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION  0x38004149#define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE   0x7FFF4416D8ull4150#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004151#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION  0x38004152#define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE   0x7FFF441710ull4153#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004154#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION  0x38004155#define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE   0x7FFF441748ull4156#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x38004157#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION  0x38004158#define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull4159#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x80004160#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x80004161#define mmKERNEL_TPC2_EML_TPC_CFG_BASE             0x7FFF441788ull4162#define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET         0xB8004163#define KERNEL_TPC2_EML_TPC_CFG_SECTION            0x27804164#define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE        0x7FFF441A00ull4165#define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004166#define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION       0x38004167#define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE        0x7FFF441A38ull4168#define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004169#define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION       0x38004170#define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE        0x7FFF441A70ull4171#define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004172#define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION       0x38004173#define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE        0x7FFF441AA8ull4174#define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004175#define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION       0x38004176#define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE        0x7FFF441AE0ull4177#define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004178#define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION       0x38004179#define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE        0x7FFF441B18ull4180#define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004181#define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION       0x38004182#define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE        0x7FFF441B50ull4183#define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004184#define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION       0x38004185#define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE        0x7FFF441B88ull4186#define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004187#define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION       0x38004188#define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE        0x7FFF441BC0ull4189#define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004190#define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION       0x38004191#define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE        0x7FFF441BF8ull4192#define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET    0x38004193#define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION       0x38004194#define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE       0x7FFF441C30ull4195#define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET   0x38004196#define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION      0x38004197#define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE       0x7FFF441C68ull4198#define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET   0x38004199#define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION      0x38004200#define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE       0x7FFF441CA0ull4201#define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET   0x38004202#define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION      0x38004203#define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE       0x7FFF441CD8ull4204#define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET   0x38004205#define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION      0x38004206#define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE       0x7FFF441D10ull4207#define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET   0x38004208#define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION      0x38004209#define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE       0x7FFF441D48ull4210#define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET   0x38004211#define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION      0x38004212#define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE     0x7FFF441D80ull4213#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x80004214#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION    0x80004215#define mmQM_TPC2_EML_TPC_CFG_BASE                 0x7FFF441D88ull4216#define QM_TPC2_EML_TPC_CFG_MAX_OFFSET             0xB8004217#define QM_TPC2_EML_TPC_CFG_SECTION                0x27804218#define mmTPC2_EML_TPC_QM_BASE                     0x7FFF442000ull4219#define TPC2_EML_TPC_QM_MAX_OFFSET                 0xD0404220#define TPC2_EML_TPC_QM_SECTION                    0x1BD0004221#define mmTPC2_EML_CS_BASE                         0x7FFF5FF000ull4222#define TPC2_EML_CS_MAX_OFFSET                     0x10004223#define TPC2_EML_CS_SECTION                        0x10004224#define mmTPC3_ROM_TABLE_BASE                      0x7FFF600000ull4225#define TPC3_ROM_TABLE_MAX_OFFSET                  0x10004226#define TPC3_ROM_TABLE_SECTION                     0x10004227#define mmTPC3_EML_SPMU_BASE                       0x7FFF601000ull4228#define TPC3_EML_SPMU_MAX_OFFSET                   0x10004229#define TPC3_EML_SPMU_SECTION                      0x10004230#define mmTPC3_EML_ETF_BASE                        0x7FFF602000ull4231#define TPC3_EML_ETF_MAX_OFFSET                    0x10004232#define TPC3_EML_ETF_SECTION                       0x10004233#define mmTPC3_EML_STM_BASE                        0x7FFF603000ull4234#define TPC3_EML_STM_MAX_OFFSET                    0x10004235#define TPC3_EML_STM_SECTION                       0x20004236#define mmTPC3_EML_CTI_BASE                        0x7FFF605000ull4237#define TPC3_EML_CTI_MAX_OFFSET                    0x10004238#define TPC3_EML_CTI_SECTION                       0x10004239#define mmTPC3_EML_FUNNEL_BASE                     0x7FFF606000ull4240#define TPC3_EML_FUNNEL_MAX_OFFSET                 0x10004241#define TPC3_EML_FUNNEL_SECTION                    0x10004242#define mmTPC3_EML_BUSMON_0_BASE                   0x7FFF607000ull4243#define TPC3_EML_BUSMON_0_MAX_OFFSET               0x10004244#define TPC3_EML_BUSMON_0_SECTION                  0x10004245#define mmTPC3_EML_BUSMON_1_BASE                   0x7FFF608000ull4246#define TPC3_EML_BUSMON_1_MAX_OFFSET               0x10004247#define TPC3_EML_BUSMON_1_SECTION                  0x10004248#define mmTPC3_EML_BUSMON_2_BASE                   0x7FFF609000ull4249#define TPC3_EML_BUSMON_2_MAX_OFFSET               0x10004250#define TPC3_EML_BUSMON_2_SECTION                  0x10004251#define mmTPC3_EML_BUSMON_3_BASE                   0x7FFF60A000ull4252#define TPC3_EML_BUSMON_3_MAX_OFFSET               0x10004253#define TPC3_EML_BUSMON_3_SECTION                  0x360004254#define mmTPC3_EML_CFG_BASE                        0x7FFF640000ull4255#define TPC3_EML_CFG_MAX_OFFSET                    0x33804256#define TPC3_EML_CFG_SECTION                       0x10004257#define mmTPC3_EML_TPC_CFG_BASE                    0x7FFF641000ull4258#define TPC3_EML_TPC_CFG_MAX_OFFSET                0xE4004259#define TPC3_EML_TPC_CFG_SECTION                   0x40004260#define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE    0x7FFF641400ull4261#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004262#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION   0x38004263#define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE    0x7FFF641438ull4264#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004265#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION   0x38004266#define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE    0x7FFF641470ull4267#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004268#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION   0x38004269#define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE    0x7FFF6414A8ull4270#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004271#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION   0x38004272#define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE    0x7FFF6414E0ull4273#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004274#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION   0x38004275#define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE    0x7FFF641518ull4276#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004277#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION   0x38004278#define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE    0x7FFF641550ull4279#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004280#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION   0x38004281#define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE    0x7FFF641588ull4282#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004283#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION   0x38004284#define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE    0x7FFF6415C0ull4285#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004286#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION   0x38004287#define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE    0x7FFF6415F8ull4288#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004289#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION   0x38004290#define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE   0x7FFF641630ull4291#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004292#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION  0x38004293#define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE   0x7FFF641668ull4294#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004295#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION  0x38004296#define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE   0x7FFF6416A0ull4297#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004298#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION  0x38004299#define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE   0x7FFF6416D8ull4300#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004301#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION  0x38004302#define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE   0x7FFF641710ull4303#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004304#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION  0x38004305#define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE   0x7FFF641748ull4306#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x38004307#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION  0x38004308#define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull4309#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x80004310#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x80004311#define mmKERNEL_TPC3_EML_TPC_CFG_BASE             0x7FFF641788ull4312#define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET         0xB8004313#define KERNEL_TPC3_EML_TPC_CFG_SECTION            0x27804314#define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE        0x7FFF641A00ull4315#define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004316#define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION       0x38004317#define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE        0x7FFF641A38ull4318#define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004319#define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION       0x38004320#define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE        0x7FFF641A70ull4321#define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004322#define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION       0x38004323#define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE        0x7FFF641AA8ull4324#define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004325#define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION       0x38004326#define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE        0x7FFF641AE0ull4327#define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004328#define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION       0x38004329#define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE        0x7FFF641B18ull4330#define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004331#define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION       0x38004332#define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE        0x7FFF641B50ull4333#define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004334#define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION       0x38004335#define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE        0x7FFF641B88ull4336#define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004337#define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION       0x38004338#define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE        0x7FFF641BC0ull4339#define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004340#define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION       0x38004341#define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE        0x7FFF641BF8ull4342#define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET    0x38004343#define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION       0x38004344#define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE       0x7FFF641C30ull4345#define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET   0x38004346#define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION      0x38004347#define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE       0x7FFF641C68ull4348#define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET   0x38004349#define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION      0x38004350#define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE       0x7FFF641CA0ull4351#define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET   0x38004352#define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION      0x38004353#define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE       0x7FFF641CD8ull4354#define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET   0x38004355#define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION      0x38004356#define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE       0x7FFF641D10ull4357#define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET   0x38004358#define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION      0x38004359#define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE       0x7FFF641D48ull4360#define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET   0x38004361#define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION      0x38004362#define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE     0x7FFF641D80ull4363#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x80004364#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION    0x80004365#define mmQM_TPC3_EML_TPC_CFG_BASE                 0x7FFF641D88ull4366#define QM_TPC3_EML_TPC_CFG_MAX_OFFSET             0xB8004367#define QM_TPC3_EML_TPC_CFG_SECTION                0x27804368#define mmTPC3_EML_TPC_QM_BASE                     0x7FFF642000ull4369#define TPC3_EML_TPC_QM_MAX_OFFSET                 0xD0404370#define TPC3_EML_TPC_QM_SECTION                    0x1BD0004371#define mmTPC3_EML_CS_BASE                         0x7FFF7FF000ull4372#define TPC3_EML_CS_MAX_OFFSET                     0x10004373#define TPC3_EML_CS_SECTION                        0x10004374#define mmTPC4_ROM_TABLE_BASE                      0x7FFF800000ull4375#define TPC4_ROM_TABLE_MAX_OFFSET                  0x10004376#define TPC4_ROM_TABLE_SECTION                     0x10004377#define mmTPC4_EML_SPMU_BASE                       0x7FFF801000ull4378#define TPC4_EML_SPMU_MAX_OFFSET                   0x10004379#define TPC4_EML_SPMU_SECTION                      0x10004380#define mmTPC4_EML_ETF_BASE                        0x7FFF802000ull4381#define TPC4_EML_ETF_MAX_OFFSET                    0x10004382#define TPC4_EML_ETF_SECTION                       0x10004383#define mmTPC4_EML_STM_BASE                        0x7FFF803000ull4384#define TPC4_EML_STM_MAX_OFFSET                    0x10004385#define TPC4_EML_STM_SECTION                       0x20004386#define mmTPC4_EML_CTI_BASE                        0x7FFF805000ull4387#define TPC4_EML_CTI_MAX_OFFSET                    0x10004388#define TPC4_EML_CTI_SECTION                       0x10004389#define mmTPC4_EML_FUNNEL_BASE                     0x7FFF806000ull4390#define TPC4_EML_FUNNEL_MAX_OFFSET                 0x10004391#define TPC4_EML_FUNNEL_SECTION                    0x10004392#define mmTPC4_EML_BUSMON_0_BASE                   0x7FFF807000ull4393#define TPC4_EML_BUSMON_0_MAX_OFFSET               0x10004394#define TPC4_EML_BUSMON_0_SECTION                  0x10004395#define mmTPC4_EML_BUSMON_1_BASE                   0x7FFF808000ull4396#define TPC4_EML_BUSMON_1_MAX_OFFSET               0x10004397#define TPC4_EML_BUSMON_1_SECTION                  0x10004398#define mmTPC4_EML_BUSMON_2_BASE                   0x7FFF809000ull4399#define TPC4_EML_BUSMON_2_MAX_OFFSET               0x10004400#define TPC4_EML_BUSMON_2_SECTION                  0x10004401#define mmTPC4_EML_BUSMON_3_BASE                   0x7FFF80A000ull4402#define TPC4_EML_BUSMON_3_MAX_OFFSET               0x10004403#define TPC4_EML_BUSMON_3_SECTION                  0x360004404#define mmTPC4_EML_CFG_BASE                        0x7FFF840000ull4405#define TPC4_EML_CFG_MAX_OFFSET                    0x33804406#define TPC4_EML_CFG_SECTION                       0x10004407#define mmTPC4_EML_TPC_CFG_BASE                    0x7FFF841000ull4408#define TPC4_EML_TPC_CFG_MAX_OFFSET                0xE4004409#define TPC4_EML_TPC_CFG_SECTION                   0x40004410#define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE    0x7FFF841400ull4411#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004412#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION   0x38004413#define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE    0x7FFF841438ull4414#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004415#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION   0x38004416#define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE    0x7FFF841470ull4417#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004418#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION   0x38004419#define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE    0x7FFF8414A8ull4420#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004421#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION   0x38004422#define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE    0x7FFF8414E0ull4423#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004424#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION   0x38004425#define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE    0x7FFF841518ull4426#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004427#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION   0x38004428#define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE    0x7FFF841550ull4429#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004430#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION   0x38004431#define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE    0x7FFF841588ull4432#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004433#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION   0x38004434#define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE    0x7FFF8415C0ull4435#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004436#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION   0x38004437#define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE    0x7FFF8415F8ull4438#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004439#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION   0x38004440#define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE   0x7FFF841630ull4441#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004442#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION  0x38004443#define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE   0x7FFF841668ull4444#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004445#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION  0x38004446#define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE   0x7FFF8416A0ull4447#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004448#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION  0x38004449#define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE   0x7FFF8416D8ull4450#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004451#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION  0x38004452#define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE   0x7FFF841710ull4453#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004454#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION  0x38004455#define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE   0x7FFF841748ull4456#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x38004457#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION  0x38004458#define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull4459#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x80004460#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x80004461#define mmKERNEL_TPC4_EML_TPC_CFG_BASE             0x7FFF841788ull4462#define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET         0xB8004463#define KERNEL_TPC4_EML_TPC_CFG_SECTION            0x27804464#define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE        0x7FFF841A00ull4465#define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004466#define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION       0x38004467#define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE        0x7FFF841A38ull4468#define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004469#define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION       0x38004470#define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE        0x7FFF841A70ull4471#define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004472#define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION       0x38004473#define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE        0x7FFF841AA8ull4474#define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004475#define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION       0x38004476#define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE        0x7FFF841AE0ull4477#define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004478#define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION       0x38004479#define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE        0x7FFF841B18ull4480#define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004481#define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION       0x38004482#define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE        0x7FFF841B50ull4483#define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004484#define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION       0x38004485#define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE        0x7FFF841B88ull4486#define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004487#define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION       0x38004488#define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE        0x7FFF841BC0ull4489#define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004490#define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION       0x38004491#define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE        0x7FFF841BF8ull4492#define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET    0x38004493#define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION       0x38004494#define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE       0x7FFF841C30ull4495#define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET   0x38004496#define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION      0x38004497#define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE       0x7FFF841C68ull4498#define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET   0x38004499#define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION      0x38004500#define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE       0x7FFF841CA0ull4501#define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET   0x38004502#define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION      0x38004503#define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE       0x7FFF841CD8ull4504#define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET   0x38004505#define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION      0x38004506#define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE       0x7FFF841D10ull4507#define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET   0x38004508#define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION      0x38004509#define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE       0x7FFF841D48ull4510#define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET   0x38004511#define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION      0x38004512#define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE     0x7FFF841D80ull4513#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x80004514#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION    0x80004515#define mmQM_TPC4_EML_TPC_CFG_BASE                 0x7FFF841D88ull4516#define QM_TPC4_EML_TPC_CFG_MAX_OFFSET             0xB8004517#define QM_TPC4_EML_TPC_CFG_SECTION                0x27804518#define mmTPC4_EML_TPC_QM_BASE                     0x7FFF842000ull4519#define TPC4_EML_TPC_QM_MAX_OFFSET                 0xD0404520#define TPC4_EML_TPC_QM_SECTION                    0x1BD0004521#define mmTPC4_EML_CS_BASE                         0x7FFF9FF000ull4522#define TPC4_EML_CS_MAX_OFFSET                     0x10004523#define TPC4_EML_CS_SECTION                        0x10004524#define mmTPC5_ROM_TABLE_BASE                      0x7FFFA00000ull4525#define TPC5_ROM_TABLE_MAX_OFFSET                  0x10004526#define TPC5_ROM_TABLE_SECTION                     0x10004527#define mmTPC5_EML_SPMU_BASE                       0x7FFFA01000ull4528#define TPC5_EML_SPMU_MAX_OFFSET                   0x10004529#define TPC5_EML_SPMU_SECTION                      0x10004530#define mmTPC5_EML_ETF_BASE                        0x7FFFA02000ull4531#define TPC5_EML_ETF_MAX_OFFSET                    0x10004532#define TPC5_EML_ETF_SECTION                       0x10004533#define mmTPC5_EML_STM_BASE                        0x7FFFA03000ull4534#define TPC5_EML_STM_MAX_OFFSET                    0x10004535#define TPC5_EML_STM_SECTION                       0x20004536#define mmTPC5_EML_CTI_BASE                        0x7FFFA05000ull4537#define TPC5_EML_CTI_MAX_OFFSET                    0x10004538#define TPC5_EML_CTI_SECTION                       0x10004539#define mmTPC5_EML_FUNNEL_BASE                     0x7FFFA06000ull4540#define TPC5_EML_FUNNEL_MAX_OFFSET                 0x10004541#define TPC5_EML_FUNNEL_SECTION                    0x10004542#define mmTPC5_EML_BUSMON_0_BASE                   0x7FFFA07000ull4543#define TPC5_EML_BUSMON_0_MAX_OFFSET               0x10004544#define TPC5_EML_BUSMON_0_SECTION                  0x10004545#define mmTPC5_EML_BUSMON_1_BASE                   0x7FFFA08000ull4546#define TPC5_EML_BUSMON_1_MAX_OFFSET               0x10004547#define TPC5_EML_BUSMON_1_SECTION                  0x10004548#define mmTPC5_EML_BUSMON_2_BASE                   0x7FFFA09000ull4549#define TPC5_EML_BUSMON_2_MAX_OFFSET               0x10004550#define TPC5_EML_BUSMON_2_SECTION                  0x10004551#define mmTPC5_EML_BUSMON_3_BASE                   0x7FFFA0A000ull4552#define TPC5_EML_BUSMON_3_MAX_OFFSET               0x10004553#define TPC5_EML_BUSMON_3_SECTION                  0x360004554#define mmTPC5_EML_CFG_BASE                        0x7FFFA40000ull4555#define TPC5_EML_CFG_MAX_OFFSET                    0x33804556#define TPC5_EML_CFG_SECTION                       0x10004557#define mmTPC5_EML_TPC_CFG_BASE                    0x7FFFA41000ull4558#define TPC5_EML_TPC_CFG_MAX_OFFSET                0xE4004559#define TPC5_EML_TPC_CFG_SECTION                   0x40004560#define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE    0x7FFFA41400ull4561#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004562#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION   0x38004563#define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE    0x7FFFA41438ull4564#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004565#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION   0x38004566#define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE    0x7FFFA41470ull4567#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004568#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION   0x38004569#define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE    0x7FFFA414A8ull4570#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004571#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION   0x38004572#define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE    0x7FFFA414E0ull4573#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004574#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION   0x38004575#define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE    0x7FFFA41518ull4576#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004577#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION   0x38004578#define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE    0x7FFFA41550ull4579#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004580#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION   0x38004581#define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE    0x7FFFA41588ull4582#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004583#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION   0x38004584#define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE    0x7FFFA415C0ull4585#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004586#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION   0x38004587#define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE    0x7FFFA415F8ull4588#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004589#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION   0x38004590#define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE   0x7FFFA41630ull4591#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004592#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION  0x38004593#define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE   0x7FFFA41668ull4594#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004595#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION  0x38004596#define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE   0x7FFFA416A0ull4597#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004598#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION  0x38004599#define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE   0x7FFFA416D8ull4600#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004601#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION  0x38004602#define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE   0x7FFFA41710ull4603#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004604#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION  0x38004605#define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE   0x7FFFA41748ull4606#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x38004607#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION  0x38004608#define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull4609#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x80004610#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x80004611#define mmKERNEL_TPC5_EML_TPC_CFG_BASE             0x7FFFA41788ull4612#define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET         0xB8004613#define KERNEL_TPC5_EML_TPC_CFG_SECTION            0x27804614#define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE        0x7FFFA41A00ull4615#define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004616#define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION       0x38004617#define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE        0x7FFFA41A38ull4618#define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004619#define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION       0x38004620#define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE        0x7FFFA41A70ull4621#define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004622#define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION       0x38004623#define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE        0x7FFFA41AA8ull4624#define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004625#define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION       0x38004626#define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE        0x7FFFA41AE0ull4627#define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004628#define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION       0x38004629#define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE        0x7FFFA41B18ull4630#define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004631#define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION       0x38004632#define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE        0x7FFFA41B50ull4633#define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004634#define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION       0x38004635#define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE        0x7FFFA41B88ull4636#define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004637#define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION       0x38004638#define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE        0x7FFFA41BC0ull4639#define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004640#define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION       0x38004641#define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE        0x7FFFA41BF8ull4642#define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET    0x38004643#define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION       0x38004644#define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE       0x7FFFA41C30ull4645#define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET   0x38004646#define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION      0x38004647#define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE       0x7FFFA41C68ull4648#define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET   0x38004649#define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION      0x38004650#define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE       0x7FFFA41CA0ull4651#define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET   0x38004652#define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION      0x38004653#define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE       0x7FFFA41CD8ull4654#define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET   0x38004655#define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION      0x38004656#define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE       0x7FFFA41D10ull4657#define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET   0x38004658#define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION      0x38004659#define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE       0x7FFFA41D48ull4660#define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET   0x38004661#define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION      0x38004662#define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE     0x7FFFA41D80ull4663#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x80004664#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION    0x80004665#define mmQM_TPC5_EML_TPC_CFG_BASE                 0x7FFFA41D88ull4666#define QM_TPC5_EML_TPC_CFG_MAX_OFFSET             0xB8004667#define QM_TPC5_EML_TPC_CFG_SECTION                0x27804668#define mmTPC5_EML_TPC_QM_BASE                     0x7FFFA42000ull4669#define TPC5_EML_TPC_QM_MAX_OFFSET                 0xD0404670#define TPC5_EML_TPC_QM_SECTION                    0x1BD0004671#define mmTPC5_EML_CS_BASE                         0x7FFFBFF000ull4672#define TPC5_EML_CS_MAX_OFFSET                     0x10004673#define TPC5_EML_CS_SECTION                        0x10004674#define mmTPC6_ROM_TABLE_BASE                      0x7FFFC00000ull4675#define TPC6_ROM_TABLE_MAX_OFFSET                  0x10004676#define TPC6_ROM_TABLE_SECTION                     0x10004677#define mmTPC6_EML_SPMU_BASE                       0x7FFFC01000ull4678#define TPC6_EML_SPMU_MAX_OFFSET                   0x10004679#define TPC6_EML_SPMU_SECTION                      0x10004680#define mmTPC6_EML_ETF_BASE                        0x7FFFC02000ull4681#define TPC6_EML_ETF_MAX_OFFSET                    0x10004682#define TPC6_EML_ETF_SECTION                       0x10004683#define mmTPC6_EML_STM_BASE                        0x7FFFC03000ull4684#define TPC6_EML_STM_MAX_OFFSET                    0x10004685#define TPC6_EML_STM_SECTION                       0x20004686#define mmTPC6_EML_CTI_BASE                        0x7FFFC05000ull4687#define TPC6_EML_CTI_MAX_OFFSET                    0x10004688#define TPC6_EML_CTI_SECTION                       0x10004689#define mmTPC6_EML_FUNNEL_BASE                     0x7FFFC06000ull4690#define TPC6_EML_FUNNEL_MAX_OFFSET                 0x10004691#define TPC6_EML_FUNNEL_SECTION                    0x10004692#define mmTPC6_EML_BUSMON_0_BASE                   0x7FFFC07000ull4693#define TPC6_EML_BUSMON_0_MAX_OFFSET               0x10004694#define TPC6_EML_BUSMON_0_SECTION                  0x10004695#define mmTPC6_EML_BUSMON_1_BASE                   0x7FFFC08000ull4696#define TPC6_EML_BUSMON_1_MAX_OFFSET               0x10004697#define TPC6_EML_BUSMON_1_SECTION                  0x10004698#define mmTPC6_EML_BUSMON_2_BASE                   0x7FFFC09000ull4699#define TPC6_EML_BUSMON_2_MAX_OFFSET               0x10004700#define TPC6_EML_BUSMON_2_SECTION                  0x10004701#define mmTPC6_EML_BUSMON_3_BASE                   0x7FFFC0A000ull4702#define TPC6_EML_BUSMON_3_MAX_OFFSET               0x10004703#define TPC6_EML_BUSMON_3_SECTION                  0x360004704#define mmTPC6_EML_CFG_BASE                        0x7FFFC40000ull4705#define TPC6_EML_CFG_MAX_OFFSET                    0x33804706#define TPC6_EML_CFG_SECTION                       0x10004707#define mmTPC6_EML_TPC_CFG_BASE                    0x7FFFC41000ull4708#define TPC6_EML_TPC_CFG_MAX_OFFSET                0xE4004709#define TPC6_EML_TPC_CFG_SECTION                   0x40004710#define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE    0x7FFFC41400ull4711#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004712#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION   0x38004713#define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE    0x7FFFC41438ull4714#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004715#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION   0x38004716#define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE    0x7FFFC41470ull4717#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004718#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION   0x38004719#define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE    0x7FFFC414A8ull4720#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004721#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION   0x38004722#define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE    0x7FFFC414E0ull4723#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004724#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION   0x38004725#define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE    0x7FFFC41518ull4726#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004727#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION   0x38004728#define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE    0x7FFFC41550ull4729#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004730#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION   0x38004731#define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE    0x7FFFC41588ull4732#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004733#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION   0x38004734#define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE    0x7FFFC415C0ull4735#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004736#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION   0x38004737#define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE    0x7FFFC415F8ull4738#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004739#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION   0x38004740#define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE   0x7FFFC41630ull4741#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004742#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION  0x38004743#define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE   0x7FFFC41668ull4744#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004745#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION  0x38004746#define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE   0x7FFFC416A0ull4747#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004748#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION  0x38004749#define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE   0x7FFFC416D8ull4750#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004751#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION  0x38004752#define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE   0x7FFFC41710ull4753#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004754#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION  0x38004755#define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE   0x7FFFC41748ull4756#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x38004757#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION  0x38004758#define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull4759#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x80004760#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x80004761#define mmKERNEL_TPC6_EML_TPC_CFG_BASE             0x7FFFC41788ull4762#define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET         0xB8004763#define KERNEL_TPC6_EML_TPC_CFG_SECTION            0x27804764#define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE        0x7FFFC41A00ull4765#define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004766#define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION       0x38004767#define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE        0x7FFFC41A38ull4768#define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004769#define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION       0x38004770#define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE        0x7FFFC41A70ull4771#define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004772#define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION       0x38004773#define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE        0x7FFFC41AA8ull4774#define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004775#define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION       0x38004776#define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE        0x7FFFC41AE0ull4777#define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004778#define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION       0x38004779#define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE        0x7FFFC41B18ull4780#define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004781#define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION       0x38004782#define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE        0x7FFFC41B50ull4783#define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004784#define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION       0x38004785#define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE        0x7FFFC41B88ull4786#define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004787#define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION       0x38004788#define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE        0x7FFFC41BC0ull4789#define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004790#define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION       0x38004791#define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE        0x7FFFC41BF8ull4792#define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET    0x38004793#define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION       0x38004794#define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE       0x7FFFC41C30ull4795#define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET   0x38004796#define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION      0x38004797#define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE       0x7FFFC41C68ull4798#define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET   0x38004799#define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION      0x38004800#define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE       0x7FFFC41CA0ull4801#define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET   0x38004802#define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION      0x38004803#define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE       0x7FFFC41CD8ull4804#define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET   0x38004805#define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION      0x38004806#define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE       0x7FFFC41D10ull4807#define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET   0x38004808#define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION      0x38004809#define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE       0x7FFFC41D48ull4810#define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET   0x38004811#define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION      0x38004812#define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE     0x7FFFC41D80ull4813#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x80004814#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION    0x80004815#define mmQM_TPC6_EML_TPC_CFG_BASE                 0x7FFFC41D88ull4816#define QM_TPC6_EML_TPC_CFG_MAX_OFFSET             0xB8004817#define QM_TPC6_EML_TPC_CFG_SECTION                0x27804818#define mmTPC6_EML_TPC_QM_BASE                     0x7FFFC42000ull4819#define TPC6_EML_TPC_QM_MAX_OFFSET                 0xD0404820#define TPC6_EML_TPC_QM_SECTION                    0x1BD0004821#define mmTPC6_EML_CS_BASE                         0x7FFFDFF000ull4822#define TPC6_EML_CS_MAX_OFFSET                     0x10004823#define TPC6_EML_CS_SECTION                        0x10004824#define mmTPC7_ROM_TABLE_BASE                      0x7FFFE00000ull4825#define TPC7_ROM_TABLE_MAX_OFFSET                  0x10004826#define TPC7_ROM_TABLE_SECTION                     0x10004827#define mmTPC7_EML_SPMU_BASE                       0x7FFFE01000ull4828#define TPC7_EML_SPMU_MAX_OFFSET                   0x10004829#define TPC7_EML_SPMU_SECTION                      0x10004830#define mmTPC7_EML_ETF_BASE                        0x7FFFE02000ull4831#define TPC7_EML_ETF_MAX_OFFSET                    0x10004832#define TPC7_EML_ETF_SECTION                       0x10004833#define mmTPC7_EML_STM_BASE                        0x7FFFE03000ull4834#define TPC7_EML_STM_MAX_OFFSET                    0x10004835#define TPC7_EML_STM_SECTION                       0x20004836#define mmTPC7_EML_CTI_BASE                        0x7FFFE05000ull4837#define TPC7_EML_CTI_MAX_OFFSET                    0x10004838#define TPC7_EML_CTI_SECTION                       0x10004839#define mmTPC7_EML_FUNNEL_BASE                     0x7FFFE06000ull4840#define TPC7_EML_FUNNEL_MAX_OFFSET                 0x10004841#define TPC7_EML_FUNNEL_SECTION                    0x10004842#define mmTPC7_EML_BUSMON_0_BASE                   0x7FFFE07000ull4843#define TPC7_EML_BUSMON_0_MAX_OFFSET               0x10004844#define TPC7_EML_BUSMON_0_SECTION                  0x10004845#define mmTPC7_EML_BUSMON_1_BASE                   0x7FFFE08000ull4846#define TPC7_EML_BUSMON_1_MAX_OFFSET               0x10004847#define TPC7_EML_BUSMON_1_SECTION                  0x10004848#define mmTPC7_EML_BUSMON_2_BASE                   0x7FFFE09000ull4849#define TPC7_EML_BUSMON_2_MAX_OFFSET               0x10004850#define TPC7_EML_BUSMON_2_SECTION                  0x10004851#define mmTPC7_EML_BUSMON_3_BASE                   0x7FFFE0A000ull4852#define TPC7_EML_BUSMON_3_MAX_OFFSET               0x10004853#define TPC7_EML_BUSMON_3_SECTION                  0x360004854#define mmTPC7_EML_CFG_BASE                        0x7FFFE40000ull4855#define TPC7_EML_CFG_MAX_OFFSET                    0x33804856#define TPC7_EML_CFG_SECTION                       0x10004857#define mmTPC7_EML_TPC_CFG_BASE                    0x7FFFE41000ull4858#define TPC7_EML_TPC_CFG_MAX_OFFSET                0xE4004859#define TPC7_EML_TPC_CFG_SECTION                   0x40004860#define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE    0x7FFFE41400ull4861#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004862#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION   0x38004863#define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE    0x7FFFE41438ull4864#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004865#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION   0x38004866#define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE    0x7FFFE41470ull4867#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004868#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION   0x38004869#define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE    0x7FFFE414A8ull4870#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004871#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION   0x38004872#define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE    0x7FFFE414E0ull4873#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004874#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION   0x38004875#define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE    0x7FFFE41518ull4876#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004877#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION   0x38004878#define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE    0x7FFFE41550ull4879#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004880#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION   0x38004881#define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE    0x7FFFE41588ull4882#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004883#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION   0x38004884#define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE    0x7FFFE415C0ull4885#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004886#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION   0x38004887#define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE    0x7FFFE415F8ull4888#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004889#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION   0x38004890#define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE   0x7FFFE41630ull4891#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004892#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION  0x38004893#define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE   0x7FFFE41668ull4894#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004895#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION  0x38004896#define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE   0x7FFFE416A0ull4897#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004898#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION  0x38004899#define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE   0x7FFFE416D8ull4900#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004901#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION  0x38004902#define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE   0x7FFFE41710ull4903#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004904#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION  0x38004905#define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE   0x7FFFE41748ull4906#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x38004907#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION  0x38004908#define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull4909#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x80004910#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x80004911#define mmKERNEL_TPC7_EML_TPC_CFG_BASE             0x7FFFE41788ull4912#define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET         0xB8004913#define KERNEL_TPC7_EML_TPC_CFG_SECTION            0x27804914#define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE        0x7FFFE41A00ull4915#define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004916#define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION       0x38004917#define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE        0x7FFFE41A38ull4918#define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004919#define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION       0x38004920#define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE        0x7FFFE41A70ull4921#define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004922#define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION       0x38004923#define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE        0x7FFFE41AA8ull4924#define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004925#define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION       0x38004926#define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE        0x7FFFE41AE0ull4927#define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004928#define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION       0x38004929#define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE        0x7FFFE41B18ull4930#define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004931#define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION       0x38004932#define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE        0x7FFFE41B50ull4933#define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004934#define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION       0x38004935#define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE        0x7FFFE41B88ull4936#define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004937#define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION       0x38004938#define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE        0x7FFFE41BC0ull4939#define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004940#define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION       0x38004941#define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE        0x7FFFE41BF8ull4942#define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET    0x38004943#define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION       0x38004944#define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE       0x7FFFE41C30ull4945#define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET   0x38004946#define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION      0x38004947#define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE       0x7FFFE41C68ull4948#define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET   0x38004949#define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION      0x38004950#define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE       0x7FFFE41CA0ull4951#define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET   0x38004952#define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION      0x38004953#define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE       0x7FFFE41CD8ull4954#define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET   0x38004955#define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION      0x38004956#define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE       0x7FFFE41D10ull4957#define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET   0x38004958#define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION      0x38004959#define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE       0x7FFFE41D48ull4960#define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET   0x38004961#define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION      0x38004962#define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE     0x7FFFE41D80ull4963#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x80004964#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION    0x80004965#define mmQM_TPC7_EML_TPC_CFG_BASE                 0x7FFFE41D88ull4966#define QM_TPC7_EML_TPC_CFG_MAX_OFFSET             0xB8004967#define QM_TPC7_EML_TPC_CFG_SECTION                0x27804968#define mmTPC7_EML_TPC_QM_BASE                     0x7FFFE42000ull4969#define TPC7_EML_TPC_QM_MAX_OFFSET                 0xD0404970#define TPC7_EML_TPC_QM_SECTION                    0x1BD0004971#define mmTPC7_EML_CS_BASE                         0x7FFFFFF000ull4972#define TPC7_EML_CS_MAX_OFFSET                     0x10004973 4974#endif /* GAUDI_BLOCKS_H_ */4975