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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2020 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8#ifndef ASIC_REG_GAUDI_REGS_H_9#define ASIC_REG_GAUDI_REGS_H_10 11#include "gaudi_blocks.h"12#include "psoc_global_conf_regs.h"13#include "psoc_timestamp_regs.h"14#include "cpu_if_regs.h"15#include "mmu_up_regs.h"16#include "stlb_regs.h"17#include "dma0_qm_regs.h"18#include "dma1_qm_regs.h"19#include "dma2_qm_regs.h"20#include "dma3_qm_regs.h"21#include "dma4_qm_regs.h"22#include "dma5_qm_regs.h"23#include "dma6_qm_regs.h"24#include "dma7_qm_regs.h"25#include "dma0_core_regs.h"26#include "dma1_core_regs.h"27#include "dma2_core_regs.h"28#include "dma3_core_regs.h"29#include "dma4_core_regs.h"30#include "dma5_core_regs.h"31#include "dma6_core_regs.h"32#include "dma7_core_regs.h"33#include "mme0_ctrl_regs.h"34#include "mme1_ctrl_regs.h"35#include "mme2_ctrl_regs.h"36#include "mme3_ctrl_regs.h"37#include "mme0_qm_regs.h"38#include "mme2_qm_regs.h"39#include "tpc0_cfg_regs.h"40#include "tpc1_cfg_regs.h"41#include "tpc2_cfg_regs.h"42#include "tpc3_cfg_regs.h"43#include "tpc4_cfg_regs.h"44#include "tpc5_cfg_regs.h"45#include "tpc6_cfg_regs.h"46#include "tpc7_cfg_regs.h"47#include "tpc0_qm_regs.h"48#include "tpc1_qm_regs.h"49#include "tpc2_qm_regs.h"50#include "tpc3_qm_regs.h"51#include "tpc4_qm_regs.h"52#include "tpc5_qm_regs.h"53#include "tpc6_qm_regs.h"54#include "tpc7_qm_regs.h"55#include "dma_if_e_n_down_ch0_regs.h"56#include "dma_if_e_n_down_ch1_regs.h"57#include "dma_if_e_s_down_ch0_regs.h"58#include "dma_if_e_s_down_ch1_regs.h"59#include "dma_if_w_n_down_ch0_regs.h"60#include "dma_if_w_n_down_ch1_regs.h"61#include "dma_if_w_s_down_ch0_regs.h"62#include "dma_if_w_s_down_ch1_regs.h"63#include "dma_if_e_n_regs.h"64#include "dma_if_e_s_regs.h"65#include "dma_if_w_n_regs.h"66#include "dma_if_w_s_regs.h"67#include "nif_rtr_ctrl_0_regs.h"68#include "nif_rtr_ctrl_1_regs.h"69#include "nif_rtr_ctrl_2_regs.h"70#include "nif_rtr_ctrl_3_regs.h"71#include "nif_rtr_ctrl_4_regs.h"72#include "nif_rtr_ctrl_5_regs.h"73#include "nif_rtr_ctrl_6_regs.h"74#include "nif_rtr_ctrl_7_regs.h"75#include "sif_rtr_ctrl_0_regs.h"76#include "sif_rtr_ctrl_1_regs.h"77#include "sif_rtr_ctrl_2_regs.h"78#include "sif_rtr_ctrl_3_regs.h"79#include "sif_rtr_ctrl_4_regs.h"80#include "sif_rtr_ctrl_5_regs.h"81#include "sif_rtr_ctrl_6_regs.h"82#include "sif_rtr_ctrl_7_regs.h"83#include "psoc_etr_regs.h"84#include "psoc_cpu_pll_regs.h"85 86#include "dma0_qm_masks.h"87#include "mme0_qm_masks.h"88#include "tpc0_qm_masks.h"89#include "dma0_core_masks.h"90#include "tpc0_cfg_masks.h"91#include "psoc_global_conf_masks.h"92 93#include "nic0_qm0_regs.h"94#include "nic1_qm0_regs.h"95#include "nic2_qm0_regs.h"96#include "nic3_qm0_regs.h"97#include "nic4_qm0_regs.h"98#include "nic0_qm1_regs.h"99#include "nic1_qm1_regs.h"100#include "nic2_qm1_regs.h"101#include "nic3_qm1_regs.h"102#include "nic4_qm1_regs.h"103 104#include "nic0_qm0_masks.h"105 106#define GAUDI_ECC_MEM_SEL_OFFSET 0xF18107#define GAUDI_ECC_ADDRESS_OFFSET 0xF1C108#define GAUDI_ECC_SYNDROME_OFFSET 0xF20109#define GAUDI_ECC_MEM_INFO_CLR_OFFSET 0xF28110#define GAUDI_ECC_MEM_INFO_CLR_SERR_MASK BIT(8)111#define GAUDI_ECC_MEM_INFO_CLR_DERR_MASK BIT(9)112#define GAUDI_ECC_SERR0_OFFSET 0xF30113#define GAUDI_ECC_DERR0_OFFSET 0xF40114 115#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x492000116#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x494000117#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x494800118#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x495000119#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 0x495800120#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x496000121#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4B2000122#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x4B6000123#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4D2000124#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4D6000125#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4F2000126#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4F2004127#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4F3FFC128#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4F4000129#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x4F4800130#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x4F5000131#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0 0x4F5800132#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4F6000133#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 0x4F67FC134 135#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x300400136#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x310400137#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x320400138#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x330400139#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x340400140#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x350400141#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x360400142#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x370400143 144#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x300490145#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x310490146#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x320490147#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x330490148#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x340490149#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x350490150#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x360490151#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x370490152 153#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x300410154#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x310410155#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x320410156#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x330410157#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x340410158#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x350410159#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x360410160#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x370410161 162#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x300450163#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x310450164#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x320450165#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x330450166#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x340450167#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x350450168#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x360450169#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x370450170 171#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3004A0172#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3104A0173#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3204A0174#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3304A0175#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3404A0176#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3504A0177#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3604A0178#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3704A0179 180#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3004E0181#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3104E0182#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3204E0183#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3304E0184#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3404E0185#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3504E0186#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3604E0187#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3704E0188 189#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x380400190#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x390400191#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x3A0400192#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x3B0400193#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x3C0400194#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x3D0400195#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x3E0400196#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x3F0400197 198#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x380490199#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x390490200#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x3A0490201#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x3B0490202#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x3C0490203#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x3D0490204#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x3E0490205#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x3F0490206 207#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x380410208#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x390410209#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x3A0410210#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x3B0410211#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x3C0410212#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x3D0410213#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x3E0410214#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x3F0410215 216#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x380450217#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x390450218#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x3A0450219#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x3B0450220#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x3C0450221#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x3D0450222#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x3E0450223#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x3F0450224 225#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3804A0226#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3904A0227#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3A04A0228#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3B04A0229#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3C04A0230#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3D04A0231#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3E04A0232#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3F04A0233 234#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3804E0235#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3904E0236#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3A04E0237#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3B04E0238#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3C04E0239#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3D04E0240#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3E04E0241#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3F04E0242 243#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0 0x489030244#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1 0x489034245 246#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0 0x4A9030247#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1 0x4A9034248 249#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0 0x4C9030250#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1 0x4C9034251 252#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0 0x4E9030253#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1 0x4E9034254 255#define mmMME1_QM_GLBL_CFG0 0xE8000256#define mmMME1_QM_GLBL_STS0 0xE8038257 258#define mmMME0_SBAB_SB_STALL 0x4002C259#define mmMME0_SBAB_ARUSER0 0x40034260#define mmMME0_SBAB_ARUSER1 0x40038261#define mmMME0_SBAB_PROT 0x40050262 263#define mmMME1_SBAB_SB_STALL 0xC002C264#define mmMME1_SBAB_ARUSER0 0xC0034265#define mmMME1_SBAB_ARUSER1 0xC0038266#define mmMME1_SBAB_PROT 0xC0050267 268#define mmMME2_SBAB_SB_STALL 0x14002C269#define mmMME2_SBAB_ARUSER0 0x140034270#define mmMME2_SBAB_ARUSER1 0x140038271#define mmMME2_SBAB_PROT 0x140050272 273#define mmMME3_SBAB_SB_STALL 0x1C002C274#define mmMME3_SBAB_ARUSER0 0x1C0034275#define mmMME3_SBAB_ARUSER1 0x1C0038276#define mmMME3_SBAB_PROT 0x1C0050277 278#define mmMME0_ACC_ACC_STALL 0x20028279#define mmMME0_ACC_WBC 0x20038280#define mmMME0_ACC_PROT 0x20050281 282#define mmMME1_ACC_ACC_STALL 0xA0028283#define mmMME1_ACC_WBC 0xA0038284#define mmMME1_ACC_PROT 0xA0050285 286#define mmMME2_ACC_ACC_STALL 0x120028287#define mmMME2_ACC_WBC 0x120038288#define mmMME2_ACC_PROT 0x120050289 290#define mmMME3_ACC_ACC_STALL 0x1A0028291#define mmMME3_ACC_WBC 0x1A0038292#define mmMME3_ACC_PROT 0x1A0050293 294#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040295 296#define mmPSOC_EFUSE_READ 0xC4A000297#define mmPSOC_EFUSE_DATA_0 0xC4A080298 299#define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20300#define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48301#define mmPCIE_WRAP_HBW_DRAIN_CFG 0xC01D54302#define mmPCIE_WRAP_LBW_DRAIN_CFG 0xC01D5C303 304#define mmPCIE_MSI_INTR_0 0xC13000305 306#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000307 308#define mmPCIE_AUX_FLR_CTRL 0xC07394309#define mmPCIE_AUX_DBI 0xC07490310 311#define mmPCIE_CORE_MSI_REQ 0xC04100312 313#define mmPSOC_PCI_PLL_NR 0xC72100314#define mmSRAM_W_PLL_NR 0x4C8100315#define mmPSOC_HBM_PLL_NR 0xC74100316#define mmNIC0_PLL_NR 0xCF9100317#define mmDMA_W_PLL_NR 0x487100318#define mmMESH_W_PLL_NR 0x4C7100319#define mmPSOC_MME_PLL_NR 0xC71100320#define mmPSOC_TPC_PLL_NR 0xC73100321#define mmIF_W_PLL_NR 0x488100322 323#define mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL 0xC01208324 325#endif /* ASIC_REG_GAUDI_REGS_H_ */326