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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MME0_QM_REGS_H_14#define ASIC_REG_MME0_QM_REGS_H_15 16/*17 *****************************************18 * MME0_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmMME0_QM_GLBL_CFG0 0x6800023 24#define mmMME0_QM_GLBL_CFG1 0x6800425 26#define mmMME0_QM_GLBL_PROT 0x6800827 28#define mmMME0_QM_GLBL_ERR_CFG 0x6800C29 30#define mmMME0_QM_GLBL_SECURE_PROPS_0 0x6801031 32#define mmMME0_QM_GLBL_SECURE_PROPS_1 0x6801433 34#define mmMME0_QM_GLBL_SECURE_PROPS_2 0x6801835 36#define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C37 38#define mmMME0_QM_GLBL_SECURE_PROPS_4 0x6802039 40#define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x6802441 42#define mmMME0_QM_GLBL_NON_SECURE_PROPS_1 0x6802843 44#define mmMME0_QM_GLBL_NON_SECURE_PROPS_2 0x6802C45 46#define mmMME0_QM_GLBL_NON_SECURE_PROPS_3 0x6803047 48#define mmMME0_QM_GLBL_NON_SECURE_PROPS_4 0x6803449 50#define mmMME0_QM_GLBL_STS0 0x6803851 52#define mmMME0_QM_GLBL_STS1_0 0x6804053 54#define mmMME0_QM_GLBL_STS1_1 0x6804455 56#define mmMME0_QM_GLBL_STS1_2 0x6804857 58#define mmMME0_QM_GLBL_STS1_3 0x6804C59 60#define mmMME0_QM_GLBL_STS1_4 0x6805061 62#define mmMME0_QM_GLBL_MSG_EN_0 0x6805463 64#define mmMME0_QM_GLBL_MSG_EN_1 0x6805865 66#define mmMME0_QM_GLBL_MSG_EN_2 0x6805C67 68#define mmMME0_QM_GLBL_MSG_EN_3 0x6806069 70#define mmMME0_QM_GLBL_MSG_EN_4 0x6806871 72#define mmMME0_QM_PQ_BASE_LO_0 0x6807073 74#define mmMME0_QM_PQ_BASE_LO_1 0x6807475 76#define mmMME0_QM_PQ_BASE_LO_2 0x6807877 78#define mmMME0_QM_PQ_BASE_LO_3 0x6807C79 80#define mmMME0_QM_PQ_BASE_HI_0 0x6808081 82#define mmMME0_QM_PQ_BASE_HI_1 0x6808483 84#define mmMME0_QM_PQ_BASE_HI_2 0x6808885 86#define mmMME0_QM_PQ_BASE_HI_3 0x6808C87 88#define mmMME0_QM_PQ_SIZE_0 0x6809089 90#define mmMME0_QM_PQ_SIZE_1 0x6809491 92#define mmMME0_QM_PQ_SIZE_2 0x6809893 94#define mmMME0_QM_PQ_SIZE_3 0x6809C95 96#define mmMME0_QM_PQ_PI_0 0x680A097 98#define mmMME0_QM_PQ_PI_1 0x680A499 100#define mmMME0_QM_PQ_PI_2 0x680A8101 102#define mmMME0_QM_PQ_PI_3 0x680AC103 104#define mmMME0_QM_PQ_CI_0 0x680B0105 106#define mmMME0_QM_PQ_CI_1 0x680B4107 108#define mmMME0_QM_PQ_CI_2 0x680B8109 110#define mmMME0_QM_PQ_CI_3 0x680BC111 112#define mmMME0_QM_PQ_CFG0_0 0x680C0113 114#define mmMME0_QM_PQ_CFG0_1 0x680C4115 116#define mmMME0_QM_PQ_CFG0_2 0x680C8117 118#define mmMME0_QM_PQ_CFG0_3 0x680CC119 120#define mmMME0_QM_PQ_CFG1_0 0x680D0121 122#define mmMME0_QM_PQ_CFG1_1 0x680D4123 124#define mmMME0_QM_PQ_CFG1_2 0x680D8125 126#define mmMME0_QM_PQ_CFG1_3 0x680DC127 128#define mmMME0_QM_PQ_ARUSER_31_11_0 0x680E0129 130#define mmMME0_QM_PQ_ARUSER_31_11_1 0x680E4131 132#define mmMME0_QM_PQ_ARUSER_31_11_2 0x680E8133 134#define mmMME0_QM_PQ_ARUSER_31_11_3 0x680EC135 136#define mmMME0_QM_PQ_STS0_0 0x680F0137 138#define mmMME0_QM_PQ_STS0_1 0x680F4139 140#define mmMME0_QM_PQ_STS0_2 0x680F8141 142#define mmMME0_QM_PQ_STS0_3 0x680FC143 144#define mmMME0_QM_PQ_STS1_0 0x68100145 146#define mmMME0_QM_PQ_STS1_1 0x68104147 148#define mmMME0_QM_PQ_STS1_2 0x68108149 150#define mmMME0_QM_PQ_STS1_3 0x6810C151 152#define mmMME0_QM_CQ_CFG0_0 0x68110153 154#define mmMME0_QM_CQ_CFG0_1 0x68114155 156#define mmMME0_QM_CQ_CFG0_2 0x68118157 158#define mmMME0_QM_CQ_CFG0_3 0x6811C159 160#define mmMME0_QM_CQ_CFG0_4 0x68120161 162#define mmMME0_QM_CQ_CFG1_0 0x68124163 164#define mmMME0_QM_CQ_CFG1_1 0x68128165 166#define mmMME0_QM_CQ_CFG1_2 0x6812C167 168#define mmMME0_QM_CQ_CFG1_3 0x68130169 170#define mmMME0_QM_CQ_CFG1_4 0x68134171 172#define mmMME0_QM_CQ_ARUSER_31_11_0 0x68138173 174#define mmMME0_QM_CQ_ARUSER_31_11_1 0x6813C175 176#define mmMME0_QM_CQ_ARUSER_31_11_2 0x68140177 178#define mmMME0_QM_CQ_ARUSER_31_11_3 0x68144179 180#define mmMME0_QM_CQ_ARUSER_31_11_4 0x68148181 182#define mmMME0_QM_CQ_STS0_0 0x6814C183 184#define mmMME0_QM_CQ_STS0_1 0x68150185 186#define mmMME0_QM_CQ_STS0_2 0x68154187 188#define mmMME0_QM_CQ_STS0_3 0x68158189 190#define mmMME0_QM_CQ_STS0_4 0x6815C191 192#define mmMME0_QM_CQ_STS1_0 0x68160193 194#define mmMME0_QM_CQ_STS1_1 0x68164195 196#define mmMME0_QM_CQ_STS1_2 0x68168197 198#define mmMME0_QM_CQ_STS1_3 0x6816C199 200#define mmMME0_QM_CQ_STS1_4 0x68170201 202#define mmMME0_QM_CQ_PTR_LO_0 0x68174203 204#define mmMME0_QM_CQ_PTR_HI_0 0x68178205 206#define mmMME0_QM_CQ_TSIZE_0 0x6817C207 208#define mmMME0_QM_CQ_CTL_0 0x68180209 210#define mmMME0_QM_CQ_PTR_LO_1 0x68184211 212#define mmMME0_QM_CQ_PTR_HI_1 0x68188213 214#define mmMME0_QM_CQ_TSIZE_1 0x6818C215 216#define mmMME0_QM_CQ_CTL_1 0x68190217 218#define mmMME0_QM_CQ_PTR_LO_2 0x68194219 220#define mmMME0_QM_CQ_PTR_HI_2 0x68198221 222#define mmMME0_QM_CQ_TSIZE_2 0x6819C223 224#define mmMME0_QM_CQ_CTL_2 0x681A0225 226#define mmMME0_QM_CQ_PTR_LO_3 0x681A4227 228#define mmMME0_QM_CQ_PTR_HI_3 0x681A8229 230#define mmMME0_QM_CQ_TSIZE_3 0x681AC231 232#define mmMME0_QM_CQ_CTL_3 0x681B0233 234#define mmMME0_QM_CQ_PTR_LO_4 0x681B4235 236#define mmMME0_QM_CQ_PTR_HI_4 0x681B8237 238#define mmMME0_QM_CQ_TSIZE_4 0x681BC239 240#define mmMME0_QM_CQ_CTL_4 0x681C0241 242#define mmMME0_QM_CQ_PTR_LO_STS_0 0x681C4243 244#define mmMME0_QM_CQ_PTR_LO_STS_1 0x681C8245 246#define mmMME0_QM_CQ_PTR_LO_STS_2 0x681CC247 248#define mmMME0_QM_CQ_PTR_LO_STS_3 0x681D0249 250#define mmMME0_QM_CQ_PTR_LO_STS_4 0x681D4251 252#define mmMME0_QM_CQ_PTR_HI_STS_0 0x681D8253 254#define mmMME0_QM_CQ_PTR_HI_STS_1 0x681DC255 256#define mmMME0_QM_CQ_PTR_HI_STS_2 0x681E0257 258#define mmMME0_QM_CQ_PTR_HI_STS_3 0x681E4259 260#define mmMME0_QM_CQ_PTR_HI_STS_4 0x681E8261 262#define mmMME0_QM_CQ_TSIZE_STS_0 0x681EC263 264#define mmMME0_QM_CQ_TSIZE_STS_1 0x681F0265 266#define mmMME0_QM_CQ_TSIZE_STS_2 0x681F4267 268#define mmMME0_QM_CQ_TSIZE_STS_3 0x681F8269 270#define mmMME0_QM_CQ_TSIZE_STS_4 0x681FC271 272#define mmMME0_QM_CQ_CTL_STS_0 0x68200273 274#define mmMME0_QM_CQ_CTL_STS_1 0x68204275 276#define mmMME0_QM_CQ_CTL_STS_2 0x68208277 278#define mmMME0_QM_CQ_CTL_STS_3 0x6820C279 280#define mmMME0_QM_CQ_CTL_STS_4 0x68210281 282#define mmMME0_QM_CQ_IFIFO_CNT_0 0x68214283 284#define mmMME0_QM_CQ_IFIFO_CNT_1 0x68218285 286#define mmMME0_QM_CQ_IFIFO_CNT_2 0x6821C287 288#define mmMME0_QM_CQ_IFIFO_CNT_3 0x68220289 290#define mmMME0_QM_CQ_IFIFO_CNT_4 0x68224291 292#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 0x68228293 294#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 0x6822C295 296#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 0x68230297 298#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 0x68234299 300#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 0x68238301 302#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 0x6823C303 304#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 0x68240305 306#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 0x68244307 308#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 0x68248309 310#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 0x6824C311 312#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 0x68250313 314#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 0x68254315 316#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 0x68258317 318#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 0x6825C319 320#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 0x68260321 322#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 0x68264323 324#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 0x68268325 326#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 0x6826C327 328#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 0x68270329 330#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 0x68274331 332#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 0x68278333 334#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 0x6827C335 336#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 0x68280337 338#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 0x68284339 340#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 0x68288341 342#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 0x6828C343 344#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 0x68290345 346#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 0x68294347 348#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 0x68298349 350#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 0x6829C351 352#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 0x682A0353 354#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 0x682A4355 356#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 0x682A8357 358#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 0x682AC359 360#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 0x682B0361 362#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 0x682B4363 364#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 0x682B8365 366#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 0x682BC367 368#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 0x682C0369 370#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 0x682C4371 372#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 0x682C8373 374#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 0x682CC375 376#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 0x682D0377 378#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 0x682D4379 380#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 0x682D8381 382#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x682E0383 384#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x682E4385 386#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x682E8387 388#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x682EC389 390#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x682F0391 392#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x682F4393 394#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x682F8395 396#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x682FC397 398#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x68300399 400#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x68304401 402#define mmMME0_QM_CP_FENCE0_RDATA_0 0x68308403 404#define mmMME0_QM_CP_FENCE0_RDATA_1 0x6830C405 406#define mmMME0_QM_CP_FENCE0_RDATA_2 0x68310407 408#define mmMME0_QM_CP_FENCE0_RDATA_3 0x68314409 410#define mmMME0_QM_CP_FENCE0_RDATA_4 0x68318411 412#define mmMME0_QM_CP_FENCE1_RDATA_0 0x6831C413 414#define mmMME0_QM_CP_FENCE1_RDATA_1 0x68320415 416#define mmMME0_QM_CP_FENCE1_RDATA_2 0x68324417 418#define mmMME0_QM_CP_FENCE1_RDATA_3 0x68328419 420#define mmMME0_QM_CP_FENCE1_RDATA_4 0x6832C421 422#define mmMME0_QM_CP_FENCE2_RDATA_0 0x68330423 424#define mmMME0_QM_CP_FENCE2_RDATA_1 0x68334425 426#define mmMME0_QM_CP_FENCE2_RDATA_2 0x68338427 428#define mmMME0_QM_CP_FENCE2_RDATA_3 0x6833C429 430#define mmMME0_QM_CP_FENCE2_RDATA_4 0x68340431 432#define mmMME0_QM_CP_FENCE3_RDATA_0 0x68344433 434#define mmMME0_QM_CP_FENCE3_RDATA_1 0x68348435 436#define mmMME0_QM_CP_FENCE3_RDATA_2 0x6834C437 438#define mmMME0_QM_CP_FENCE3_RDATA_3 0x68350439 440#define mmMME0_QM_CP_FENCE3_RDATA_4 0x68354441 442#define mmMME0_QM_CP_FENCE0_CNT_0 0x68358443 444#define mmMME0_QM_CP_FENCE0_CNT_1 0x6835C445 446#define mmMME0_QM_CP_FENCE0_CNT_2 0x68360447 448#define mmMME0_QM_CP_FENCE0_CNT_3 0x68364449 450#define mmMME0_QM_CP_FENCE0_CNT_4 0x68368451 452#define mmMME0_QM_CP_FENCE1_CNT_0 0x6836C453 454#define mmMME0_QM_CP_FENCE1_CNT_1 0x68370455 456#define mmMME0_QM_CP_FENCE1_CNT_2 0x68374457 458#define mmMME0_QM_CP_FENCE1_CNT_3 0x68378459 460#define mmMME0_QM_CP_FENCE1_CNT_4 0x6837C461 462#define mmMME0_QM_CP_FENCE2_CNT_0 0x68380463 464#define mmMME0_QM_CP_FENCE2_CNT_1 0x68384465 466#define mmMME0_QM_CP_FENCE2_CNT_2 0x68388467 468#define mmMME0_QM_CP_FENCE2_CNT_3 0x6838C469 470#define mmMME0_QM_CP_FENCE2_CNT_4 0x68390471 472#define mmMME0_QM_CP_FENCE3_CNT_0 0x68394473 474#define mmMME0_QM_CP_FENCE3_CNT_1 0x68398475 476#define mmMME0_QM_CP_FENCE3_CNT_2 0x6839C477 478#define mmMME0_QM_CP_FENCE3_CNT_3 0x683A0479 480#define mmMME0_QM_CP_FENCE3_CNT_4 0x683A4481 482#define mmMME0_QM_CP_STS_0 0x683A8483 484#define mmMME0_QM_CP_STS_1 0x683AC485 486#define mmMME0_QM_CP_STS_2 0x683B0487 488#define mmMME0_QM_CP_STS_3 0x683B4489 490#define mmMME0_QM_CP_STS_4 0x683B8491 492#define mmMME0_QM_CP_CURRENT_INST_LO_0 0x683BC493 494#define mmMME0_QM_CP_CURRENT_INST_LO_1 0x683C0495 496#define mmMME0_QM_CP_CURRENT_INST_LO_2 0x683C4497 498#define mmMME0_QM_CP_CURRENT_INST_LO_3 0x683C8499 500#define mmMME0_QM_CP_CURRENT_INST_LO_4 0x683CC501 502#define mmMME0_QM_CP_CURRENT_INST_HI_0 0x683D0503 504#define mmMME0_QM_CP_CURRENT_INST_HI_1 0x683D4505 506#define mmMME0_QM_CP_CURRENT_INST_HI_2 0x683D8507 508#define mmMME0_QM_CP_CURRENT_INST_HI_3 0x683DC509 510#define mmMME0_QM_CP_CURRENT_INST_HI_4 0x683E0511 512#define mmMME0_QM_CP_BARRIER_CFG_0 0x683F4513 514#define mmMME0_QM_CP_BARRIER_CFG_1 0x683F8515 516#define mmMME0_QM_CP_BARRIER_CFG_2 0x683FC517 518#define mmMME0_QM_CP_BARRIER_CFG_3 0x68400519 520#define mmMME0_QM_CP_BARRIER_CFG_4 0x68404521 522#define mmMME0_QM_CP_DBG_0_0 0x68408523 524#define mmMME0_QM_CP_DBG_0_1 0x6840C525 526#define mmMME0_QM_CP_DBG_0_2 0x68410527 528#define mmMME0_QM_CP_DBG_0_3 0x68414529 530#define mmMME0_QM_CP_DBG_0_4 0x68418531 532#define mmMME0_QM_CP_ARUSER_31_11_0 0x6841C533 534#define mmMME0_QM_CP_ARUSER_31_11_1 0x68420535 536#define mmMME0_QM_CP_ARUSER_31_11_2 0x68424537 538#define mmMME0_QM_CP_ARUSER_31_11_3 0x68428539 540#define mmMME0_QM_CP_ARUSER_31_11_4 0x6842C541 542#define mmMME0_QM_CP_AWUSER_31_11_0 0x68430543 544#define mmMME0_QM_CP_AWUSER_31_11_1 0x68434545 546#define mmMME0_QM_CP_AWUSER_31_11_2 0x68438547 548#define mmMME0_QM_CP_AWUSER_31_11_3 0x6843C549 550#define mmMME0_QM_CP_AWUSER_31_11_4 0x68440551 552#define mmMME0_QM_ARB_CFG_0 0x68A00553 554#define mmMME0_QM_ARB_CHOISE_Q_PUSH 0x68A04555 556#define mmMME0_QM_ARB_WRR_WEIGHT_0 0x68A08557 558#define mmMME0_QM_ARB_WRR_WEIGHT_1 0x68A0C559 560#define mmMME0_QM_ARB_WRR_WEIGHT_2 0x68A10561 562#define mmMME0_QM_ARB_WRR_WEIGHT_3 0x68A14563 564#define mmMME0_QM_ARB_CFG_1 0x68A18565 566#define mmMME0_QM_ARB_MST_AVAIL_CRED_0 0x68A20567 568#define mmMME0_QM_ARB_MST_AVAIL_CRED_1 0x68A24569 570#define mmMME0_QM_ARB_MST_AVAIL_CRED_2 0x68A28571 572#define mmMME0_QM_ARB_MST_AVAIL_CRED_3 0x68A2C573 574#define mmMME0_QM_ARB_MST_AVAIL_CRED_4 0x68A30575 576#define mmMME0_QM_ARB_MST_AVAIL_CRED_5 0x68A34577 578#define mmMME0_QM_ARB_MST_AVAIL_CRED_6 0x68A38579 580#define mmMME0_QM_ARB_MST_AVAIL_CRED_7 0x68A3C581 582#define mmMME0_QM_ARB_MST_AVAIL_CRED_8 0x68A40583 584#define mmMME0_QM_ARB_MST_AVAIL_CRED_9 0x68A44585 586#define mmMME0_QM_ARB_MST_AVAIL_CRED_10 0x68A48587 588#define mmMME0_QM_ARB_MST_AVAIL_CRED_11 0x68A4C589 590#define mmMME0_QM_ARB_MST_AVAIL_CRED_12 0x68A50591 592#define mmMME0_QM_ARB_MST_AVAIL_CRED_13 0x68A54593 594#define mmMME0_QM_ARB_MST_AVAIL_CRED_14 0x68A58595 596#define mmMME0_QM_ARB_MST_AVAIL_CRED_15 0x68A5C597 598#define mmMME0_QM_ARB_MST_AVAIL_CRED_16 0x68A60599 600#define mmMME0_QM_ARB_MST_AVAIL_CRED_17 0x68A64601 602#define mmMME0_QM_ARB_MST_AVAIL_CRED_18 0x68A68603 604#define mmMME0_QM_ARB_MST_AVAIL_CRED_19 0x68A6C605 606#define mmMME0_QM_ARB_MST_AVAIL_CRED_20 0x68A70607 608#define mmMME0_QM_ARB_MST_AVAIL_CRED_21 0x68A74609 610#define mmMME0_QM_ARB_MST_AVAIL_CRED_22 0x68A78611 612#define mmMME0_QM_ARB_MST_AVAIL_CRED_23 0x68A7C613 614#define mmMME0_QM_ARB_MST_AVAIL_CRED_24 0x68A80615 616#define mmMME0_QM_ARB_MST_AVAIL_CRED_25 0x68A84617 618#define mmMME0_QM_ARB_MST_AVAIL_CRED_26 0x68A88619 620#define mmMME0_QM_ARB_MST_AVAIL_CRED_27 0x68A8C621 622#define mmMME0_QM_ARB_MST_AVAIL_CRED_28 0x68A90623 624#define mmMME0_QM_ARB_MST_AVAIL_CRED_29 0x68A94625 626#define mmMME0_QM_ARB_MST_AVAIL_CRED_30 0x68A98627 628#define mmMME0_QM_ARB_MST_AVAIL_CRED_31 0x68A9C629 630#define mmMME0_QM_ARB_MST_CRED_INC 0x68AA0631 632#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x68AA4633 634#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x68AA8635 636#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x68AAC637 638#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x68AB0639 640#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x68AB4641 642#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x68AB8643 644#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x68ABC645 646#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x68AC0647 648#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x68AC4649 650#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x68AC8651 652#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x68ACC653 654#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x68AD0655 656#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x68AD4657 658#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x68AD8659 660#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x68ADC661 662#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x68AE0663 664#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x68AE4665 666#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x68AE8667 668#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x68AEC669 670#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x68AF0671 672#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x68AF4673 674#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x68AF8675 676#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x68AFC677 678#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x68B00679 680#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x68B04681 682#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x68B08683 684#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x68B0C685 686#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x68B10687 688#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x68B14689 690#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x68B18691 692#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x68B1C693 694#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x68B20695 696#define mmMME0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x68B28697 698#define mmMME0_QM_ARB_MST_SLAVE_EN 0x68B2C699 700#define mmMME0_QM_ARB_MST_QUIET_PER 0x68B34701 702#define mmMME0_QM_ARB_SLV_CHOISE_WDT 0x68B38703 704#define mmMME0_QM_ARB_SLV_ID 0x68B3C705 706#define mmMME0_QM_ARB_MSG_MAX_INFLIGHT 0x68B44707 708#define mmMME0_QM_ARB_MSG_AWUSER_31_11 0x68B48709 710#define mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP 0x68B4C711 712#define mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x68B50713 714#define mmMME0_QM_ARB_BASE_LO 0x68B54715 716#define mmMME0_QM_ARB_BASE_HI 0x68B58717 718#define mmMME0_QM_ARB_STATE_STS 0x68B80719 720#define mmMME0_QM_ARB_CHOISE_FULLNESS_STS 0x68B84721 722#define mmMME0_QM_ARB_MSG_STS 0x68B88723 724#define mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD 0x68B8C725 726#define mmMME0_QM_ARB_ERR_CAUSE 0x68B9C727 728#define mmMME0_QM_ARB_ERR_MSG_EN 0x68BA0729 730#define mmMME0_QM_ARB_ERR_STS_DRP 0x68BA8731 732#define mmMME0_QM_ARB_MST_CRED_STS_0 0x68BB0733 734#define mmMME0_QM_ARB_MST_CRED_STS_1 0x68BB4735 736#define mmMME0_QM_ARB_MST_CRED_STS_2 0x68BB8737 738#define mmMME0_QM_ARB_MST_CRED_STS_3 0x68BBC739 740#define mmMME0_QM_ARB_MST_CRED_STS_4 0x68BC0741 742#define mmMME0_QM_ARB_MST_CRED_STS_5 0x68BC4743 744#define mmMME0_QM_ARB_MST_CRED_STS_6 0x68BC8745 746#define mmMME0_QM_ARB_MST_CRED_STS_7 0x68BCC747 748#define mmMME0_QM_ARB_MST_CRED_STS_8 0x68BD0749 750#define mmMME0_QM_ARB_MST_CRED_STS_9 0x68BD4751 752#define mmMME0_QM_ARB_MST_CRED_STS_10 0x68BD8753 754#define mmMME0_QM_ARB_MST_CRED_STS_11 0x68BDC755 756#define mmMME0_QM_ARB_MST_CRED_STS_12 0x68BE0757 758#define mmMME0_QM_ARB_MST_CRED_STS_13 0x68BE4759 760#define mmMME0_QM_ARB_MST_CRED_STS_14 0x68BE8761 762#define mmMME0_QM_ARB_MST_CRED_STS_15 0x68BEC763 764#define mmMME0_QM_ARB_MST_CRED_STS_16 0x68BF0765 766#define mmMME0_QM_ARB_MST_CRED_STS_17 0x68BF4767 768#define mmMME0_QM_ARB_MST_CRED_STS_18 0x68BF8769 770#define mmMME0_QM_ARB_MST_CRED_STS_19 0x68BFC771 772#define mmMME0_QM_ARB_MST_CRED_STS_20 0x68C00773 774#define mmMME0_QM_ARB_MST_CRED_STS_21 0x68C04775 776#define mmMME0_QM_ARB_MST_CRED_STS_22 0x68C08777 778#define mmMME0_QM_ARB_MST_CRED_STS_23 0x68C0C779 780#define mmMME0_QM_ARB_MST_CRED_STS_24 0x68C10781 782#define mmMME0_QM_ARB_MST_CRED_STS_25 0x68C14783 784#define mmMME0_QM_ARB_MST_CRED_STS_26 0x68C18785 786#define mmMME0_QM_ARB_MST_CRED_STS_27 0x68C1C787 788#define mmMME0_QM_ARB_MST_CRED_STS_28 0x68C20789 790#define mmMME0_QM_ARB_MST_CRED_STS_29 0x68C24791 792#define mmMME0_QM_ARB_MST_CRED_STS_30 0x68C28793 794#define mmMME0_QM_ARB_MST_CRED_STS_31 0x68C2C795 796#define mmMME0_QM_CGM_CFG 0x68C70797 798#define mmMME0_QM_CGM_STS 0x68C74799 800#define mmMME0_QM_CGM_CFG1 0x68C78801 802#define mmMME0_QM_LOCAL_RANGE_BASE 0x68C80803 804#define mmMME0_QM_LOCAL_RANGE_SIZE 0x68C84805 806#define mmMME0_QM_CSMR_STRICT_PRIO_CFG 0x68C90807 808#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 0x68C94809 810#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 0x68C98811 812#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 0x68C9C813 814#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 0x68CA0815 816#define mmMME0_QM_GLBL_AXCACHE 0x68CA4817 818#define mmMME0_QM_IND_GW_APB_CFG 0x68CB0819 820#define mmMME0_QM_IND_GW_APB_WDATA 0x68CB4821 822#define mmMME0_QM_IND_GW_APB_RDATA 0x68CB8823 824#define mmMME0_QM_IND_GW_APB_STATUS 0x68CBC825 826#define mmMME0_QM_GLBL_ERR_ADDR_LO 0x68CD0827 828#define mmMME0_QM_GLBL_ERR_ADDR_HI 0x68CD4829 830#define mmMME0_QM_GLBL_ERR_WDATA 0x68CD8831 832#define mmMME0_QM_GLBL_MEM_INIT_BUSY 0x68D00833 834#endif /* ASIC_REG_MME0_QM_REGS_H_ */835