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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MME2_QM_REGS_H_14#define ASIC_REG_MME2_QM_REGS_H_15 16/*17 *****************************************18 * MME2_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmMME2_QM_GLBL_CFG0 0x16800023 24#define mmMME2_QM_GLBL_CFG1 0x16800425 26#define mmMME2_QM_GLBL_PROT 0x16800827 28#define mmMME2_QM_GLBL_ERR_CFG 0x16800C29 30#define mmMME2_QM_GLBL_SECURE_PROPS_0 0x16801031 32#define mmMME2_QM_GLBL_SECURE_PROPS_1 0x16801433 34#define mmMME2_QM_GLBL_SECURE_PROPS_2 0x16801835 36#define mmMME2_QM_GLBL_SECURE_PROPS_3 0x16801C37 38#define mmMME2_QM_GLBL_SECURE_PROPS_4 0x16802039 40#define mmMME2_QM_GLBL_NON_SECURE_PROPS_0 0x16802441 42#define mmMME2_QM_GLBL_NON_SECURE_PROPS_1 0x16802843 44#define mmMME2_QM_GLBL_NON_SECURE_PROPS_2 0x16802C45 46#define mmMME2_QM_GLBL_NON_SECURE_PROPS_3 0x16803047 48#define mmMME2_QM_GLBL_NON_SECURE_PROPS_4 0x16803449 50#define mmMME2_QM_GLBL_STS0 0x16803851 52#define mmMME2_QM_GLBL_STS1_0 0x16804053 54#define mmMME2_QM_GLBL_STS1_1 0x16804455 56#define mmMME2_QM_GLBL_STS1_2 0x16804857 58#define mmMME2_QM_GLBL_STS1_3 0x16804C59 60#define mmMME2_QM_GLBL_STS1_4 0x16805061 62#define mmMME2_QM_GLBL_MSG_EN_0 0x16805463 64#define mmMME2_QM_GLBL_MSG_EN_1 0x16805865 66#define mmMME2_QM_GLBL_MSG_EN_2 0x16805C67 68#define mmMME2_QM_GLBL_MSG_EN_3 0x16806069 70#define mmMME2_QM_GLBL_MSG_EN_4 0x16806871 72#define mmMME2_QM_PQ_BASE_LO_0 0x16807073 74#define mmMME2_QM_PQ_BASE_LO_1 0x16807475 76#define mmMME2_QM_PQ_BASE_LO_2 0x16807877 78#define mmMME2_QM_PQ_BASE_LO_3 0x16807C79 80#define mmMME2_QM_PQ_BASE_HI_0 0x16808081 82#define mmMME2_QM_PQ_BASE_HI_1 0x16808483 84#define mmMME2_QM_PQ_BASE_HI_2 0x16808885 86#define mmMME2_QM_PQ_BASE_HI_3 0x16808C87 88#define mmMME2_QM_PQ_SIZE_0 0x16809089 90#define mmMME2_QM_PQ_SIZE_1 0x16809491 92#define mmMME2_QM_PQ_SIZE_2 0x16809893 94#define mmMME2_QM_PQ_SIZE_3 0x16809C95 96#define mmMME2_QM_PQ_PI_0 0x1680A097 98#define mmMME2_QM_PQ_PI_1 0x1680A499 100#define mmMME2_QM_PQ_PI_2 0x1680A8101 102#define mmMME2_QM_PQ_PI_3 0x1680AC103 104#define mmMME2_QM_PQ_CI_0 0x1680B0105 106#define mmMME2_QM_PQ_CI_1 0x1680B4107 108#define mmMME2_QM_PQ_CI_2 0x1680B8109 110#define mmMME2_QM_PQ_CI_3 0x1680BC111 112#define mmMME2_QM_PQ_CFG0_0 0x1680C0113 114#define mmMME2_QM_PQ_CFG0_1 0x1680C4115 116#define mmMME2_QM_PQ_CFG0_2 0x1680C8117 118#define mmMME2_QM_PQ_CFG0_3 0x1680CC119 120#define mmMME2_QM_PQ_CFG1_0 0x1680D0121 122#define mmMME2_QM_PQ_CFG1_1 0x1680D4123 124#define mmMME2_QM_PQ_CFG1_2 0x1680D8125 126#define mmMME2_QM_PQ_CFG1_3 0x1680DC127 128#define mmMME2_QM_PQ_ARUSER_31_11_0 0x1680E0129 130#define mmMME2_QM_PQ_ARUSER_31_11_1 0x1680E4131 132#define mmMME2_QM_PQ_ARUSER_31_11_2 0x1680E8133 134#define mmMME2_QM_PQ_ARUSER_31_11_3 0x1680EC135 136#define mmMME2_QM_PQ_STS0_0 0x1680F0137 138#define mmMME2_QM_PQ_STS0_1 0x1680F4139 140#define mmMME2_QM_PQ_STS0_2 0x1680F8141 142#define mmMME2_QM_PQ_STS0_3 0x1680FC143 144#define mmMME2_QM_PQ_STS1_0 0x168100145 146#define mmMME2_QM_PQ_STS1_1 0x168104147 148#define mmMME2_QM_PQ_STS1_2 0x168108149 150#define mmMME2_QM_PQ_STS1_3 0x16810C151 152#define mmMME2_QM_CQ_CFG0_0 0x168110153 154#define mmMME2_QM_CQ_CFG0_1 0x168114155 156#define mmMME2_QM_CQ_CFG0_2 0x168118157 158#define mmMME2_QM_CQ_CFG0_3 0x16811C159 160#define mmMME2_QM_CQ_CFG0_4 0x168120161 162#define mmMME2_QM_CQ_CFG1_0 0x168124163 164#define mmMME2_QM_CQ_CFG1_1 0x168128165 166#define mmMME2_QM_CQ_CFG1_2 0x16812C167 168#define mmMME2_QM_CQ_CFG1_3 0x168130169 170#define mmMME2_QM_CQ_CFG1_4 0x168134171 172#define mmMME2_QM_CQ_ARUSER_31_11_0 0x168138173 174#define mmMME2_QM_CQ_ARUSER_31_11_1 0x16813C175 176#define mmMME2_QM_CQ_ARUSER_31_11_2 0x168140177 178#define mmMME2_QM_CQ_ARUSER_31_11_3 0x168144179 180#define mmMME2_QM_CQ_ARUSER_31_11_4 0x168148181 182#define mmMME2_QM_CQ_STS0_0 0x16814C183 184#define mmMME2_QM_CQ_STS0_1 0x168150185 186#define mmMME2_QM_CQ_STS0_2 0x168154187 188#define mmMME2_QM_CQ_STS0_3 0x168158189 190#define mmMME2_QM_CQ_STS0_4 0x16815C191 192#define mmMME2_QM_CQ_STS1_0 0x168160193 194#define mmMME2_QM_CQ_STS1_1 0x168164195 196#define mmMME2_QM_CQ_STS1_2 0x168168197 198#define mmMME2_QM_CQ_STS1_3 0x16816C199 200#define mmMME2_QM_CQ_STS1_4 0x168170201 202#define mmMME2_QM_CQ_PTR_LO_0 0x168174203 204#define mmMME2_QM_CQ_PTR_HI_0 0x168178205 206#define mmMME2_QM_CQ_TSIZE_0 0x16817C207 208#define mmMME2_QM_CQ_CTL_0 0x168180209 210#define mmMME2_QM_CQ_PTR_LO_1 0x168184211 212#define mmMME2_QM_CQ_PTR_HI_1 0x168188213 214#define mmMME2_QM_CQ_TSIZE_1 0x16818C215 216#define mmMME2_QM_CQ_CTL_1 0x168190217 218#define mmMME2_QM_CQ_PTR_LO_2 0x168194219 220#define mmMME2_QM_CQ_PTR_HI_2 0x168198221 222#define mmMME2_QM_CQ_TSIZE_2 0x16819C223 224#define mmMME2_QM_CQ_CTL_2 0x1681A0225 226#define mmMME2_QM_CQ_PTR_LO_3 0x1681A4227 228#define mmMME2_QM_CQ_PTR_HI_3 0x1681A8229 230#define mmMME2_QM_CQ_TSIZE_3 0x1681AC231 232#define mmMME2_QM_CQ_CTL_3 0x1681B0233 234#define mmMME2_QM_CQ_PTR_LO_4 0x1681B4235 236#define mmMME2_QM_CQ_PTR_HI_4 0x1681B8237 238#define mmMME2_QM_CQ_TSIZE_4 0x1681BC239 240#define mmMME2_QM_CQ_CTL_4 0x1681C0241 242#define mmMME2_QM_CQ_PTR_LO_STS_0 0x1681C4243 244#define mmMME2_QM_CQ_PTR_LO_STS_1 0x1681C8245 246#define mmMME2_QM_CQ_PTR_LO_STS_2 0x1681CC247 248#define mmMME2_QM_CQ_PTR_LO_STS_3 0x1681D0249 250#define mmMME2_QM_CQ_PTR_LO_STS_4 0x1681D4251 252#define mmMME2_QM_CQ_PTR_HI_STS_0 0x1681D8253 254#define mmMME2_QM_CQ_PTR_HI_STS_1 0x1681DC255 256#define mmMME2_QM_CQ_PTR_HI_STS_2 0x1681E0257 258#define mmMME2_QM_CQ_PTR_HI_STS_3 0x1681E4259 260#define mmMME2_QM_CQ_PTR_HI_STS_4 0x1681E8261 262#define mmMME2_QM_CQ_TSIZE_STS_0 0x1681EC263 264#define mmMME2_QM_CQ_TSIZE_STS_1 0x1681F0265 266#define mmMME2_QM_CQ_TSIZE_STS_2 0x1681F4267 268#define mmMME2_QM_CQ_TSIZE_STS_3 0x1681F8269 270#define mmMME2_QM_CQ_TSIZE_STS_4 0x1681FC271 272#define mmMME2_QM_CQ_CTL_STS_0 0x168200273 274#define mmMME2_QM_CQ_CTL_STS_1 0x168204275 276#define mmMME2_QM_CQ_CTL_STS_2 0x168208277 278#define mmMME2_QM_CQ_CTL_STS_3 0x16820C279 280#define mmMME2_QM_CQ_CTL_STS_4 0x168210281 282#define mmMME2_QM_CQ_IFIFO_CNT_0 0x168214283 284#define mmMME2_QM_CQ_IFIFO_CNT_1 0x168218285 286#define mmMME2_QM_CQ_IFIFO_CNT_2 0x16821C287 288#define mmMME2_QM_CQ_IFIFO_CNT_3 0x168220289 290#define mmMME2_QM_CQ_IFIFO_CNT_4 0x168224291 292#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 0x168228293 294#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 0x16822C295 296#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 0x168230297 298#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 0x168234299 300#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 0x168238301 302#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 0x16823C303 304#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 0x168240305 306#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 0x168244307 308#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 0x168248309 310#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 0x16824C311 312#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 0x168250313 314#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 0x168254315 316#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 0x168258317 318#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 0x16825C319 320#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 0x168260321 322#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 0x168264323 324#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 0x168268325 326#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 0x16826C327 328#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 0x168270329 330#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 0x168274331 332#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 0x168278333 334#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 0x16827C335 336#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 0x168280337 338#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 0x168284339 340#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 0x168288341 342#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 0x16828C343 344#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 0x168290345 346#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 0x168294347 348#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 0x168298349 350#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 0x16829C351 352#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 0x1682A0353 354#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 0x1682A4355 356#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 0x1682A8357 358#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 0x1682AC359 360#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 0x1682B0361 362#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 0x1682B4363 364#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 0x1682B8365 366#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 0x1682BC367 368#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 0x1682C0369 370#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 0x1682C4371 372#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 0x1682C8373 374#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 0x1682CC375 376#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 0x1682D0377 378#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 0x1682D4379 380#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 0x1682D8381 382#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x1682E0383 384#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x1682E4385 386#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x1682E8387 388#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x1682EC389 390#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x1682F0391 392#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x1682F4393 394#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x1682F8395 396#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x1682FC397 398#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x168300399 400#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x168304401 402#define mmMME2_QM_CP_FENCE0_RDATA_0 0x168308403 404#define mmMME2_QM_CP_FENCE0_RDATA_1 0x16830C405 406#define mmMME2_QM_CP_FENCE0_RDATA_2 0x168310407 408#define mmMME2_QM_CP_FENCE0_RDATA_3 0x168314409 410#define mmMME2_QM_CP_FENCE0_RDATA_4 0x168318411 412#define mmMME2_QM_CP_FENCE1_RDATA_0 0x16831C413 414#define mmMME2_QM_CP_FENCE1_RDATA_1 0x168320415 416#define mmMME2_QM_CP_FENCE1_RDATA_2 0x168324417 418#define mmMME2_QM_CP_FENCE1_RDATA_3 0x168328419 420#define mmMME2_QM_CP_FENCE1_RDATA_4 0x16832C421 422#define mmMME2_QM_CP_FENCE2_RDATA_0 0x168330423 424#define mmMME2_QM_CP_FENCE2_RDATA_1 0x168334425 426#define mmMME2_QM_CP_FENCE2_RDATA_2 0x168338427 428#define mmMME2_QM_CP_FENCE2_RDATA_3 0x16833C429 430#define mmMME2_QM_CP_FENCE2_RDATA_4 0x168340431 432#define mmMME2_QM_CP_FENCE3_RDATA_0 0x168344433 434#define mmMME2_QM_CP_FENCE3_RDATA_1 0x168348435 436#define mmMME2_QM_CP_FENCE3_RDATA_2 0x16834C437 438#define mmMME2_QM_CP_FENCE3_RDATA_3 0x168350439 440#define mmMME2_QM_CP_FENCE3_RDATA_4 0x168354441 442#define mmMME2_QM_CP_FENCE0_CNT_0 0x168358443 444#define mmMME2_QM_CP_FENCE0_CNT_1 0x16835C445 446#define mmMME2_QM_CP_FENCE0_CNT_2 0x168360447 448#define mmMME2_QM_CP_FENCE0_CNT_3 0x168364449 450#define mmMME2_QM_CP_FENCE0_CNT_4 0x168368451 452#define mmMME2_QM_CP_FENCE1_CNT_0 0x16836C453 454#define mmMME2_QM_CP_FENCE1_CNT_1 0x168370455 456#define mmMME2_QM_CP_FENCE1_CNT_2 0x168374457 458#define mmMME2_QM_CP_FENCE1_CNT_3 0x168378459 460#define mmMME2_QM_CP_FENCE1_CNT_4 0x16837C461 462#define mmMME2_QM_CP_FENCE2_CNT_0 0x168380463 464#define mmMME2_QM_CP_FENCE2_CNT_1 0x168384465 466#define mmMME2_QM_CP_FENCE2_CNT_2 0x168388467 468#define mmMME2_QM_CP_FENCE2_CNT_3 0x16838C469 470#define mmMME2_QM_CP_FENCE2_CNT_4 0x168390471 472#define mmMME2_QM_CP_FENCE3_CNT_0 0x168394473 474#define mmMME2_QM_CP_FENCE3_CNT_1 0x168398475 476#define mmMME2_QM_CP_FENCE3_CNT_2 0x16839C477 478#define mmMME2_QM_CP_FENCE3_CNT_3 0x1683A0479 480#define mmMME2_QM_CP_FENCE3_CNT_4 0x1683A4481 482#define mmMME2_QM_CP_STS_0 0x1683A8483 484#define mmMME2_QM_CP_STS_1 0x1683AC485 486#define mmMME2_QM_CP_STS_2 0x1683B0487 488#define mmMME2_QM_CP_STS_3 0x1683B4489 490#define mmMME2_QM_CP_STS_4 0x1683B8491 492#define mmMME2_QM_CP_CURRENT_INST_LO_0 0x1683BC493 494#define mmMME2_QM_CP_CURRENT_INST_LO_1 0x1683C0495 496#define mmMME2_QM_CP_CURRENT_INST_LO_2 0x1683C4497 498#define mmMME2_QM_CP_CURRENT_INST_LO_3 0x1683C8499 500#define mmMME2_QM_CP_CURRENT_INST_LO_4 0x1683CC501 502#define mmMME2_QM_CP_CURRENT_INST_HI_0 0x1683D0503 504#define mmMME2_QM_CP_CURRENT_INST_HI_1 0x1683D4505 506#define mmMME2_QM_CP_CURRENT_INST_HI_2 0x1683D8507 508#define mmMME2_QM_CP_CURRENT_INST_HI_3 0x1683DC509 510#define mmMME2_QM_CP_CURRENT_INST_HI_4 0x1683E0511 512#define mmMME2_QM_CP_BARRIER_CFG_0 0x1683F4513 514#define mmMME2_QM_CP_BARRIER_CFG_1 0x1683F8515 516#define mmMME2_QM_CP_BARRIER_CFG_2 0x1683FC517 518#define mmMME2_QM_CP_BARRIER_CFG_3 0x168400519 520#define mmMME2_QM_CP_BARRIER_CFG_4 0x168404521 522#define mmMME2_QM_CP_DBG_0_0 0x168408523 524#define mmMME2_QM_CP_DBG_0_1 0x16840C525 526#define mmMME2_QM_CP_DBG_0_2 0x168410527 528#define mmMME2_QM_CP_DBG_0_3 0x168414529 530#define mmMME2_QM_CP_DBG_0_4 0x168418531 532#define mmMME2_QM_CP_ARUSER_31_11_0 0x16841C533 534#define mmMME2_QM_CP_ARUSER_31_11_1 0x168420535 536#define mmMME2_QM_CP_ARUSER_31_11_2 0x168424537 538#define mmMME2_QM_CP_ARUSER_31_11_3 0x168428539 540#define mmMME2_QM_CP_ARUSER_31_11_4 0x16842C541 542#define mmMME2_QM_CP_AWUSER_31_11_0 0x168430543 544#define mmMME2_QM_CP_AWUSER_31_11_1 0x168434545 546#define mmMME2_QM_CP_AWUSER_31_11_2 0x168438547 548#define mmMME2_QM_CP_AWUSER_31_11_3 0x16843C549 550#define mmMME2_QM_CP_AWUSER_31_11_4 0x168440551 552#define mmMME2_QM_ARB_CFG_0 0x168A00553 554#define mmMME2_QM_ARB_CHOISE_Q_PUSH 0x168A04555 556#define mmMME2_QM_ARB_WRR_WEIGHT_0 0x168A08557 558#define mmMME2_QM_ARB_WRR_WEIGHT_1 0x168A0C559 560#define mmMME2_QM_ARB_WRR_WEIGHT_2 0x168A10561 562#define mmMME2_QM_ARB_WRR_WEIGHT_3 0x168A14563 564#define mmMME2_QM_ARB_CFG_1 0x168A18565 566#define mmMME2_QM_ARB_MST_AVAIL_CRED_0 0x168A20567 568#define mmMME2_QM_ARB_MST_AVAIL_CRED_1 0x168A24569 570#define mmMME2_QM_ARB_MST_AVAIL_CRED_2 0x168A28571 572#define mmMME2_QM_ARB_MST_AVAIL_CRED_3 0x168A2C573 574#define mmMME2_QM_ARB_MST_AVAIL_CRED_4 0x168A30575 576#define mmMME2_QM_ARB_MST_AVAIL_CRED_5 0x168A34577 578#define mmMME2_QM_ARB_MST_AVAIL_CRED_6 0x168A38579 580#define mmMME2_QM_ARB_MST_AVAIL_CRED_7 0x168A3C581 582#define mmMME2_QM_ARB_MST_AVAIL_CRED_8 0x168A40583 584#define mmMME2_QM_ARB_MST_AVAIL_CRED_9 0x168A44585 586#define mmMME2_QM_ARB_MST_AVAIL_CRED_10 0x168A48587 588#define mmMME2_QM_ARB_MST_AVAIL_CRED_11 0x168A4C589 590#define mmMME2_QM_ARB_MST_AVAIL_CRED_12 0x168A50591 592#define mmMME2_QM_ARB_MST_AVAIL_CRED_13 0x168A54593 594#define mmMME2_QM_ARB_MST_AVAIL_CRED_14 0x168A58595 596#define mmMME2_QM_ARB_MST_AVAIL_CRED_15 0x168A5C597 598#define mmMME2_QM_ARB_MST_AVAIL_CRED_16 0x168A60599 600#define mmMME2_QM_ARB_MST_AVAIL_CRED_17 0x168A64601 602#define mmMME2_QM_ARB_MST_AVAIL_CRED_18 0x168A68603 604#define mmMME2_QM_ARB_MST_AVAIL_CRED_19 0x168A6C605 606#define mmMME2_QM_ARB_MST_AVAIL_CRED_20 0x168A70607 608#define mmMME2_QM_ARB_MST_AVAIL_CRED_21 0x168A74609 610#define mmMME2_QM_ARB_MST_AVAIL_CRED_22 0x168A78611 612#define mmMME2_QM_ARB_MST_AVAIL_CRED_23 0x168A7C613 614#define mmMME2_QM_ARB_MST_AVAIL_CRED_24 0x168A80615 616#define mmMME2_QM_ARB_MST_AVAIL_CRED_25 0x168A84617 618#define mmMME2_QM_ARB_MST_AVAIL_CRED_26 0x168A88619 620#define mmMME2_QM_ARB_MST_AVAIL_CRED_27 0x168A8C621 622#define mmMME2_QM_ARB_MST_AVAIL_CRED_28 0x168A90623 624#define mmMME2_QM_ARB_MST_AVAIL_CRED_29 0x168A94625 626#define mmMME2_QM_ARB_MST_AVAIL_CRED_30 0x168A98627 628#define mmMME2_QM_ARB_MST_AVAIL_CRED_31 0x168A9C629 630#define mmMME2_QM_ARB_MST_CRED_INC 0x168AA0631 632#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x168AA4633 634#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x168AA8635 636#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x168AAC637 638#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x168AB0639 640#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x168AB4641 642#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x168AB8643 644#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x168ABC645 646#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x168AC0647 648#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x168AC4649 650#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x168AC8651 652#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x168ACC653 654#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x168AD0655 656#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x168AD4657 658#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x168AD8659 660#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x168ADC661 662#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x168AE0663 664#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x168AE4665 666#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x168AE8667 668#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x168AEC669 670#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x168AF0671 672#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x168AF4673 674#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x168AF8675 676#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x168AFC677 678#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x168B00679 680#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x168B04681 682#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x168B08683 684#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x168B0C685 686#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x168B10687 688#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x168B14689 690#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x168B18691 692#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x168B1C693 694#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x168B20695 696#define mmMME2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x168B28697 698#define mmMME2_QM_ARB_MST_SLAVE_EN 0x168B2C699 700#define mmMME2_QM_ARB_MST_QUIET_PER 0x168B34701 702#define mmMME2_QM_ARB_SLV_CHOISE_WDT 0x168B38703 704#define mmMME2_QM_ARB_SLV_ID 0x168B3C705 706#define mmMME2_QM_ARB_MSG_MAX_INFLIGHT 0x168B44707 708#define mmMME2_QM_ARB_MSG_AWUSER_31_11 0x168B48709 710#define mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP 0x168B4C711 712#define mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x168B50713 714#define mmMME2_QM_ARB_BASE_LO 0x168B54715 716#define mmMME2_QM_ARB_BASE_HI 0x168B58717 718#define mmMME2_QM_ARB_STATE_STS 0x168B80719 720#define mmMME2_QM_ARB_CHOISE_FULLNESS_STS 0x168B84721 722#define mmMME2_QM_ARB_MSG_STS 0x168B88723 724#define mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD 0x168B8C725 726#define mmMME2_QM_ARB_ERR_CAUSE 0x168B9C727 728#define mmMME2_QM_ARB_ERR_MSG_EN 0x168BA0729 730#define mmMME2_QM_ARB_ERR_STS_DRP 0x168BA8731 732#define mmMME2_QM_ARB_MST_CRED_STS_0 0x168BB0733 734#define mmMME2_QM_ARB_MST_CRED_STS_1 0x168BB4735 736#define mmMME2_QM_ARB_MST_CRED_STS_2 0x168BB8737 738#define mmMME2_QM_ARB_MST_CRED_STS_3 0x168BBC739 740#define mmMME2_QM_ARB_MST_CRED_STS_4 0x168BC0741 742#define mmMME2_QM_ARB_MST_CRED_STS_5 0x168BC4743 744#define mmMME2_QM_ARB_MST_CRED_STS_6 0x168BC8745 746#define mmMME2_QM_ARB_MST_CRED_STS_7 0x168BCC747 748#define mmMME2_QM_ARB_MST_CRED_STS_8 0x168BD0749 750#define mmMME2_QM_ARB_MST_CRED_STS_9 0x168BD4751 752#define mmMME2_QM_ARB_MST_CRED_STS_10 0x168BD8753 754#define mmMME2_QM_ARB_MST_CRED_STS_11 0x168BDC755 756#define mmMME2_QM_ARB_MST_CRED_STS_12 0x168BE0757 758#define mmMME2_QM_ARB_MST_CRED_STS_13 0x168BE4759 760#define mmMME2_QM_ARB_MST_CRED_STS_14 0x168BE8761 762#define mmMME2_QM_ARB_MST_CRED_STS_15 0x168BEC763 764#define mmMME2_QM_ARB_MST_CRED_STS_16 0x168BF0765 766#define mmMME2_QM_ARB_MST_CRED_STS_17 0x168BF4767 768#define mmMME2_QM_ARB_MST_CRED_STS_18 0x168BF8769 770#define mmMME2_QM_ARB_MST_CRED_STS_19 0x168BFC771 772#define mmMME2_QM_ARB_MST_CRED_STS_20 0x168C00773 774#define mmMME2_QM_ARB_MST_CRED_STS_21 0x168C04775 776#define mmMME2_QM_ARB_MST_CRED_STS_22 0x168C08777 778#define mmMME2_QM_ARB_MST_CRED_STS_23 0x168C0C779 780#define mmMME2_QM_ARB_MST_CRED_STS_24 0x168C10781 782#define mmMME2_QM_ARB_MST_CRED_STS_25 0x168C14783 784#define mmMME2_QM_ARB_MST_CRED_STS_26 0x168C18785 786#define mmMME2_QM_ARB_MST_CRED_STS_27 0x168C1C787 788#define mmMME2_QM_ARB_MST_CRED_STS_28 0x168C20789 790#define mmMME2_QM_ARB_MST_CRED_STS_29 0x168C24791 792#define mmMME2_QM_ARB_MST_CRED_STS_30 0x168C28793 794#define mmMME2_QM_ARB_MST_CRED_STS_31 0x168C2C795 796#define mmMME2_QM_CGM_CFG 0x168C70797 798#define mmMME2_QM_CGM_STS 0x168C74799 800#define mmMME2_QM_CGM_CFG1 0x168C78801 802#define mmMME2_QM_LOCAL_RANGE_BASE 0x168C80803 804#define mmMME2_QM_LOCAL_RANGE_SIZE 0x168C84805 806#define mmMME2_QM_CSMR_STRICT_PRIO_CFG 0x168C90807 808#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 0x168C94809 810#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 0x168C98811 812#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 0x168C9C813 814#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 0x168CA0815 816#define mmMME2_QM_GLBL_AXCACHE 0x168CA4817 818#define mmMME2_QM_IND_GW_APB_CFG 0x168CB0819 820#define mmMME2_QM_IND_GW_APB_WDATA 0x168CB4821 822#define mmMME2_QM_IND_GW_APB_RDATA 0x168CB8823 824#define mmMME2_QM_IND_GW_APB_STATUS 0x168CBC825 826#define mmMME2_QM_GLBL_ERR_ADDR_LO 0x168CD0827 828#define mmMME2_QM_GLBL_ERR_ADDR_HI 0x168CD4829 830#define mmMME2_QM_GLBL_ERR_WDATA 0x168CD8831 832#define mmMME2_QM_GLBL_MEM_INIT_BUSY 0x168D00833 834#endif /* ASIC_REG_MME2_QM_REGS_H_ */835