73 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_MMU_UP_REGS_H_14#define ASIC_REG_MMU_UP_REGS_H_15 16/*17 *****************************************18 * MMU_UP (Prototype: MMU)19 *****************************************20 */21 22#define mmMMU_UP_MMU_ENABLE 0xC1100C23 24#define mmMMU_UP_FORCE_ORDERING 0xC1101025 26#define mmMMU_UP_FEATURE_ENABLE 0xC1101427 28#define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC1101829 30#define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C31 32#define mmMMU_UP_LOG2_DDR_SIZE 0xC1102033 34#define mmMMU_UP_SCRAMBLER 0xC1102435 36#define mmMMU_UP_MEM_INIT_BUSY 0xC1102837 38#define mmMMU_UP_SPI_MASK 0xC1102C39 40#define mmMMU_UP_SPI_CAUSE 0xC1103041 42#define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC1103443 44#define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC1103845 46#define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C47 48#define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC1104049 50#define mmMMU_UP_SPI_INTERRUPT_CLR 0xC1104451 52#define mmMMU_UP_SPI_INTERRUPT_MASK 0xC1104853 54#define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C55 56#define mmMMU_UP_SPI_CAUSE_CLR 0xC1105057 58#define mmMMU_UP_SLICE_CREDIT 0xC1105459 60#define mmMMU_UP_PIPE_CREDIT 0xC1105861 62#define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C63 64#define mmMMU_UP_RAZWI_WRITE_ID 0xC1106065 66#define mmMMU_UP_RAZWI_READ_VLD 0xC1106467 68#define mmMMU_UP_RAZWI_READ_ID 0xC1106869 70#define mmMMU_UP_MMU_BYPASS 0xC1106C71 72#endif /* ASIC_REG_MMU_UP_REGS_H_ */73