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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_NIC0_QM0_MASKS_H_14#define ASIC_REG_NIC0_QM0_MASKS_H_15 16/*17 *****************************************18 * NIC0_QM0 (Prototype: QMAN)19 *****************************************20 */21 22/* NIC0_QM0_GLBL_CFG0 */23#define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 024#define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF25#define NIC0_QM0_GLBL_CFG0_CQF_EN_SHIFT 426#define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F027#define NIC0_QM0_GLBL_CFG0_CP_EN_SHIFT 928#define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E0029 30/* NIC0_QM0_GLBL_CFG1 */31#define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 032#define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF33#define NIC0_QM0_GLBL_CFG1_CQF_STOP_SHIFT 434#define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F035#define NIC0_QM0_GLBL_CFG1_CP_STOP_SHIFT 936#define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E0037#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_SHIFT 1638#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF000039#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_SHIFT 2040#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F0000041#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_SHIFT 2542#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_MASK 0x3E00000043 44/* NIC0_QM0_GLBL_PROT */45#define NIC0_QM0_GLBL_PROT_PQF_SHIFT 046#define NIC0_QM0_GLBL_PROT_PQF_MASK 0xF47#define NIC0_QM0_GLBL_PROT_CQF_SHIFT 448#define NIC0_QM0_GLBL_PROT_CQF_MASK 0x1F049#define NIC0_QM0_GLBL_PROT_CP_SHIFT 950#define NIC0_QM0_GLBL_PROT_CP_MASK 0x3E0051#define NIC0_QM0_GLBL_PROT_ERR_SHIFT 1452#define NIC0_QM0_GLBL_PROT_ERR_MASK 0x400053#define NIC0_QM0_GLBL_PROT_ARB_SHIFT 1554#define NIC0_QM0_GLBL_PROT_ARB_MASK 0x800055 56/* NIC0_QM0_GLBL_ERR_CFG */57#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 058#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF59#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 460#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F061#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 962#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E0063#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 1664#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF000065#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 2066#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F0000067#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 2568#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E00000069#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 3170#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x8000000071 72/* NIC0_QM0_GLBL_SECURE_PROPS */73#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_SHIFT 074#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF75#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_SHIFT 076#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF77#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_SHIFT 078#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF79#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_SHIFT 080#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF81#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_SHIFT 082#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF83#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_SHIFT 1084#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_MASK 0x40085#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_SHIFT 1086#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_MASK 0x40087#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_SHIFT 1088#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_MASK 0x40089#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_SHIFT 1090#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_MASK 0x40091#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_SHIFT 1092#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_MASK 0x40093 94/* NIC0_QM0_GLBL_NON_SECURE_PROPS */95#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 096#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF97#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 098#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF99#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0100#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF101#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0102#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF103#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0104#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF105#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10106#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400107#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10108#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400109#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10110#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400111#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10112#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400113#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10114#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400115 116/* NIC0_QM0_GLBL_STS0 */117#define NIC0_QM0_GLBL_STS0_PQF_IDLE_SHIFT 0118#define NIC0_QM0_GLBL_STS0_PQF_IDLE_MASK 0xF119#define NIC0_QM0_GLBL_STS0_CQF_IDLE_SHIFT 4120#define NIC0_QM0_GLBL_STS0_CQF_IDLE_MASK 0x1F0121#define NIC0_QM0_GLBL_STS0_CP_IDLE_SHIFT 9122#define NIC0_QM0_GLBL_STS0_CP_IDLE_MASK 0x3E00123#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_SHIFT 16124#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000125#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_SHIFT 20126#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000127#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_SHIFT 25128#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000129#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_SHIFT 31130#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000131 132/* NIC0_QM0_GLBL_STS1 */133#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_SHIFT 0134#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_MASK 0x1135#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_SHIFT 1136#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_MASK 0x2137#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_SHIFT 2138#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_MASK 0x4139#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3140#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8141#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_SHIFT 4142#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_MASK 0x10143#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5144#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20145#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_SHIFT 6146#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_MASK 0x40147#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8148#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100149#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9150#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200151#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10152#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400153#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11154#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800155#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12156#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000157#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13158#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000159#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14160#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000161#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15162#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000163 164/* NIC0_QM0_GLBL_STS1_4 */165#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1166#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2167#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_SHIFT 2168#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_MASK 0x4169#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3170#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8171#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_SHIFT 4172#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_MASK 0x10173#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5174#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20175#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6176#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40177#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8178#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100179#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9180#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200181#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10182#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400183#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11184#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800185#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12186#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000187#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13188#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000189#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14190#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000191#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15192#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000193 194/* NIC0_QM0_GLBL_MSG_EN */195#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0196#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1197#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1198#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2199#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2200#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4201#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3202#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8203#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4204#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10205#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5206#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20207#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6208#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40209#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8210#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100211#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9212#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200213#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10214#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400215#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11216#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800217#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12218#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000219#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13220#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000221#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14222#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000223#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15224#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000225 226/* NIC0_QM0_GLBL_MSG_EN_4 */227#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1228#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2229#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2230#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4231#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3232#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8233#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4234#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10235#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5236#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20237#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6238#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40239#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8240#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100241#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9242#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200243#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10244#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400245#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11246#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800247#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12248#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000249#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13250#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000251#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14252#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000253#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15254#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000255 256/* NIC0_QM0_PQ_BASE_LO */257#define NIC0_QM0_PQ_BASE_LO_VAL_SHIFT 0258#define NIC0_QM0_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF259 260/* NIC0_QM0_PQ_BASE_HI */261#define NIC0_QM0_PQ_BASE_HI_VAL_SHIFT 0262#define NIC0_QM0_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF263 264/* NIC0_QM0_PQ_SIZE */265#define NIC0_QM0_PQ_SIZE_VAL_SHIFT 0266#define NIC0_QM0_PQ_SIZE_VAL_MASK 0xFFFFFFFF267 268/* NIC0_QM0_PQ_PI */269#define NIC0_QM0_PQ_PI_VAL_SHIFT 0270#define NIC0_QM0_PQ_PI_VAL_MASK 0xFFFFFFFF271 272/* NIC0_QM0_PQ_CI */273#define NIC0_QM0_PQ_CI_VAL_SHIFT 0274#define NIC0_QM0_PQ_CI_VAL_MASK 0xFFFFFFFF275 276/* NIC0_QM0_PQ_CFG0 */277#define NIC0_QM0_PQ_CFG0_RESERVED_SHIFT 0278#define NIC0_QM0_PQ_CFG0_RESERVED_MASK 0x1279 280/* NIC0_QM0_PQ_CFG1 */281#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_SHIFT 0282#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF283#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_SHIFT 16284#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000285 286/* NIC0_QM0_PQ_ARUSER_31_11 */287#define NIC0_QM0_PQ_ARUSER_31_11_VAL_SHIFT 0288#define NIC0_QM0_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF289 290/* NIC0_QM0_PQ_STS0 */291#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0292#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF293#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_SHIFT 16294#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000295 296/* NIC0_QM0_PQ_STS1 */297#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0298#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF299#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30300#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000301#define NIC0_QM0_PQ_STS1_PQ_BUSY_SHIFT 31302#define NIC0_QM0_PQ_STS1_PQ_BUSY_MASK 0x80000000303 304/* NIC0_QM0_CQ_CFG0 */305#define NIC0_QM0_CQ_CFG0_RESERVED_SHIFT 0306#define NIC0_QM0_CQ_CFG0_RESERVED_MASK 0x1307 308/* NIC0_QM0_CQ_CFG1 */309#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_SHIFT 0310#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF311#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_SHIFT 16312#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000313 314/* NIC0_QM0_CQ_ARUSER_31_11 */315#define NIC0_QM0_CQ_ARUSER_31_11_VAL_SHIFT 0316#define NIC0_QM0_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF317 318/* NIC0_QM0_CQ_STS0 */319#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0320#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF321#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_SHIFT 16322#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000323 324/* NIC0_QM0_CQ_STS1 */325#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0326#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF327#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30328#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000329#define NIC0_QM0_CQ_STS1_CQ_BUSY_SHIFT 31330#define NIC0_QM0_CQ_STS1_CQ_BUSY_MASK 0x80000000331 332/* NIC0_QM0_CQ_PTR_LO_0 */333#define NIC0_QM0_CQ_PTR_LO_0_VAL_SHIFT 0334#define NIC0_QM0_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF335 336/* NIC0_QM0_CQ_PTR_HI_0 */337#define NIC0_QM0_CQ_PTR_HI_0_VAL_SHIFT 0338#define NIC0_QM0_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF339 340/* NIC0_QM0_CQ_TSIZE_0 */341#define NIC0_QM0_CQ_TSIZE_0_VAL_SHIFT 0342#define NIC0_QM0_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF343 344/* NIC0_QM0_CQ_CTL_0 */345#define NIC0_QM0_CQ_CTL_0_RPT_SHIFT 0346#define NIC0_QM0_CQ_CTL_0_RPT_MASK 0xFFFF347#define NIC0_QM0_CQ_CTL_0_CTL_SHIFT 16348#define NIC0_QM0_CQ_CTL_0_CTL_MASK 0xFFFF0000349 350/* NIC0_QM0_CQ_PTR_LO_1 */351#define NIC0_QM0_CQ_PTR_LO_1_VAL_SHIFT 0352#define NIC0_QM0_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF353 354/* NIC0_QM0_CQ_PTR_HI_1 */355#define NIC0_QM0_CQ_PTR_HI_1_VAL_SHIFT 0356#define NIC0_QM0_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF357 358/* NIC0_QM0_CQ_TSIZE_1 */359#define NIC0_QM0_CQ_TSIZE_1_VAL_SHIFT 0360#define NIC0_QM0_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF361 362/* NIC0_QM0_CQ_CTL_1 */363#define NIC0_QM0_CQ_CTL_1_RPT_SHIFT 0364#define NIC0_QM0_CQ_CTL_1_RPT_MASK 0xFFFF365#define NIC0_QM0_CQ_CTL_1_CTL_SHIFT 16366#define NIC0_QM0_CQ_CTL_1_CTL_MASK 0xFFFF0000367 368/* NIC0_QM0_CQ_PTR_LO_2 */369#define NIC0_QM0_CQ_PTR_LO_2_VAL_SHIFT 0370#define NIC0_QM0_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF371 372/* NIC0_QM0_CQ_PTR_HI_2 */373#define NIC0_QM0_CQ_PTR_HI_2_VAL_SHIFT 0374#define NIC0_QM0_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF375 376/* NIC0_QM0_CQ_TSIZE_2 */377#define NIC0_QM0_CQ_TSIZE_2_VAL_SHIFT 0378#define NIC0_QM0_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF379 380/* NIC0_QM0_CQ_CTL_2 */381#define NIC0_QM0_CQ_CTL_2_RPT_SHIFT 0382#define NIC0_QM0_CQ_CTL_2_RPT_MASK 0xFFFF383#define NIC0_QM0_CQ_CTL_2_CTL_SHIFT 16384#define NIC0_QM0_CQ_CTL_2_CTL_MASK 0xFFFF0000385 386/* NIC0_QM0_CQ_PTR_LO_3 */387#define NIC0_QM0_CQ_PTR_LO_3_VAL_SHIFT 0388#define NIC0_QM0_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF389 390/* NIC0_QM0_CQ_PTR_HI_3 */391#define NIC0_QM0_CQ_PTR_HI_3_VAL_SHIFT 0392#define NIC0_QM0_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF393 394/* NIC0_QM0_CQ_TSIZE_3 */395#define NIC0_QM0_CQ_TSIZE_3_VAL_SHIFT 0396#define NIC0_QM0_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF397 398/* NIC0_QM0_CQ_CTL_3 */399#define NIC0_QM0_CQ_CTL_3_RPT_SHIFT 0400#define NIC0_QM0_CQ_CTL_3_RPT_MASK 0xFFFF401#define NIC0_QM0_CQ_CTL_3_CTL_SHIFT 16402#define NIC0_QM0_CQ_CTL_3_CTL_MASK 0xFFFF0000403 404/* NIC0_QM0_CQ_PTR_LO_4 */405#define NIC0_QM0_CQ_PTR_LO_4_VAL_SHIFT 0406#define NIC0_QM0_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF407 408/* NIC0_QM0_CQ_PTR_HI_4 */409#define NIC0_QM0_CQ_PTR_HI_4_VAL_SHIFT 0410#define NIC0_QM0_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF411 412/* NIC0_QM0_CQ_TSIZE_4 */413#define NIC0_QM0_CQ_TSIZE_4_VAL_SHIFT 0414#define NIC0_QM0_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF415 416/* NIC0_QM0_CQ_CTL_4 */417#define NIC0_QM0_CQ_CTL_4_RPT_SHIFT 0418#define NIC0_QM0_CQ_CTL_4_RPT_MASK 0xFFFF419#define NIC0_QM0_CQ_CTL_4_CTL_SHIFT 16420#define NIC0_QM0_CQ_CTL_4_CTL_MASK 0xFFFF0000421 422/* NIC0_QM0_CQ_PTR_LO_STS */423#define NIC0_QM0_CQ_PTR_LO_STS_VAL_SHIFT 0424#define NIC0_QM0_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF425 426/* NIC0_QM0_CQ_PTR_HI_STS */427#define NIC0_QM0_CQ_PTR_HI_STS_VAL_SHIFT 0428#define NIC0_QM0_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF429 430/* NIC0_QM0_CQ_TSIZE_STS */431#define NIC0_QM0_CQ_TSIZE_STS_VAL_SHIFT 0432#define NIC0_QM0_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF433 434/* NIC0_QM0_CQ_CTL_STS */435#define NIC0_QM0_CQ_CTL_STS_RPT_SHIFT 0436#define NIC0_QM0_CQ_CTL_STS_RPT_MASK 0xFFFF437#define NIC0_QM0_CQ_CTL_STS_CTL_SHIFT 16438#define NIC0_QM0_CQ_CTL_STS_CTL_MASK 0xFFFF0000439 440/* NIC0_QM0_CQ_IFIFO_CNT */441#define NIC0_QM0_CQ_IFIFO_CNT_VAL_SHIFT 0442#define NIC0_QM0_CQ_IFIFO_CNT_VAL_MASK 0x3443 444/* NIC0_QM0_CP_MSG_BASE0_ADDR_LO */445#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0446#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF447 448/* NIC0_QM0_CP_MSG_BASE0_ADDR_HI */449#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0450#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF451 452/* NIC0_QM0_CP_MSG_BASE1_ADDR_LO */453#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0454#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF455 456/* NIC0_QM0_CP_MSG_BASE1_ADDR_HI */457#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0458#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF459 460/* NIC0_QM0_CP_MSG_BASE2_ADDR_LO */461#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0462#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF463 464/* NIC0_QM0_CP_MSG_BASE2_ADDR_HI */465#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0466#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF467 468/* NIC0_QM0_CP_MSG_BASE3_ADDR_LO */469#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0470#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF471 472/* NIC0_QM0_CP_MSG_BASE3_ADDR_HI */473#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0474#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF475 476/* NIC0_QM0_CP_LDMA_TSIZE_OFFSET */477#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0478#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF479 480/* NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET */481#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0482#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF483 484/* NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET */485#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0486#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF487 488/* NIC0_QM0_CP_FENCE0_RDATA */489#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_SHIFT 0490#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_MASK 0xF491 492/* NIC0_QM0_CP_FENCE1_RDATA */493#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_SHIFT 0494#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_MASK 0xF495 496/* NIC0_QM0_CP_FENCE2_RDATA */497#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_SHIFT 0498#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_MASK 0xF499 500/* NIC0_QM0_CP_FENCE3_RDATA */501#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_SHIFT 0502#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_MASK 0xF503 504/* NIC0_QM0_CP_FENCE0_CNT */505#define NIC0_QM0_CP_FENCE0_CNT_VAL_SHIFT 0506#define NIC0_QM0_CP_FENCE0_CNT_VAL_MASK 0x3FFF507 508/* NIC0_QM0_CP_FENCE1_CNT */509#define NIC0_QM0_CP_FENCE1_CNT_VAL_SHIFT 0510#define NIC0_QM0_CP_FENCE1_CNT_VAL_MASK 0x3FFF511 512/* NIC0_QM0_CP_FENCE2_CNT */513#define NIC0_QM0_CP_FENCE2_CNT_VAL_SHIFT 0514#define NIC0_QM0_CP_FENCE2_CNT_VAL_MASK 0x3FFF515 516/* NIC0_QM0_CP_FENCE3_CNT */517#define NIC0_QM0_CP_FENCE3_CNT_VAL_SHIFT 0518#define NIC0_QM0_CP_FENCE3_CNT_VAL_MASK 0x3FFF519 520/* NIC0_QM0_CP_STS */521#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0522#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF523#define NIC0_QM0_CP_STS_ERDY_SHIFT 16524#define NIC0_QM0_CP_STS_ERDY_MASK 0x10000525#define NIC0_QM0_CP_STS_RRDY_SHIFT 17526#define NIC0_QM0_CP_STS_RRDY_MASK 0x20000527#define NIC0_QM0_CP_STS_MRDY_SHIFT 18528#define NIC0_QM0_CP_STS_MRDY_MASK 0x40000529#define NIC0_QM0_CP_STS_SW_STOP_SHIFT 19530#define NIC0_QM0_CP_STS_SW_STOP_MASK 0x80000531#define NIC0_QM0_CP_STS_FENCE_ID_SHIFT 20532#define NIC0_QM0_CP_STS_FENCE_ID_MASK 0x300000533#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_SHIFT 22534#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000535 536/* NIC0_QM0_CP_CURRENT_INST_LO */537#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_SHIFT 0538#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF539 540/* NIC0_QM0_CP_CURRENT_INST_HI */541#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_SHIFT 0542#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF543 544/* NIC0_QM0_CP_BARRIER_CFG */545#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_SHIFT 0546#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF547#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_SHIFT 16548#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000549 550/* NIC0_QM0_CP_DBG_0 */551#define NIC0_QM0_CP_DBG_0_CS_SHIFT 0552#define NIC0_QM0_CP_DBG_0_CS_MASK 0xF553#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4554#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10555#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5556#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20557#define NIC0_QM0_CP_DBG_0_MREB_STALL_SHIFT 6558#define NIC0_QM0_CP_DBG_0_MREB_STALL_MASK 0x40559#define NIC0_QM0_CP_DBG_0_STALL_SHIFT 7560#define NIC0_QM0_CP_DBG_0_STALL_MASK 0x80561 562/* NIC0_QM0_CP_ARUSER_31_11 */563#define NIC0_QM0_CP_ARUSER_31_11_VAL_SHIFT 0564#define NIC0_QM0_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF565 566/* NIC0_QM0_CP_AWUSER_31_11 */567#define NIC0_QM0_CP_AWUSER_31_11_VAL_SHIFT 0568#define NIC0_QM0_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF569 570/* NIC0_QM0_ARB_CFG_0 */571#define NIC0_QM0_ARB_CFG_0_TYPE_SHIFT 0572#define NIC0_QM0_ARB_CFG_0_TYPE_MASK 0x1573#define NIC0_QM0_ARB_CFG_0_IS_MASTER_SHIFT 4574#define NIC0_QM0_ARB_CFG_0_IS_MASTER_MASK 0x10575#define NIC0_QM0_ARB_CFG_0_EN_SHIFT 8576#define NIC0_QM0_ARB_CFG_0_EN_MASK 0x100577#define NIC0_QM0_ARB_CFG_0_MASK_SHIFT 12578#define NIC0_QM0_ARB_CFG_0_MASK_MASK 0xF000579#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16580#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000581 582/* NIC0_QM0_ARB_CHOISE_Q_PUSH */583#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0584#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3585 586/* NIC0_QM0_ARB_WRR_WEIGHT */587#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_SHIFT 0588#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF589 590/* NIC0_QM0_ARB_CFG_1 */591#define NIC0_QM0_ARB_CFG_1_CLR_SHIFT 0592#define NIC0_QM0_ARB_CFG_1_CLR_MASK 0x1593 594/* NIC0_QM0_ARB_MST_AVAIL_CRED */595#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_SHIFT 0596#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F597 598/* NIC0_QM0_ARB_MST_CRED_INC */599#define NIC0_QM0_ARB_MST_CRED_INC_VAL_SHIFT 0600#define NIC0_QM0_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF601 602/* NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST */603#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0604#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF605 606/* NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST */607#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0608#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF609 610/* NIC0_QM0_ARB_MST_SLAVE_EN */611#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_SHIFT 0612#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF613 614/* NIC0_QM0_ARB_MST_QUIET_PER */615#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_SHIFT 0616#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF617 618/* NIC0_QM0_ARB_SLV_CHOISE_WDT */619#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0620#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF621 622/* NIC0_QM0_ARB_SLV_ID */623#define NIC0_QM0_ARB_SLV_ID_VAL_SHIFT 0624#define NIC0_QM0_ARB_SLV_ID_VAL_MASK 0x1F625 626/* NIC0_QM0_ARB_MSG_MAX_INFLIGHT */627#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0628#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F629 630/* NIC0_QM0_ARB_MSG_AWUSER_31_11 */631#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0632#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF633 634/* NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP */635#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0636#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF637#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10638#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400639 640/* NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP */641#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0642#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF643#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10644#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400645 646/* NIC0_QM0_ARB_BASE_LO */647#define NIC0_QM0_ARB_BASE_LO_VAL_SHIFT 0648#define NIC0_QM0_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF649 650/* NIC0_QM0_ARB_BASE_HI */651#define NIC0_QM0_ARB_BASE_HI_VAL_SHIFT 0652#define NIC0_QM0_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF653 654/* NIC0_QM0_ARB_STATE_STS */655#define NIC0_QM0_ARB_STATE_STS_VAL_SHIFT 0656#define NIC0_QM0_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF657 658/* NIC0_QM0_ARB_CHOISE_FULLNESS_STS */659#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0660#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F661 662/* NIC0_QM0_ARB_MSG_STS */663#define NIC0_QM0_ARB_MSG_STS_FULL_SHIFT 0664#define NIC0_QM0_ARB_MSG_STS_FULL_MASK 0x1665#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1666#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2667 668/* NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD */669#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0670#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3671 672/* NIC0_QM0_ARB_ERR_CAUSE */673#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0674#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1675#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1676#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2677#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2678#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4679 680/* NIC0_QM0_ARB_ERR_MSG_EN */681#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0682#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1683#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1684#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2685#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2686#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4687 688/* NIC0_QM0_ARB_ERR_STS_DRP */689#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_SHIFT 0690#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_MASK 0x3691 692/* NIC0_QM0_ARB_MST_CRED_STS */693#define NIC0_QM0_ARB_MST_CRED_STS_VAL_SHIFT 0694#define NIC0_QM0_ARB_MST_CRED_STS_VAL_MASK 0x7F695 696/* NIC0_QM0_CGM_CFG */697#define NIC0_QM0_CGM_CFG_IDLE_TH_SHIFT 0698#define NIC0_QM0_CGM_CFG_IDLE_TH_MASK 0xFFF699#define NIC0_QM0_CGM_CFG_G2F_TH_SHIFT 16700#define NIC0_QM0_CGM_CFG_G2F_TH_MASK 0xFF0000701#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_SHIFT 24702#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000703#define NIC0_QM0_CGM_CFG_EN_SHIFT 31704#define NIC0_QM0_CGM_CFG_EN_MASK 0x80000000705 706/* NIC0_QM0_CGM_STS */707#define NIC0_QM0_CGM_STS_ST_SHIFT 0708#define NIC0_QM0_CGM_STS_ST_MASK 0x3709#define NIC0_QM0_CGM_STS_CG_SHIFT 4710#define NIC0_QM0_CGM_STS_CG_MASK 0x10711#define NIC0_QM0_CGM_STS_AGENT_IDLE_SHIFT 8712#define NIC0_QM0_CGM_STS_AGENT_IDLE_MASK 0x100713#define NIC0_QM0_CGM_STS_AXI_IDLE_SHIFT 9714#define NIC0_QM0_CGM_STS_AXI_IDLE_MASK 0x200715#define NIC0_QM0_CGM_STS_CP_IDLE_SHIFT 10716#define NIC0_QM0_CGM_STS_CP_IDLE_MASK 0x400717 718/* NIC0_QM0_CGM_CFG1 */719#define NIC0_QM0_CGM_CFG1_MASK_TH_SHIFT 0720#define NIC0_QM0_CGM_CFG1_MASK_TH_MASK 0xFF721 722/* NIC0_QM0_LOCAL_RANGE_BASE */723#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_SHIFT 0724#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF725 726/* NIC0_QM0_LOCAL_RANGE_SIZE */727#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_SHIFT 0728#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF729 730/* NIC0_QM0_CSMR_STRICT_PRIO_CFG */731#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0732#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1733 734/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_1 */735#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0736#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF737#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31738#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000739 740/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_0 */741#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0742#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF743#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16744#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000745 746/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_1 */747#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0748#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF749#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31750#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000751 752/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_0 */753#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0754#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF755#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16756#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000757 758/* NIC0_QM0_GLBL_AXCACHE */759#define NIC0_QM0_GLBL_AXCACHE_AR_SHIFT 0760#define NIC0_QM0_GLBL_AXCACHE_AR_MASK 0xF761#define NIC0_QM0_GLBL_AXCACHE_AW_SHIFT 16762#define NIC0_QM0_GLBL_AXCACHE_AW_MASK 0xF0000763 764/* NIC0_QM0_IND_GW_APB_CFG */765#define NIC0_QM0_IND_GW_APB_CFG_ADDR_SHIFT 0766#define NIC0_QM0_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF767#define NIC0_QM0_IND_GW_APB_CFG_CMD_SHIFT 31768#define NIC0_QM0_IND_GW_APB_CFG_CMD_MASK 0x80000000769 770/* NIC0_QM0_IND_GW_APB_WDATA */771#define NIC0_QM0_IND_GW_APB_WDATA_VAL_SHIFT 0772#define NIC0_QM0_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF773 774/* NIC0_QM0_IND_GW_APB_RDATA */775#define NIC0_QM0_IND_GW_APB_RDATA_VAL_SHIFT 0776#define NIC0_QM0_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF777 778/* NIC0_QM0_IND_GW_APB_STATUS */779#define NIC0_QM0_IND_GW_APB_STATUS_RDY_SHIFT 0780#define NIC0_QM0_IND_GW_APB_STATUS_RDY_MASK 0x1781#define NIC0_QM0_IND_GW_APB_STATUS_ERR_SHIFT 1782#define NIC0_QM0_IND_GW_APB_STATUS_ERR_MASK 0x2783 784/* NIC0_QM0_GLBL_ERR_ADDR_LO */785#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_SHIFT 0786#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF787 788/* NIC0_QM0_GLBL_ERR_ADDR_HI */789#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_SHIFT 0790#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF791 792/* NIC0_QM0_GLBL_ERR_WDATA */793#define NIC0_QM0_GLBL_ERR_WDATA_VAL_SHIFT 0794#define NIC0_QM0_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF795 796/* NIC0_QM0_GLBL_MEM_INIT_BUSY */797#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0798#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF799 800#endif /* ASIC_REG_NIC0_QM0_MASKS_H_ */801