835 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_NIC2_QM0_REGS_H_14#define ASIC_REG_NIC2_QM0_REGS_H_15 16/*17 *****************************************18 * NIC2_QM0 (Prototype: QMAN)19 *****************************************20 */21 22#define mmNIC2_QM0_GLBL_CFG0 0xD6000023 24#define mmNIC2_QM0_GLBL_CFG1 0xD6000425 26#define mmNIC2_QM0_GLBL_PROT 0xD6000827 28#define mmNIC2_QM0_GLBL_ERR_CFG 0xD6000C29 30#define mmNIC2_QM0_GLBL_SECURE_PROPS_0 0xD6001031 32#define mmNIC2_QM0_GLBL_SECURE_PROPS_1 0xD6001433 34#define mmNIC2_QM0_GLBL_SECURE_PROPS_2 0xD6001835 36#define mmNIC2_QM0_GLBL_SECURE_PROPS_3 0xD6001C37 38#define mmNIC2_QM0_GLBL_SECURE_PROPS_4 0xD6002039 40#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0 0xD6002441 42#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1 0xD6002843 44#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2 0xD6002C45 46#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3 0xD6003047 48#define mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4 0xD6003449 50#define mmNIC2_QM0_GLBL_STS0 0xD6003851 52#define mmNIC2_QM0_GLBL_STS1_0 0xD6004053 54#define mmNIC2_QM0_GLBL_STS1_1 0xD6004455 56#define mmNIC2_QM0_GLBL_STS1_2 0xD6004857 58#define mmNIC2_QM0_GLBL_STS1_3 0xD6004C59 60#define mmNIC2_QM0_GLBL_STS1_4 0xD6005061 62#define mmNIC2_QM0_GLBL_MSG_EN_0 0xD6005463 64#define mmNIC2_QM0_GLBL_MSG_EN_1 0xD6005865 66#define mmNIC2_QM0_GLBL_MSG_EN_2 0xD6005C67 68#define mmNIC2_QM0_GLBL_MSG_EN_3 0xD6006069 70#define mmNIC2_QM0_GLBL_MSG_EN_4 0xD6006871 72#define mmNIC2_QM0_PQ_BASE_LO_0 0xD6007073 74#define mmNIC2_QM0_PQ_BASE_LO_1 0xD6007475 76#define mmNIC2_QM0_PQ_BASE_LO_2 0xD6007877 78#define mmNIC2_QM0_PQ_BASE_LO_3 0xD6007C79 80#define mmNIC2_QM0_PQ_BASE_HI_0 0xD6008081 82#define mmNIC2_QM0_PQ_BASE_HI_1 0xD6008483 84#define mmNIC2_QM0_PQ_BASE_HI_2 0xD6008885 86#define mmNIC2_QM0_PQ_BASE_HI_3 0xD6008C87 88#define mmNIC2_QM0_PQ_SIZE_0 0xD6009089 90#define mmNIC2_QM0_PQ_SIZE_1 0xD6009491 92#define mmNIC2_QM0_PQ_SIZE_2 0xD6009893 94#define mmNIC2_QM0_PQ_SIZE_3 0xD6009C95 96#define mmNIC2_QM0_PQ_PI_0 0xD600A097 98#define mmNIC2_QM0_PQ_PI_1 0xD600A499 100#define mmNIC2_QM0_PQ_PI_2 0xD600A8101 102#define mmNIC2_QM0_PQ_PI_3 0xD600AC103 104#define mmNIC2_QM0_PQ_CI_0 0xD600B0105 106#define mmNIC2_QM0_PQ_CI_1 0xD600B4107 108#define mmNIC2_QM0_PQ_CI_2 0xD600B8109 110#define mmNIC2_QM0_PQ_CI_3 0xD600BC111 112#define mmNIC2_QM0_PQ_CFG0_0 0xD600C0113 114#define mmNIC2_QM0_PQ_CFG0_1 0xD600C4115 116#define mmNIC2_QM0_PQ_CFG0_2 0xD600C8117 118#define mmNIC2_QM0_PQ_CFG0_3 0xD600CC119 120#define mmNIC2_QM0_PQ_CFG1_0 0xD600D0121 122#define mmNIC2_QM0_PQ_CFG1_1 0xD600D4123 124#define mmNIC2_QM0_PQ_CFG1_2 0xD600D8125 126#define mmNIC2_QM0_PQ_CFG1_3 0xD600DC127 128#define mmNIC2_QM0_PQ_ARUSER_31_11_0 0xD600E0129 130#define mmNIC2_QM0_PQ_ARUSER_31_11_1 0xD600E4131 132#define mmNIC2_QM0_PQ_ARUSER_31_11_2 0xD600E8133 134#define mmNIC2_QM0_PQ_ARUSER_31_11_3 0xD600EC135 136#define mmNIC2_QM0_PQ_STS0_0 0xD600F0137 138#define mmNIC2_QM0_PQ_STS0_1 0xD600F4139 140#define mmNIC2_QM0_PQ_STS0_2 0xD600F8141 142#define mmNIC2_QM0_PQ_STS0_3 0xD600FC143 144#define mmNIC2_QM0_PQ_STS1_0 0xD60100145 146#define mmNIC2_QM0_PQ_STS1_1 0xD60104147 148#define mmNIC2_QM0_PQ_STS1_2 0xD60108149 150#define mmNIC2_QM0_PQ_STS1_3 0xD6010C151 152#define mmNIC2_QM0_CQ_CFG0_0 0xD60110153 154#define mmNIC2_QM0_CQ_CFG0_1 0xD60114155 156#define mmNIC2_QM0_CQ_CFG0_2 0xD60118157 158#define mmNIC2_QM0_CQ_CFG0_3 0xD6011C159 160#define mmNIC2_QM0_CQ_CFG0_4 0xD60120161 162#define mmNIC2_QM0_CQ_CFG1_0 0xD60124163 164#define mmNIC2_QM0_CQ_CFG1_1 0xD60128165 166#define mmNIC2_QM0_CQ_CFG1_2 0xD6012C167 168#define mmNIC2_QM0_CQ_CFG1_3 0xD60130169 170#define mmNIC2_QM0_CQ_CFG1_4 0xD60134171 172#define mmNIC2_QM0_CQ_ARUSER_31_11_0 0xD60138173 174#define mmNIC2_QM0_CQ_ARUSER_31_11_1 0xD6013C175 176#define mmNIC2_QM0_CQ_ARUSER_31_11_2 0xD60140177 178#define mmNIC2_QM0_CQ_ARUSER_31_11_3 0xD60144179 180#define mmNIC2_QM0_CQ_ARUSER_31_11_4 0xD60148181 182#define mmNIC2_QM0_CQ_STS0_0 0xD6014C183 184#define mmNIC2_QM0_CQ_STS0_1 0xD60150185 186#define mmNIC2_QM0_CQ_STS0_2 0xD60154187 188#define mmNIC2_QM0_CQ_STS0_3 0xD60158189 190#define mmNIC2_QM0_CQ_STS0_4 0xD6015C191 192#define mmNIC2_QM0_CQ_STS1_0 0xD60160193 194#define mmNIC2_QM0_CQ_STS1_1 0xD60164195 196#define mmNIC2_QM0_CQ_STS1_2 0xD60168197 198#define mmNIC2_QM0_CQ_STS1_3 0xD6016C199 200#define mmNIC2_QM0_CQ_STS1_4 0xD60170201 202#define mmNIC2_QM0_CQ_PTR_LO_0 0xD60174203 204#define mmNIC2_QM0_CQ_PTR_HI_0 0xD60178205 206#define mmNIC2_QM0_CQ_TSIZE_0 0xD6017C207 208#define mmNIC2_QM0_CQ_CTL_0 0xD60180209 210#define mmNIC2_QM0_CQ_PTR_LO_1 0xD60184211 212#define mmNIC2_QM0_CQ_PTR_HI_1 0xD60188213 214#define mmNIC2_QM0_CQ_TSIZE_1 0xD6018C215 216#define mmNIC2_QM0_CQ_CTL_1 0xD60190217 218#define mmNIC2_QM0_CQ_PTR_LO_2 0xD60194219 220#define mmNIC2_QM0_CQ_PTR_HI_2 0xD60198221 222#define mmNIC2_QM0_CQ_TSIZE_2 0xD6019C223 224#define mmNIC2_QM0_CQ_CTL_2 0xD601A0225 226#define mmNIC2_QM0_CQ_PTR_LO_3 0xD601A4227 228#define mmNIC2_QM0_CQ_PTR_HI_3 0xD601A8229 230#define mmNIC2_QM0_CQ_TSIZE_3 0xD601AC231 232#define mmNIC2_QM0_CQ_CTL_3 0xD601B0233 234#define mmNIC2_QM0_CQ_PTR_LO_4 0xD601B4235 236#define mmNIC2_QM0_CQ_PTR_HI_4 0xD601B8237 238#define mmNIC2_QM0_CQ_TSIZE_4 0xD601BC239 240#define mmNIC2_QM0_CQ_CTL_4 0xD601C0241 242#define mmNIC2_QM0_CQ_PTR_LO_STS_0 0xD601C4243 244#define mmNIC2_QM0_CQ_PTR_LO_STS_1 0xD601C8245 246#define mmNIC2_QM0_CQ_PTR_LO_STS_2 0xD601CC247 248#define mmNIC2_QM0_CQ_PTR_LO_STS_3 0xD601D0249 250#define mmNIC2_QM0_CQ_PTR_LO_STS_4 0xD601D4251 252#define mmNIC2_QM0_CQ_PTR_HI_STS_0 0xD601D8253 254#define mmNIC2_QM0_CQ_PTR_HI_STS_1 0xD601DC255 256#define mmNIC2_QM0_CQ_PTR_HI_STS_2 0xD601E0257 258#define mmNIC2_QM0_CQ_PTR_HI_STS_3 0xD601E4259 260#define mmNIC2_QM0_CQ_PTR_HI_STS_4 0xD601E8261 262#define mmNIC2_QM0_CQ_TSIZE_STS_0 0xD601EC263 264#define mmNIC2_QM0_CQ_TSIZE_STS_1 0xD601F0265 266#define mmNIC2_QM0_CQ_TSIZE_STS_2 0xD601F4267 268#define mmNIC2_QM0_CQ_TSIZE_STS_3 0xD601F8269 270#define mmNIC2_QM0_CQ_TSIZE_STS_4 0xD601FC271 272#define mmNIC2_QM0_CQ_CTL_STS_0 0xD60200273 274#define mmNIC2_QM0_CQ_CTL_STS_1 0xD60204275 276#define mmNIC2_QM0_CQ_CTL_STS_2 0xD60208277 278#define mmNIC2_QM0_CQ_CTL_STS_3 0xD6020C279 280#define mmNIC2_QM0_CQ_CTL_STS_4 0xD60210281 282#define mmNIC2_QM0_CQ_IFIFO_CNT_0 0xD60214283 284#define mmNIC2_QM0_CQ_IFIFO_CNT_1 0xD60218285 286#define mmNIC2_QM0_CQ_IFIFO_CNT_2 0xD6021C287 288#define mmNIC2_QM0_CQ_IFIFO_CNT_3 0xD60220289 290#define mmNIC2_QM0_CQ_IFIFO_CNT_4 0xD60224291 292#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_0 0xD60228293 294#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_1 0xD6022C295 296#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_2 0xD60230297 298#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_3 0xD60234299 300#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_4 0xD60238301 302#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_0 0xD6023C303 304#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_1 0xD60240305 306#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_2 0xD60244307 308#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_3 0xD60248309 310#define mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_4 0xD6024C311 312#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_0 0xD60250313 314#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_1 0xD60254315 316#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_2 0xD60258317 318#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_3 0xD6025C319 320#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_4 0xD60260321 322#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_0 0xD60264323 324#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_1 0xD60268325 326#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_2 0xD6026C327 328#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_3 0xD60270329 330#define mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_4 0xD60274331 332#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_0 0xD60278333 334#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_1 0xD6027C335 336#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 0xD60280337 338#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_3 0xD60284339 340#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_4 0xD60288341 342#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_0 0xD6028C343 344#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_1 0xD60290345 346#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_2 0xD60294347 348#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_3 0xD60298349 350#define mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_4 0xD6029C351 352#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_0 0xD602A0353 354#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_1 0xD602A4355 356#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_2 0xD602A8357 358#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_3 0xD602AC359 360#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_4 0xD602B0361 362#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_0 0xD602B4363 364#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_1 0xD602B8365 366#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_2 0xD602BC367 368#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_3 0xD602C0369 370#define mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_4 0xD602C4371 372#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_0 0xD602C8373 374#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_1 0xD602CC375 376#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_2 0xD602D0377 378#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_3 0xD602D4379 380#define mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_4 0xD602D8381 382#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD602E0383 384#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD602E4385 386#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD602E8387 388#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD602EC389 390#define mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD602F0391 392#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD602F4393 394#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD602F8395 396#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD602FC397 398#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD60300399 400#define mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD60304401 402#define mmNIC2_QM0_CP_FENCE0_RDATA_0 0xD60308403 404#define mmNIC2_QM0_CP_FENCE0_RDATA_1 0xD6030C405 406#define mmNIC2_QM0_CP_FENCE0_RDATA_2 0xD60310407 408#define mmNIC2_QM0_CP_FENCE0_RDATA_3 0xD60314409 410#define mmNIC2_QM0_CP_FENCE0_RDATA_4 0xD60318411 412#define mmNIC2_QM0_CP_FENCE1_RDATA_0 0xD6031C413 414#define mmNIC2_QM0_CP_FENCE1_RDATA_1 0xD60320415 416#define mmNIC2_QM0_CP_FENCE1_RDATA_2 0xD60324417 418#define mmNIC2_QM0_CP_FENCE1_RDATA_3 0xD60328419 420#define mmNIC2_QM0_CP_FENCE1_RDATA_4 0xD6032C421 422#define mmNIC2_QM0_CP_FENCE2_RDATA_0 0xD60330423 424#define mmNIC2_QM0_CP_FENCE2_RDATA_1 0xD60334425 426#define mmNIC2_QM0_CP_FENCE2_RDATA_2 0xD60338427 428#define mmNIC2_QM0_CP_FENCE2_RDATA_3 0xD6033C429 430#define mmNIC2_QM0_CP_FENCE2_RDATA_4 0xD60340431 432#define mmNIC2_QM0_CP_FENCE3_RDATA_0 0xD60344433 434#define mmNIC2_QM0_CP_FENCE3_RDATA_1 0xD60348435 436#define mmNIC2_QM0_CP_FENCE3_RDATA_2 0xD6034C437 438#define mmNIC2_QM0_CP_FENCE3_RDATA_3 0xD60350439 440#define mmNIC2_QM0_CP_FENCE3_RDATA_4 0xD60354441 442#define mmNIC2_QM0_CP_FENCE0_CNT_0 0xD60358443 444#define mmNIC2_QM0_CP_FENCE0_CNT_1 0xD6035C445 446#define mmNIC2_QM0_CP_FENCE0_CNT_2 0xD60360447 448#define mmNIC2_QM0_CP_FENCE0_CNT_3 0xD60364449 450#define mmNIC2_QM0_CP_FENCE0_CNT_4 0xD60368451 452#define mmNIC2_QM0_CP_FENCE1_CNT_0 0xD6036C453 454#define mmNIC2_QM0_CP_FENCE1_CNT_1 0xD60370455 456#define mmNIC2_QM0_CP_FENCE1_CNT_2 0xD60374457 458#define mmNIC2_QM0_CP_FENCE1_CNT_3 0xD60378459 460#define mmNIC2_QM0_CP_FENCE1_CNT_4 0xD6037C461 462#define mmNIC2_QM0_CP_FENCE2_CNT_0 0xD60380463 464#define mmNIC2_QM0_CP_FENCE2_CNT_1 0xD60384465 466#define mmNIC2_QM0_CP_FENCE2_CNT_2 0xD60388467 468#define mmNIC2_QM0_CP_FENCE2_CNT_3 0xD6038C469 470#define mmNIC2_QM0_CP_FENCE2_CNT_4 0xD60390471 472#define mmNIC2_QM0_CP_FENCE3_CNT_0 0xD60394473 474#define mmNIC2_QM0_CP_FENCE3_CNT_1 0xD60398475 476#define mmNIC2_QM0_CP_FENCE3_CNT_2 0xD6039C477 478#define mmNIC2_QM0_CP_FENCE3_CNT_3 0xD603A0479 480#define mmNIC2_QM0_CP_FENCE3_CNT_4 0xD603A4481 482#define mmNIC2_QM0_CP_STS_0 0xD603A8483 484#define mmNIC2_QM0_CP_STS_1 0xD603AC485 486#define mmNIC2_QM0_CP_STS_2 0xD603B0487 488#define mmNIC2_QM0_CP_STS_3 0xD603B4489 490#define mmNIC2_QM0_CP_STS_4 0xD603B8491 492#define mmNIC2_QM0_CP_CURRENT_INST_LO_0 0xD603BC493 494#define mmNIC2_QM0_CP_CURRENT_INST_LO_1 0xD603C0495 496#define mmNIC2_QM0_CP_CURRENT_INST_LO_2 0xD603C4497 498#define mmNIC2_QM0_CP_CURRENT_INST_LO_3 0xD603C8499 500#define mmNIC2_QM0_CP_CURRENT_INST_LO_4 0xD603CC501 502#define mmNIC2_QM0_CP_CURRENT_INST_HI_0 0xD603D0503 504#define mmNIC2_QM0_CP_CURRENT_INST_HI_1 0xD603D4505 506#define mmNIC2_QM0_CP_CURRENT_INST_HI_2 0xD603D8507 508#define mmNIC2_QM0_CP_CURRENT_INST_HI_3 0xD603DC509 510#define mmNIC2_QM0_CP_CURRENT_INST_HI_4 0xD603E0511 512#define mmNIC2_QM0_CP_BARRIER_CFG_0 0xD603F4513 514#define mmNIC2_QM0_CP_BARRIER_CFG_1 0xD603F8515 516#define mmNIC2_QM0_CP_BARRIER_CFG_2 0xD603FC517 518#define mmNIC2_QM0_CP_BARRIER_CFG_3 0xD60400519 520#define mmNIC2_QM0_CP_BARRIER_CFG_4 0xD60404521 522#define mmNIC2_QM0_CP_DBG_0_0 0xD60408523 524#define mmNIC2_QM0_CP_DBG_0_1 0xD6040C525 526#define mmNIC2_QM0_CP_DBG_0_2 0xD60410527 528#define mmNIC2_QM0_CP_DBG_0_3 0xD60414529 530#define mmNIC2_QM0_CP_DBG_0_4 0xD60418531 532#define mmNIC2_QM0_CP_ARUSER_31_11_0 0xD6041C533 534#define mmNIC2_QM0_CP_ARUSER_31_11_1 0xD60420535 536#define mmNIC2_QM0_CP_ARUSER_31_11_2 0xD60424537 538#define mmNIC2_QM0_CP_ARUSER_31_11_3 0xD60428539 540#define mmNIC2_QM0_CP_ARUSER_31_11_4 0xD6042C541 542#define mmNIC2_QM0_CP_AWUSER_31_11_0 0xD60430543 544#define mmNIC2_QM0_CP_AWUSER_31_11_1 0xD60434545 546#define mmNIC2_QM0_CP_AWUSER_31_11_2 0xD60438547 548#define mmNIC2_QM0_CP_AWUSER_31_11_3 0xD6043C549 550#define mmNIC2_QM0_CP_AWUSER_31_11_4 0xD60440551 552#define mmNIC2_QM0_ARB_CFG_0 0xD60A00553 554#define mmNIC2_QM0_ARB_CHOISE_Q_PUSH 0xD60A04555 556#define mmNIC2_QM0_ARB_WRR_WEIGHT_0 0xD60A08557 558#define mmNIC2_QM0_ARB_WRR_WEIGHT_1 0xD60A0C559 560#define mmNIC2_QM0_ARB_WRR_WEIGHT_2 0xD60A10561 562#define mmNIC2_QM0_ARB_WRR_WEIGHT_3 0xD60A14563 564#define mmNIC2_QM0_ARB_CFG_1 0xD60A18565 566#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_0 0xD60A20567 568#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_1 0xD60A24569 570#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_2 0xD60A28571 572#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_3 0xD60A2C573 574#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_4 0xD60A30575 576#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_5 0xD60A34577 578#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_6 0xD60A38579 580#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_7 0xD60A3C581 582#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_8 0xD60A40583 584#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_9 0xD60A44585 586#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_10 0xD60A48587 588#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_11 0xD60A4C589 590#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_12 0xD60A50591 592#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_13 0xD60A54593 594#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_14 0xD60A58595 596#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_15 0xD60A5C597 598#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_16 0xD60A60599 600#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_17 0xD60A64601 602#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_18 0xD60A68603 604#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_19 0xD60A6C605 606#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_20 0xD60A70607 608#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_21 0xD60A74609 610#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_22 0xD60A78611 612#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_23 0xD60A7C613 614#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 0xD60A80615 616#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_25 0xD60A84617 618#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_26 0xD60A88619 620#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_27 0xD60A8C621 622#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_28 0xD60A90623 624#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_29 0xD60A94625 626#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_30 0xD60A98627 628#define mmNIC2_QM0_ARB_MST_AVAIL_CRED_31 0xD60A9C629 630#define mmNIC2_QM0_ARB_MST_CRED_INC 0xD60AA0631 632#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xD60AA4633 634#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xD60AA8635 636#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xD60AAC637 638#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xD60AB0639 640#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xD60AB4641 642#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xD60AB8643 644#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xD60ABC645 646#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xD60AC0647 648#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xD60AC4649 650#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xD60AC8651 652#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xD60ACC653 654#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xD60AD0655 656#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xD60AD4657 658#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xD60AD8659 660#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xD60ADC661 662#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xD60AE0663 664#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xD60AE4665 666#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xD60AE8667 668#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xD60AEC669 670#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xD60AF0671 672#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xD60AF4673 674#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xD60AF8675 676#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xD60AFC677 678#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xD60B00679 680#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xD60B04681 682#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xD60B08683 684#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xD60B0C685 686#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xD60B10687 688#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xD60B14689 690#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xD60B18691 692#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xD60B1C693 694#define mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xD60B20695 696#define mmNIC2_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xD60B28697 698#define mmNIC2_QM0_ARB_MST_SLAVE_EN 0xD60B2C699 700#define mmNIC2_QM0_ARB_MST_QUIET_PER 0xD60B34701 702#define mmNIC2_QM0_ARB_SLV_CHOISE_WDT 0xD60B38703 704#define mmNIC2_QM0_ARB_SLV_ID 0xD60B3C705 706#define mmNIC2_QM0_ARB_MSG_MAX_INFLIGHT 0xD60B44707 708#define mmNIC2_QM0_ARB_MSG_AWUSER_31_11 0xD60B48709 710#define mmNIC2_QM0_ARB_MSG_AWUSER_SEC_PROP 0xD60B4C711 712#define mmNIC2_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xD60B50713 714#define mmNIC2_QM0_ARB_BASE_LO 0xD60B54715 716#define mmNIC2_QM0_ARB_BASE_HI 0xD60B58717 718#define mmNIC2_QM0_ARB_STATE_STS 0xD60B80719 720#define mmNIC2_QM0_ARB_CHOISE_FULLNESS_STS 0xD60B84721 722#define mmNIC2_QM0_ARB_MSG_STS 0xD60B88723 724#define mmNIC2_QM0_ARB_SLV_CHOISE_Q_HEAD 0xD60B8C725 726#define mmNIC2_QM0_ARB_ERR_CAUSE 0xD60B9C727 728#define mmNIC2_QM0_ARB_ERR_MSG_EN 0xD60BA0729 730#define mmNIC2_QM0_ARB_ERR_STS_DRP 0xD60BA8731 732#define mmNIC2_QM0_ARB_MST_CRED_STS_0 0xD60BB0733 734#define mmNIC2_QM0_ARB_MST_CRED_STS_1 0xD60BB4735 736#define mmNIC2_QM0_ARB_MST_CRED_STS_2 0xD60BB8737 738#define mmNIC2_QM0_ARB_MST_CRED_STS_3 0xD60BBC739 740#define mmNIC2_QM0_ARB_MST_CRED_STS_4 0xD60BC0741 742#define mmNIC2_QM0_ARB_MST_CRED_STS_5 0xD60BC4743 744#define mmNIC2_QM0_ARB_MST_CRED_STS_6 0xD60BC8745 746#define mmNIC2_QM0_ARB_MST_CRED_STS_7 0xD60BCC747 748#define mmNIC2_QM0_ARB_MST_CRED_STS_8 0xD60BD0749 750#define mmNIC2_QM0_ARB_MST_CRED_STS_9 0xD60BD4751 752#define mmNIC2_QM0_ARB_MST_CRED_STS_10 0xD60BD8753 754#define mmNIC2_QM0_ARB_MST_CRED_STS_11 0xD60BDC755 756#define mmNIC2_QM0_ARB_MST_CRED_STS_12 0xD60BE0757 758#define mmNIC2_QM0_ARB_MST_CRED_STS_13 0xD60BE4759 760#define mmNIC2_QM0_ARB_MST_CRED_STS_14 0xD60BE8761 762#define mmNIC2_QM0_ARB_MST_CRED_STS_15 0xD60BEC763 764#define mmNIC2_QM0_ARB_MST_CRED_STS_16 0xD60BF0765 766#define mmNIC2_QM0_ARB_MST_CRED_STS_17 0xD60BF4767 768#define mmNIC2_QM0_ARB_MST_CRED_STS_18 0xD60BF8769 770#define mmNIC2_QM0_ARB_MST_CRED_STS_19 0xD60BFC771 772#define mmNIC2_QM0_ARB_MST_CRED_STS_20 0xD60C00773 774#define mmNIC2_QM0_ARB_MST_CRED_STS_21 0xD60C04775 776#define mmNIC2_QM0_ARB_MST_CRED_STS_22 0xD60C08777 778#define mmNIC2_QM0_ARB_MST_CRED_STS_23 0xD60C0C779 780#define mmNIC2_QM0_ARB_MST_CRED_STS_24 0xD60C10781 782#define mmNIC2_QM0_ARB_MST_CRED_STS_25 0xD60C14783 784#define mmNIC2_QM0_ARB_MST_CRED_STS_26 0xD60C18785 786#define mmNIC2_QM0_ARB_MST_CRED_STS_27 0xD60C1C787 788#define mmNIC2_QM0_ARB_MST_CRED_STS_28 0xD60C20789 790#define mmNIC2_QM0_ARB_MST_CRED_STS_29 0xD60C24791 792#define mmNIC2_QM0_ARB_MST_CRED_STS_30 0xD60C28793 794#define mmNIC2_QM0_ARB_MST_CRED_STS_31 0xD60C2C795 796#define mmNIC2_QM0_CGM_CFG 0xD60C70797 798#define mmNIC2_QM0_CGM_STS 0xD60C74799 800#define mmNIC2_QM0_CGM_CFG1 0xD60C78801 802#define mmNIC2_QM0_LOCAL_RANGE_BASE 0xD60C80803 804#define mmNIC2_QM0_LOCAL_RANGE_SIZE 0xD60C84805 806#define mmNIC2_QM0_CSMR_STRICT_PRIO_CFG 0xD60C90807 808#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_1 0xD60C94809 810#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_0 0xD60C98811 812#define mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_1 0xD60C9C813 814#define mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_0 0xD60CA0815 816#define mmNIC2_QM0_GLBL_AXCACHE 0xD60CA4817 818#define mmNIC2_QM0_IND_GW_APB_CFG 0xD60CB0819 820#define mmNIC2_QM0_IND_GW_APB_WDATA 0xD60CB4821 822#define mmNIC2_QM0_IND_GW_APB_RDATA 0xD60CB8823 824#define mmNIC2_QM0_IND_GW_APB_STATUS 0xD60CBC825 826#define mmNIC2_QM0_GLBL_ERR_ADDR_LO 0xD60CD0827 828#define mmNIC2_QM0_GLBL_ERR_ADDR_HI 0xD60CD4829 830#define mmNIC2_QM0_GLBL_ERR_WDATA 0xD60CD8831 832#define mmNIC2_QM0_GLBL_MEM_INIT_BUSY 0xD60D00833 834#endif /* ASIC_REG_NIC2_QM0_REGS_H_ */835