835 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_NIC2_QM1_REGS_H_14#define ASIC_REG_NIC2_QM1_REGS_H_15 16/*17 *****************************************18 * NIC2_QM1 (Prototype: QMAN)19 *****************************************20 */21 22#define mmNIC2_QM1_GLBL_CFG0 0xD6200023 24#define mmNIC2_QM1_GLBL_CFG1 0xD6200425 26#define mmNIC2_QM1_GLBL_PROT 0xD6200827 28#define mmNIC2_QM1_GLBL_ERR_CFG 0xD6200C29 30#define mmNIC2_QM1_GLBL_SECURE_PROPS_0 0xD6201031 32#define mmNIC2_QM1_GLBL_SECURE_PROPS_1 0xD6201433 34#define mmNIC2_QM1_GLBL_SECURE_PROPS_2 0xD6201835 36#define mmNIC2_QM1_GLBL_SECURE_PROPS_3 0xD6201C37 38#define mmNIC2_QM1_GLBL_SECURE_PROPS_4 0xD6202039 40#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0 0xD6202441 42#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1 0xD6202843 44#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2 0xD6202C45 46#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3 0xD6203047 48#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4 0xD6203449 50#define mmNIC2_QM1_GLBL_STS0 0xD6203851 52#define mmNIC2_QM1_GLBL_STS1_0 0xD6204053 54#define mmNIC2_QM1_GLBL_STS1_1 0xD6204455 56#define mmNIC2_QM1_GLBL_STS1_2 0xD6204857 58#define mmNIC2_QM1_GLBL_STS1_3 0xD6204C59 60#define mmNIC2_QM1_GLBL_STS1_4 0xD6205061 62#define mmNIC2_QM1_GLBL_MSG_EN_0 0xD6205463 64#define mmNIC2_QM1_GLBL_MSG_EN_1 0xD6205865 66#define mmNIC2_QM1_GLBL_MSG_EN_2 0xD6205C67 68#define mmNIC2_QM1_GLBL_MSG_EN_3 0xD6206069 70#define mmNIC2_QM1_GLBL_MSG_EN_4 0xD6206871 72#define mmNIC2_QM1_PQ_BASE_LO_0 0xD6207073 74#define mmNIC2_QM1_PQ_BASE_LO_1 0xD6207475 76#define mmNIC2_QM1_PQ_BASE_LO_2 0xD6207877 78#define mmNIC2_QM1_PQ_BASE_LO_3 0xD6207C79 80#define mmNIC2_QM1_PQ_BASE_HI_0 0xD6208081 82#define mmNIC2_QM1_PQ_BASE_HI_1 0xD6208483 84#define mmNIC2_QM1_PQ_BASE_HI_2 0xD6208885 86#define mmNIC2_QM1_PQ_BASE_HI_3 0xD6208C87 88#define mmNIC2_QM1_PQ_SIZE_0 0xD6209089 90#define mmNIC2_QM1_PQ_SIZE_1 0xD6209491 92#define mmNIC2_QM1_PQ_SIZE_2 0xD6209893 94#define mmNIC2_QM1_PQ_SIZE_3 0xD6209C95 96#define mmNIC2_QM1_PQ_PI_0 0xD620A097 98#define mmNIC2_QM1_PQ_PI_1 0xD620A499 100#define mmNIC2_QM1_PQ_PI_2 0xD620A8101 102#define mmNIC2_QM1_PQ_PI_3 0xD620AC103 104#define mmNIC2_QM1_PQ_CI_0 0xD620B0105 106#define mmNIC2_QM1_PQ_CI_1 0xD620B4107 108#define mmNIC2_QM1_PQ_CI_2 0xD620B8109 110#define mmNIC2_QM1_PQ_CI_3 0xD620BC111 112#define mmNIC2_QM1_PQ_CFG0_0 0xD620C0113 114#define mmNIC2_QM1_PQ_CFG0_1 0xD620C4115 116#define mmNIC2_QM1_PQ_CFG0_2 0xD620C8117 118#define mmNIC2_QM1_PQ_CFG0_3 0xD620CC119 120#define mmNIC2_QM1_PQ_CFG1_0 0xD620D0121 122#define mmNIC2_QM1_PQ_CFG1_1 0xD620D4123 124#define mmNIC2_QM1_PQ_CFG1_2 0xD620D8125 126#define mmNIC2_QM1_PQ_CFG1_3 0xD620DC127 128#define mmNIC2_QM1_PQ_ARUSER_31_11_0 0xD620E0129 130#define mmNIC2_QM1_PQ_ARUSER_31_11_1 0xD620E4131 132#define mmNIC2_QM1_PQ_ARUSER_31_11_2 0xD620E8133 134#define mmNIC2_QM1_PQ_ARUSER_31_11_3 0xD620EC135 136#define mmNIC2_QM1_PQ_STS0_0 0xD620F0137 138#define mmNIC2_QM1_PQ_STS0_1 0xD620F4139 140#define mmNIC2_QM1_PQ_STS0_2 0xD620F8141 142#define mmNIC2_QM1_PQ_STS0_3 0xD620FC143 144#define mmNIC2_QM1_PQ_STS1_0 0xD62100145 146#define mmNIC2_QM1_PQ_STS1_1 0xD62104147 148#define mmNIC2_QM1_PQ_STS1_2 0xD62108149 150#define mmNIC2_QM1_PQ_STS1_3 0xD6210C151 152#define mmNIC2_QM1_CQ_CFG0_0 0xD62110153 154#define mmNIC2_QM1_CQ_CFG0_1 0xD62114155 156#define mmNIC2_QM1_CQ_CFG0_2 0xD62118157 158#define mmNIC2_QM1_CQ_CFG0_3 0xD6211C159 160#define mmNIC2_QM1_CQ_CFG0_4 0xD62120161 162#define mmNIC2_QM1_CQ_CFG1_0 0xD62124163 164#define mmNIC2_QM1_CQ_CFG1_1 0xD62128165 166#define mmNIC2_QM1_CQ_CFG1_2 0xD6212C167 168#define mmNIC2_QM1_CQ_CFG1_3 0xD62130169 170#define mmNIC2_QM1_CQ_CFG1_4 0xD62134171 172#define mmNIC2_QM1_CQ_ARUSER_31_11_0 0xD62138173 174#define mmNIC2_QM1_CQ_ARUSER_31_11_1 0xD6213C175 176#define mmNIC2_QM1_CQ_ARUSER_31_11_2 0xD62140177 178#define mmNIC2_QM1_CQ_ARUSER_31_11_3 0xD62144179 180#define mmNIC2_QM1_CQ_ARUSER_31_11_4 0xD62148181 182#define mmNIC2_QM1_CQ_STS0_0 0xD6214C183 184#define mmNIC2_QM1_CQ_STS0_1 0xD62150185 186#define mmNIC2_QM1_CQ_STS0_2 0xD62154187 188#define mmNIC2_QM1_CQ_STS0_3 0xD62158189 190#define mmNIC2_QM1_CQ_STS0_4 0xD6215C191 192#define mmNIC2_QM1_CQ_STS1_0 0xD62160193 194#define mmNIC2_QM1_CQ_STS1_1 0xD62164195 196#define mmNIC2_QM1_CQ_STS1_2 0xD62168197 198#define mmNIC2_QM1_CQ_STS1_3 0xD6216C199 200#define mmNIC2_QM1_CQ_STS1_4 0xD62170201 202#define mmNIC2_QM1_CQ_PTR_LO_0 0xD62174203 204#define mmNIC2_QM1_CQ_PTR_HI_0 0xD62178205 206#define mmNIC2_QM1_CQ_TSIZE_0 0xD6217C207 208#define mmNIC2_QM1_CQ_CTL_0 0xD62180209 210#define mmNIC2_QM1_CQ_PTR_LO_1 0xD62184211 212#define mmNIC2_QM1_CQ_PTR_HI_1 0xD62188213 214#define mmNIC2_QM1_CQ_TSIZE_1 0xD6218C215 216#define mmNIC2_QM1_CQ_CTL_1 0xD62190217 218#define mmNIC2_QM1_CQ_PTR_LO_2 0xD62194219 220#define mmNIC2_QM1_CQ_PTR_HI_2 0xD62198221 222#define mmNIC2_QM1_CQ_TSIZE_2 0xD6219C223 224#define mmNIC2_QM1_CQ_CTL_2 0xD621A0225 226#define mmNIC2_QM1_CQ_PTR_LO_3 0xD621A4227 228#define mmNIC2_QM1_CQ_PTR_HI_3 0xD621A8229 230#define mmNIC2_QM1_CQ_TSIZE_3 0xD621AC231 232#define mmNIC2_QM1_CQ_CTL_3 0xD621B0233 234#define mmNIC2_QM1_CQ_PTR_LO_4 0xD621B4235 236#define mmNIC2_QM1_CQ_PTR_HI_4 0xD621B8237 238#define mmNIC2_QM1_CQ_TSIZE_4 0xD621BC239 240#define mmNIC2_QM1_CQ_CTL_4 0xD621C0241 242#define mmNIC2_QM1_CQ_PTR_LO_STS_0 0xD621C4243 244#define mmNIC2_QM1_CQ_PTR_LO_STS_1 0xD621C8245 246#define mmNIC2_QM1_CQ_PTR_LO_STS_2 0xD621CC247 248#define mmNIC2_QM1_CQ_PTR_LO_STS_3 0xD621D0249 250#define mmNIC2_QM1_CQ_PTR_LO_STS_4 0xD621D4251 252#define mmNIC2_QM1_CQ_PTR_HI_STS_0 0xD621D8253 254#define mmNIC2_QM1_CQ_PTR_HI_STS_1 0xD621DC255 256#define mmNIC2_QM1_CQ_PTR_HI_STS_2 0xD621E0257 258#define mmNIC2_QM1_CQ_PTR_HI_STS_3 0xD621E4259 260#define mmNIC2_QM1_CQ_PTR_HI_STS_4 0xD621E8261 262#define mmNIC2_QM1_CQ_TSIZE_STS_0 0xD621EC263 264#define mmNIC2_QM1_CQ_TSIZE_STS_1 0xD621F0265 266#define mmNIC2_QM1_CQ_TSIZE_STS_2 0xD621F4267 268#define mmNIC2_QM1_CQ_TSIZE_STS_3 0xD621F8269 270#define mmNIC2_QM1_CQ_TSIZE_STS_4 0xD621FC271 272#define mmNIC2_QM1_CQ_CTL_STS_0 0xD62200273 274#define mmNIC2_QM1_CQ_CTL_STS_1 0xD62204275 276#define mmNIC2_QM1_CQ_CTL_STS_2 0xD62208277 278#define mmNIC2_QM1_CQ_CTL_STS_3 0xD6220C279 280#define mmNIC2_QM1_CQ_CTL_STS_4 0xD62210281 282#define mmNIC2_QM1_CQ_IFIFO_CNT_0 0xD62214283 284#define mmNIC2_QM1_CQ_IFIFO_CNT_1 0xD62218285 286#define mmNIC2_QM1_CQ_IFIFO_CNT_2 0xD6221C287 288#define mmNIC2_QM1_CQ_IFIFO_CNT_3 0xD62220289 290#define mmNIC2_QM1_CQ_IFIFO_CNT_4 0xD62224291 292#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_0 0xD62228293 294#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_1 0xD6222C295 296#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_2 0xD62230297 298#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_3 0xD62234299 300#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_4 0xD62238301 302#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_0 0xD6223C303 304#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_1 0xD62240305 306#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_2 0xD62244307 308#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_3 0xD62248309 310#define mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_4 0xD6224C311 312#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_0 0xD62250313 314#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_1 0xD62254315 316#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_2 0xD62258317 318#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_3 0xD6225C319 320#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_4 0xD62260321 322#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_0 0xD62264323 324#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_1 0xD62268325 326#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_2 0xD6226C327 328#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_3 0xD62270329 330#define mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_4 0xD62274331 332#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_0 0xD62278333 334#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_1 0xD6227C335 336#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 0xD62280337 338#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_3 0xD62284339 340#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_4 0xD62288341 342#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_0 0xD6228C343 344#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_1 0xD62290345 346#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_2 0xD62294347 348#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_3 0xD62298349 350#define mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_4 0xD6229C351 352#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_0 0xD622A0353 354#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_1 0xD622A4355 356#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_2 0xD622A8357 358#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_3 0xD622AC359 360#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_4 0xD622B0361 362#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_0 0xD622B4363 364#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_1 0xD622B8365 366#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_2 0xD622BC367 368#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_3 0xD622C0369 370#define mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_4 0xD622C4371 372#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_0 0xD622C8373 374#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_1 0xD622CC375 376#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_2 0xD622D0377 378#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_3 0xD622D4379 380#define mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_4 0xD622D8381 382#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD622E0383 384#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD622E4385 386#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD622E8387 388#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD622EC389 390#define mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD622F0391 392#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD622F4393 394#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD622F8395 396#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD622FC397 398#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD62300399 400#define mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD62304401 402#define mmNIC2_QM1_CP_FENCE0_RDATA_0 0xD62308403 404#define mmNIC2_QM1_CP_FENCE0_RDATA_1 0xD6230C405 406#define mmNIC2_QM1_CP_FENCE0_RDATA_2 0xD62310407 408#define mmNIC2_QM1_CP_FENCE0_RDATA_3 0xD62314409 410#define mmNIC2_QM1_CP_FENCE0_RDATA_4 0xD62318411 412#define mmNIC2_QM1_CP_FENCE1_RDATA_0 0xD6231C413 414#define mmNIC2_QM1_CP_FENCE1_RDATA_1 0xD62320415 416#define mmNIC2_QM1_CP_FENCE1_RDATA_2 0xD62324417 418#define mmNIC2_QM1_CP_FENCE1_RDATA_3 0xD62328419 420#define mmNIC2_QM1_CP_FENCE1_RDATA_4 0xD6232C421 422#define mmNIC2_QM1_CP_FENCE2_RDATA_0 0xD62330423 424#define mmNIC2_QM1_CP_FENCE2_RDATA_1 0xD62334425 426#define mmNIC2_QM1_CP_FENCE2_RDATA_2 0xD62338427 428#define mmNIC2_QM1_CP_FENCE2_RDATA_3 0xD6233C429 430#define mmNIC2_QM1_CP_FENCE2_RDATA_4 0xD62340431 432#define mmNIC2_QM1_CP_FENCE3_RDATA_0 0xD62344433 434#define mmNIC2_QM1_CP_FENCE3_RDATA_1 0xD62348435 436#define mmNIC2_QM1_CP_FENCE3_RDATA_2 0xD6234C437 438#define mmNIC2_QM1_CP_FENCE3_RDATA_3 0xD62350439 440#define mmNIC2_QM1_CP_FENCE3_RDATA_4 0xD62354441 442#define mmNIC2_QM1_CP_FENCE0_CNT_0 0xD62358443 444#define mmNIC2_QM1_CP_FENCE0_CNT_1 0xD6235C445 446#define mmNIC2_QM1_CP_FENCE0_CNT_2 0xD62360447 448#define mmNIC2_QM1_CP_FENCE0_CNT_3 0xD62364449 450#define mmNIC2_QM1_CP_FENCE0_CNT_4 0xD62368451 452#define mmNIC2_QM1_CP_FENCE1_CNT_0 0xD6236C453 454#define mmNIC2_QM1_CP_FENCE1_CNT_1 0xD62370455 456#define mmNIC2_QM1_CP_FENCE1_CNT_2 0xD62374457 458#define mmNIC2_QM1_CP_FENCE1_CNT_3 0xD62378459 460#define mmNIC2_QM1_CP_FENCE1_CNT_4 0xD6237C461 462#define mmNIC2_QM1_CP_FENCE2_CNT_0 0xD62380463 464#define mmNIC2_QM1_CP_FENCE2_CNT_1 0xD62384465 466#define mmNIC2_QM1_CP_FENCE2_CNT_2 0xD62388467 468#define mmNIC2_QM1_CP_FENCE2_CNT_3 0xD6238C469 470#define mmNIC2_QM1_CP_FENCE2_CNT_4 0xD62390471 472#define mmNIC2_QM1_CP_FENCE3_CNT_0 0xD62394473 474#define mmNIC2_QM1_CP_FENCE3_CNT_1 0xD62398475 476#define mmNIC2_QM1_CP_FENCE3_CNT_2 0xD6239C477 478#define mmNIC2_QM1_CP_FENCE3_CNT_3 0xD623A0479 480#define mmNIC2_QM1_CP_FENCE3_CNT_4 0xD623A4481 482#define mmNIC2_QM1_CP_STS_0 0xD623A8483 484#define mmNIC2_QM1_CP_STS_1 0xD623AC485 486#define mmNIC2_QM1_CP_STS_2 0xD623B0487 488#define mmNIC2_QM1_CP_STS_3 0xD623B4489 490#define mmNIC2_QM1_CP_STS_4 0xD623B8491 492#define mmNIC2_QM1_CP_CURRENT_INST_LO_0 0xD623BC493 494#define mmNIC2_QM1_CP_CURRENT_INST_LO_1 0xD623C0495 496#define mmNIC2_QM1_CP_CURRENT_INST_LO_2 0xD623C4497 498#define mmNIC2_QM1_CP_CURRENT_INST_LO_3 0xD623C8499 500#define mmNIC2_QM1_CP_CURRENT_INST_LO_4 0xD623CC501 502#define mmNIC2_QM1_CP_CURRENT_INST_HI_0 0xD623D0503 504#define mmNIC2_QM1_CP_CURRENT_INST_HI_1 0xD623D4505 506#define mmNIC2_QM1_CP_CURRENT_INST_HI_2 0xD623D8507 508#define mmNIC2_QM1_CP_CURRENT_INST_HI_3 0xD623DC509 510#define mmNIC2_QM1_CP_CURRENT_INST_HI_4 0xD623E0511 512#define mmNIC2_QM1_CP_BARRIER_CFG_0 0xD623F4513 514#define mmNIC2_QM1_CP_BARRIER_CFG_1 0xD623F8515 516#define mmNIC2_QM1_CP_BARRIER_CFG_2 0xD623FC517 518#define mmNIC2_QM1_CP_BARRIER_CFG_3 0xD62400519 520#define mmNIC2_QM1_CP_BARRIER_CFG_4 0xD62404521 522#define mmNIC2_QM1_CP_DBG_0_0 0xD62408523 524#define mmNIC2_QM1_CP_DBG_0_1 0xD6240C525 526#define mmNIC2_QM1_CP_DBG_0_2 0xD62410527 528#define mmNIC2_QM1_CP_DBG_0_3 0xD62414529 530#define mmNIC2_QM1_CP_DBG_0_4 0xD62418531 532#define mmNIC2_QM1_CP_ARUSER_31_11_0 0xD6241C533 534#define mmNIC2_QM1_CP_ARUSER_31_11_1 0xD62420535 536#define mmNIC2_QM1_CP_ARUSER_31_11_2 0xD62424537 538#define mmNIC2_QM1_CP_ARUSER_31_11_3 0xD62428539 540#define mmNIC2_QM1_CP_ARUSER_31_11_4 0xD6242C541 542#define mmNIC2_QM1_CP_AWUSER_31_11_0 0xD62430543 544#define mmNIC2_QM1_CP_AWUSER_31_11_1 0xD62434545 546#define mmNIC2_QM1_CP_AWUSER_31_11_2 0xD62438547 548#define mmNIC2_QM1_CP_AWUSER_31_11_3 0xD6243C549 550#define mmNIC2_QM1_CP_AWUSER_31_11_4 0xD62440551 552#define mmNIC2_QM1_ARB_CFG_0 0xD62A00553 554#define mmNIC2_QM1_ARB_CHOISE_Q_PUSH 0xD62A04555 556#define mmNIC2_QM1_ARB_WRR_WEIGHT_0 0xD62A08557 558#define mmNIC2_QM1_ARB_WRR_WEIGHT_1 0xD62A0C559 560#define mmNIC2_QM1_ARB_WRR_WEIGHT_2 0xD62A10561 562#define mmNIC2_QM1_ARB_WRR_WEIGHT_3 0xD62A14563 564#define mmNIC2_QM1_ARB_CFG_1 0xD62A18565 566#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_0 0xD62A20567 568#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_1 0xD62A24569 570#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_2 0xD62A28571 572#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_3 0xD62A2C573 574#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_4 0xD62A30575 576#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_5 0xD62A34577 578#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_6 0xD62A38579 580#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_7 0xD62A3C581 582#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_8 0xD62A40583 584#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_9 0xD62A44585 586#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_10 0xD62A48587 588#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_11 0xD62A4C589 590#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_12 0xD62A50591 592#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_13 0xD62A54593 594#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_14 0xD62A58595 596#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_15 0xD62A5C597 598#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_16 0xD62A60599 600#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_17 0xD62A64601 602#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_18 0xD62A68603 604#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_19 0xD62A6C605 606#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_20 0xD62A70607 608#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_21 0xD62A74609 610#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_22 0xD62A78611 612#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_23 0xD62A7C613 614#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 0xD62A80615 616#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_25 0xD62A84617 618#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_26 0xD62A88619 620#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_27 0xD62A8C621 622#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_28 0xD62A90623 624#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_29 0xD62A94625 626#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_30 0xD62A98627 628#define mmNIC2_QM1_ARB_MST_AVAIL_CRED_31 0xD62A9C629 630#define mmNIC2_QM1_ARB_MST_CRED_INC 0xD62AA0631 632#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xD62AA4633 634#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xD62AA8635 636#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xD62AAC637 638#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xD62AB0639 640#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xD62AB4641 642#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xD62AB8643 644#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xD62ABC645 646#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xD62AC0647 648#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xD62AC4649 650#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xD62AC8651 652#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xD62ACC653 654#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xD62AD0655 656#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xD62AD4657 658#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xD62AD8659 660#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xD62ADC661 662#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xD62AE0663 664#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xD62AE4665 666#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xD62AE8667 668#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xD62AEC669 670#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xD62AF0671 672#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xD62AF4673 674#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xD62AF8675 676#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xD62AFC677 678#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xD62B00679 680#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xD62B04681 682#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xD62B08683 684#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xD62B0C685 686#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xD62B10687 688#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xD62B14689 690#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xD62B18691 692#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xD62B1C693 694#define mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xD62B20695 696#define mmNIC2_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xD62B28697 698#define mmNIC2_QM1_ARB_MST_SLAVE_EN 0xD62B2C699 700#define mmNIC2_QM1_ARB_MST_QUIET_PER 0xD62B34701 702#define mmNIC2_QM1_ARB_SLV_CHOISE_WDT 0xD62B38703 704#define mmNIC2_QM1_ARB_SLV_ID 0xD62B3C705 706#define mmNIC2_QM1_ARB_MSG_MAX_INFLIGHT 0xD62B44707 708#define mmNIC2_QM1_ARB_MSG_AWUSER_31_11 0xD62B48709 710#define mmNIC2_QM1_ARB_MSG_AWUSER_SEC_PROP 0xD62B4C711 712#define mmNIC2_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xD62B50713 714#define mmNIC2_QM1_ARB_BASE_LO 0xD62B54715 716#define mmNIC2_QM1_ARB_BASE_HI 0xD62B58717 718#define mmNIC2_QM1_ARB_STATE_STS 0xD62B80719 720#define mmNIC2_QM1_ARB_CHOISE_FULLNESS_STS 0xD62B84721 722#define mmNIC2_QM1_ARB_MSG_STS 0xD62B88723 724#define mmNIC2_QM1_ARB_SLV_CHOISE_Q_HEAD 0xD62B8C725 726#define mmNIC2_QM1_ARB_ERR_CAUSE 0xD62B9C727 728#define mmNIC2_QM1_ARB_ERR_MSG_EN 0xD62BA0729 730#define mmNIC2_QM1_ARB_ERR_STS_DRP 0xD62BA8731 732#define mmNIC2_QM1_ARB_MST_CRED_STS_0 0xD62BB0733 734#define mmNIC2_QM1_ARB_MST_CRED_STS_1 0xD62BB4735 736#define mmNIC2_QM1_ARB_MST_CRED_STS_2 0xD62BB8737 738#define mmNIC2_QM1_ARB_MST_CRED_STS_3 0xD62BBC739 740#define mmNIC2_QM1_ARB_MST_CRED_STS_4 0xD62BC0741 742#define mmNIC2_QM1_ARB_MST_CRED_STS_5 0xD62BC4743 744#define mmNIC2_QM1_ARB_MST_CRED_STS_6 0xD62BC8745 746#define mmNIC2_QM1_ARB_MST_CRED_STS_7 0xD62BCC747 748#define mmNIC2_QM1_ARB_MST_CRED_STS_8 0xD62BD0749 750#define mmNIC2_QM1_ARB_MST_CRED_STS_9 0xD62BD4751 752#define mmNIC2_QM1_ARB_MST_CRED_STS_10 0xD62BD8753 754#define mmNIC2_QM1_ARB_MST_CRED_STS_11 0xD62BDC755 756#define mmNIC2_QM1_ARB_MST_CRED_STS_12 0xD62BE0757 758#define mmNIC2_QM1_ARB_MST_CRED_STS_13 0xD62BE4759 760#define mmNIC2_QM1_ARB_MST_CRED_STS_14 0xD62BE8761 762#define mmNIC2_QM1_ARB_MST_CRED_STS_15 0xD62BEC763 764#define mmNIC2_QM1_ARB_MST_CRED_STS_16 0xD62BF0765 766#define mmNIC2_QM1_ARB_MST_CRED_STS_17 0xD62BF4767 768#define mmNIC2_QM1_ARB_MST_CRED_STS_18 0xD62BF8769 770#define mmNIC2_QM1_ARB_MST_CRED_STS_19 0xD62BFC771 772#define mmNIC2_QM1_ARB_MST_CRED_STS_20 0xD62C00773 774#define mmNIC2_QM1_ARB_MST_CRED_STS_21 0xD62C04775 776#define mmNIC2_QM1_ARB_MST_CRED_STS_22 0xD62C08777 778#define mmNIC2_QM1_ARB_MST_CRED_STS_23 0xD62C0C779 780#define mmNIC2_QM1_ARB_MST_CRED_STS_24 0xD62C10781 782#define mmNIC2_QM1_ARB_MST_CRED_STS_25 0xD62C14783 784#define mmNIC2_QM1_ARB_MST_CRED_STS_26 0xD62C18785 786#define mmNIC2_QM1_ARB_MST_CRED_STS_27 0xD62C1C787 788#define mmNIC2_QM1_ARB_MST_CRED_STS_28 0xD62C20789 790#define mmNIC2_QM1_ARB_MST_CRED_STS_29 0xD62C24791 792#define mmNIC2_QM1_ARB_MST_CRED_STS_30 0xD62C28793 794#define mmNIC2_QM1_ARB_MST_CRED_STS_31 0xD62C2C795 796#define mmNIC2_QM1_CGM_CFG 0xD62C70797 798#define mmNIC2_QM1_CGM_STS 0xD62C74799 800#define mmNIC2_QM1_CGM_CFG1 0xD62C78801 802#define mmNIC2_QM1_LOCAL_RANGE_BASE 0xD62C80803 804#define mmNIC2_QM1_LOCAL_RANGE_SIZE 0xD62C84805 806#define mmNIC2_QM1_CSMR_STRICT_PRIO_CFG 0xD62C90807 808#define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_1 0xD62C94809 810#define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_0 0xD62C98811 812#define mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_1 0xD62C9C813 814#define mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_0 0xD62CA0815 816#define mmNIC2_QM1_GLBL_AXCACHE 0xD62CA4817 818#define mmNIC2_QM1_IND_GW_APB_CFG 0xD62CB0819 820#define mmNIC2_QM1_IND_GW_APB_WDATA 0xD62CB4821 822#define mmNIC2_QM1_IND_GW_APB_RDATA 0xD62CB8823 824#define mmNIC2_QM1_IND_GW_APB_STATUS 0xD62CBC825 826#define mmNIC2_QM1_GLBL_ERR_ADDR_LO 0xD62CD0827 828#define mmNIC2_QM1_GLBL_ERR_ADDR_HI 0xD62CD4829 830#define mmNIC2_QM1_GLBL_ERR_WDATA 0xD62CD8831 832#define mmNIC2_QM1_GLBL_MEM_INIT_BUSY 0xD62D00833 834#endif /* ASIC_REG_NIC2_QM1_REGS_H_ */835