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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 **       DO NOT EDIT BELOW        **11 ************************************/12 13#ifndef ASIC_REG_STLB_REGS_H_14#define ASIC_REG_STLB_REGS_H_15 16/*17 *****************************************18 *   STLB (Prototype: STLB)19 *****************************************20 */21 22#define mmSTLB_CACHE_INV                                             0xC1201023 24#define mmSTLB_CACHE_INV_BASE_39_8                                   0xC1201425 26#define mmSTLB_CACHE_INV_BASE_49_40                                  0xC1201827 28#define mmSTLB_STLB_FEATURE_EN                                       0xC1201C29 30#define mmSTLB_STLB_AXI_CACHE                                        0xC1202031 32#define mmSTLB_HOP_CONFIGURATION                                     0xC1202433 34#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32                           0xC1202835 36#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0                            0xC1202C37 38#define mmSTLB_LINK_LIST                                             0xC1203039 40#define mmSTLB_INV_ALL_START                                         0xC1203441 42#define mmSTLB_INV_ALL_SET                                           0xC1203843 44#define mmSTLB_INV_PS                                                0xC1203C45 46#define mmSTLB_INV_CONSUMER_INDEX                                    0xC1204047 48#define mmSTLB_INV_HIT_COUNT                                         0xC1204449 50#define mmSTLB_INV_SET                                               0xC1204851 52#define mmSTLB_SRAM_INIT                                             0xC1204C53 54#define mmSTLB_MEM_CACHE_INVALIDATION                                0xC1205055 56#define mmSTLB_MEM_CACHE_INV_STATUS                                  0xC1205457 58#define mmSTLB_MEM_CACHE_BASE_38_7                                   0xC1205859 60#define mmSTLB_MEM_CACHE_BASE_49_39                                  0xC1205C61 62#define mmSTLB_MEM_CACHE_CONFIG                                      0xC1206063 64#define mmSTLB_SET_THRESHOLD_HOP4                                    0xC1206465 66#define mmSTLB_SET_THRESHOLD_HOP3                                    0xC1206867 68#define mmSTLB_SET_THRESHOLD_HOP2                                    0xC1206C69 70#define mmSTLB_SET_THRESHOLD_HOP1                                    0xC1207071 72#define mmSTLB_SET_THRESHOLD_HOP0                                    0xC1207473 74#define mmSTLB_MULTI_HIT_INTERRUPT_CLR                               0xC1207875 76#define mmSTLB_MULTI_HIT_INTERRUPT_MASK                              0xC1207C77 78#define mmSTLB_MEM_L0_CACHE_CFG                                      0xC1208079 80#define mmSTLB_MEM_READ_ARPROT                                       0xC1208481 82#endif /* ASIC_REG_STLB_REGS_H_ */83