2579 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC0_CFG_MASKS_H_14#define ASIC_REG_TPC0_CFG_MASKS_H_15 16/*17 *****************************************18 * TPC0_CFG (Prototype: TPC)19 *****************************************20 */21 22/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */23#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 024#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF25 26/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */27#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 028#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF29 30/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */31#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 032#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF33 34/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */35#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 036#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x737#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 838#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F0039#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 1640#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x7000041#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 1942#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x8000043#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 2044#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x10000045#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 2146#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x60000047 48/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */49#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 050#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF51 52/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */53#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 054#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF55 56/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */57#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 058#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF59 60/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */61#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 062#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF63 64/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */65#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 066#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF67 68/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */69#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 070#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF71 72/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */73#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 074#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF75 76/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */77#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 078#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF79 80/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */81#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 082#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF83 84/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */85#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 086#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF87 88/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */89#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 090#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF91 92/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */93#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 094#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF95 96/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */97#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 098#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF99 100/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */101#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0102#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7103#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8104#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00105#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16106#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000107#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19108#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000109#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20110#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000111#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21112#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000113 114/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */115#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0116#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF117 118/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */119#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0120#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF121 122/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */123#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0124#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF125 126/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */127#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0128#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF129 130/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */131#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0132#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF133 134/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */135#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0136#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF137 138/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */139#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0140#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF141 142/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */143#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0144#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF145 146/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */147#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0148#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF149 150/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */151#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0152#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF153 154/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */155#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0156#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF157 158/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */159#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0160#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF161 162/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */163#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0164#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF165 166/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */167#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0168#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7169#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8170#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00171#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16172#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000173#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19174#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000175#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20176#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000177#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21178#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000179 180/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */181#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0182#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF183 184/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */185#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0186#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF187 188/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */189#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0190#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF191 192/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */193#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0194#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF195 196/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */197#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0198#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF199 200/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */201#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0202#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF203 204/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */205#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0206#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF207 208/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */209#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0210#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF211 212/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */213#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0214#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF215 216/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */217#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0218#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF219 220/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */221#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0222#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF223 224/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */225#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0226#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF227 228/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */229#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0230#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF231 232/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */233#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0234#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7235#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8236#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00237#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16238#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000239#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19240#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000241#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20242#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000243#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21244#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000245 246/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */247#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0248#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF249 250/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */251#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0252#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF253 254/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */255#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0256#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF257 258/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */259#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0260#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF261 262/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */263#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0264#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF265 266/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */267#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0268#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF269 270/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */271#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0272#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF273 274/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */275#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0276#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF277 278/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */279#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0280#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF281 282/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */283#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0284#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF285 286/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */287#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0288#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF289 290/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */291#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0292#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF293 294/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */295#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0296#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF297 298/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */299#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0300#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7301#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8302#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00303#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16304#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000305#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19306#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000307#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20308#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000309#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21310#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000311 312/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */313#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0314#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF315 316/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */317#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0318#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF319 320/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */321#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0322#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF323 324/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */325#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0326#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF327 328/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */329#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0330#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF331 332/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */333#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0334#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF335 336/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */337#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0338#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF339 340/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */341#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0342#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF343 344/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */345#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0346#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF347 348/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */349#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0350#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF351 352/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */353#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0354#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF355 356/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */357#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0358#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF359 360/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */361#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0362#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF363 364/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */365#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0366#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7367#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8368#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00369#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16370#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000371#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19372#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000373#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20374#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000375#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21376#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000377 378/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */379#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0380#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF381 382/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */383#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0384#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF385 386/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */387#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0388#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF389 390/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */391#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0392#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF393 394/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */395#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0396#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF397 398/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */399#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0400#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF401 402/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */403#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0404#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF405 406/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */407#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0408#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF409 410/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */411#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0412#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF413 414/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */415#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0416#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF417 418/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */419#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0420#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF421 422/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */423#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0424#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF425 426/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */427#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0428#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF429 430/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */431#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0432#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7433#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8434#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00435#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16436#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000437#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19438#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000439#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20440#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000441#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21442#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000443 444/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */445#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0446#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF447 448/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */449#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0450#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF451 452/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */453#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0454#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF455 456/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */457#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0458#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF459 460/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */461#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0462#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF463 464/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */465#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0466#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF467 468/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */469#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0470#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF471 472/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */473#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0474#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF475 476/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */477#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0478#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF479 480/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */481#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0482#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF483 484/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */485#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0486#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF487 488/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */489#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0490#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF491 492/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */493#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0494#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF495 496/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */497#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0498#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7499#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8500#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00501#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16502#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000503#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19504#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000505#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20506#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000507#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21508#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000509 510/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */511#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0512#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF513 514/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */515#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0516#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF517 518/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */519#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0520#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF521 522/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */523#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0524#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF525 526/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */527#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0528#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF529 530/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */531#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0532#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF533 534/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */535#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0536#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF537 538/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */539#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0540#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF541 542/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */543#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0544#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF545 546/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */547#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0548#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF549 550/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */551#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0552#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF553 554/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */555#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0556#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF557 558/* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */559#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT 0560#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF561 562/* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */563#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0564#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7565#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8566#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00567#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16568#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000569#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19570#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000571#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20572#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000573#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21574#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000575 576/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */577#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT 0578#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF579 580/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */581#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0582#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF583 584/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */585#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT 0586#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF587 588/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */589#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0590#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF591 592/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */593#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT 0594#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF595 596/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */597#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0598#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF599 600/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */601#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT 0602#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF603 604/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */605#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0606#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF607 608/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */609#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT 0610#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF611 612/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */613#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0614#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF615 616/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */617#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0618#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF619 620/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */621#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0622#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF623 624/* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */625#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT 0626#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF627 628/* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */629#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0630#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7631#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8632#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00633#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16634#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000635#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19636#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000637#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20638#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000639#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21640#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000641 642/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */643#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT 0644#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF645 646/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */647#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0648#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF649 650/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */651#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT 0652#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF653 654/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */655#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0656#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF657 658/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */659#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT 0660#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF661 662/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */663#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0664#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF665 666/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */667#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT 0668#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF669 670/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */671#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0672#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF673 674/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */675#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT 0676#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF677 678/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */679#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0680#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF681 682/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */683#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0684#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF685 686/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */687#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0688#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF689 690/* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */691#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT 0692#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF693 694/* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */695#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0696#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7697#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8698#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00699#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16700#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000701#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19702#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000703#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20704#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000705#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21706#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000707 708/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */709#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT 0710#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF711 712/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */713#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0714#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF715 716/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */717#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT 0718#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF719 720/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */721#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0722#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF723 724/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */725#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT 0726#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF727 728/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */729#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0730#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF731 732/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */733#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT 0734#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF735 736/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */737#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0738#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF739 740/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */741#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT 0742#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF743 744/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */745#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0746#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF747 748/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */749#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0750#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF751 752/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */753#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0754#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF755 756/* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */757#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT 0758#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF759 760/* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */761#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0762#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7763#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8764#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00765#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16766#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000767#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19768#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000769#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20770#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000771#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21772#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000773 774/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */775#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT 0776#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF777 778/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */779#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0780#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF781 782/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */783#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT 0784#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF785 786/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */787#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0788#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF789 790/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */791#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT 0792#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF793 794/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */795#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0796#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF797 798/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */799#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT 0800#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF801 802/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */803#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0804#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF805 806/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */807#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT 0808#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF809 810/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */811#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0812#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF813 814/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */815#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0816#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF817 818/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */819#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0820#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF821 822/* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */823#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT 0824#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF825 826/* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */827#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0828#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7829#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8830#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00831#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16832#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000833#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19834#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000835#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20836#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000837#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21838#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000839 840/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */841#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT 0842#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF843 844/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */845#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0846#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF847 848/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */849#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT 0850#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF851 852/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */853#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0854#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF855 856/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */857#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT 0858#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF859 860/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */861#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0862#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF863 864/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */865#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT 0866#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF867 868/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */869#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0870#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF871 872/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */873#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT 0874#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF875 876/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */877#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0878#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF879 880/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */881#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0882#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF883 884/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */885#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0886#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF887 888/* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */889#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT 0890#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF891 892/* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */893#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0894#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7895#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8896#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00897#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16898#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000899#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19900#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000901#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20902#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000903#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21904#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000905 906/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */907#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT 0908#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF909 910/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */911#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0912#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF913 914/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */915#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT 0916#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF917 918/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */919#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0920#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF921 922/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */923#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT 0924#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF925 926/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */927#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0928#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF929 930/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */931#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT 0932#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF933 934/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */935#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0936#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF937 938/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */939#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT 0940#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF941 942/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */943#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0944#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF945 946/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */947#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0948#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF949 950/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */951#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0952#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF953 954/* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */955#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT 0956#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF957 958/* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */959#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0960#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7961#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8962#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00963#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16964#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000965#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19966#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000967#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20968#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000969#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21970#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000971 972/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */973#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT 0974#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF975 976/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */977#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0978#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF979 980/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */981#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT 0982#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF983 984/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */985#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0986#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF987 988/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */989#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT 0990#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF991 992/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */993#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0994#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF995 996/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */997#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT 0998#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF999 1000/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */1001#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT 01002#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1003 1004/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */1005#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT 01006#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF1007 1008/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */1009#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT 01010#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1011 1012/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */1013#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 01014#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1015 1016/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */1017#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 01018#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1019 1020/* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */1021#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT 01022#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF1023 1024/* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */1025#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 01026#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x71027#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81028#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001029#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 161030#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x700001031#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 191032#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x800001033#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 201034#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001035#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 211036#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x6000001037 1038/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */1039#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT 01040#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF1041 1042/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */1043#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT 01044#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1045 1046/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */1047#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT 01048#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF1049 1050/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */1051#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT 01052#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1053 1054/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */1055#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT 01056#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF1057 1058/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */1059#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT 01060#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1061 1062/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */1063#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT 01064#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF1065 1066/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */1067#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT 01068#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1069 1070/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */1071#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT 01072#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF1073 1074/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */1075#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT 01076#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1077 1078/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */1079#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 01080#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF1081#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT 161082#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF00001083#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 291084#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE00000001085 1086/* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */1087#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT 01088#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF1089 1090/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */1091#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 01092#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF1093 1094/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */1095#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 01096#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF1097 1098/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */1099#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 01100#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF1101 1102/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */1103#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 01104#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF1105 1106/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */1107#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 01108#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF1109 1110/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */1111#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 01112#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF1113 1114/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */1115#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 01116#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF1117 1118/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */1119#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 01120#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF1121 1122/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */1123#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 01124#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF1125 1126/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */1127#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 01128#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF1129 1130/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */1131#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 01132#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF1133 1134/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */1135#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 01136#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF1137 1138/* TPC0_CFG_KERNEL_KERNEL_CONFIG */1139#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 01140#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x11141#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 11142#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x21143#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 21144#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC1145#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 81146#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF001147#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 161148#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF00001149 1150/* TPC0_CFG_KERNEL_KERNEL_ID */1151#define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT 01152#define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK 0xFFFF1153 1154/* TPC0_CFG_KERNEL_SRF */1155#define TPC0_CFG_KERNEL_SRF_V_SHIFT 01156#define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF1157 1158/* TPC0_CFG_ROUND_CSR */1159#define TPC0_CFG_ROUND_CSR_MODE_SHIFT 01160#define TPC0_CFG_ROUND_CSR_MODE_MASK 0x71161 1162/* TPC0_CFG_PROT */1163#define TPC0_CFG_PROT_AWPROT_SHIFT 01164#define TPC0_CFG_PROT_AWPROT_MASK 0x71165#define TPC0_CFG_PROT_ARPROT_SHIFT 31166#define TPC0_CFG_PROT_ARPROT_MASK 0x381167 1168/* TPC0_CFG_SEMAPHORE */1169#define TPC0_CFG_SEMAPHORE_V_SHIFT 01170#define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF1171 1172/* TPC0_CFG_VFLAGS */1173#define TPC0_CFG_VFLAGS_V_SHIFT 01174#define TPC0_CFG_VFLAGS_V_MASK 0xF1175 1176/* TPC0_CFG_SFLAGS */1177#define TPC0_CFG_SFLAGS_V_SHIFT 01178#define TPC0_CFG_SFLAGS_V_MASK 0xF1179 1180/* TPC0_CFG_LFSR_POLYNOM */1181#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 01182#define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF1183 1184/* TPC0_CFG_STATUS */1185#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 11186#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x21187#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 21188#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x41189#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 31190#define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x81191#define TPC0_CFG_STATUS_SB_EMPTY_SHIFT 51192#define TPC0_CFG_STATUS_SB_EMPTY_MASK 0x201193#define TPC0_CFG_STATUS_QM_IDLE_SHIFT 61194#define TPC0_CFG_STATUS_QM_IDLE_MASK 0x401195#define TPC0_CFG_STATUS_QM_RDY_SHIFT 71196#define TPC0_CFG_STATUS_QM_RDY_MASK 0x801197 1198/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */1199#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 01200#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF1201 1202/* TPC0_CFG_CFG_SUBTRACT_VALUE */1203#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 01204#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF1205 1206/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */1207#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 01208#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF1209 1210/* TPC0_CFG_TPC_CMD */1211#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 01212#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x11213#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 11214#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x21215#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 21216#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x41217#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 31218#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x81219#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 41220#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x101221#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 51222#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x201223#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 61224#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x401225 1226/* TPC0_CFG_TPC_EXECUTE */1227#define TPC0_CFG_TPC_EXECUTE_V_SHIFT 01228#define TPC0_CFG_TPC_EXECUTE_V_MASK 0x11229 1230/* TPC0_CFG_TPC_STALL */1231#define TPC0_CFG_TPC_STALL_V_SHIFT 01232#define TPC0_CFG_TPC_STALL_V_MASK 0x11233 1234/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */1235#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 01236#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF1237 1238/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */1239#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 01240#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF1241 1242/* TPC0_CFG_RD_RATE_LIMIT */1243#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 01244#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x11245#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 11246#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE1247#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 91248#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE001249 1250/* TPC0_CFG_WR_RATE_LIMIT */1251#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 01252#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x11253#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 11254#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE1255#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 91256#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE001257 1258/* TPC0_CFG_MSS_CONFIG */1259#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 01260#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF1261#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 41262#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF01263#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 81264#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x3001265#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 101266#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x4001267#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 111268#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x8001269 1270/* TPC0_CFG_TPC_INTR_CAUSE */1271#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 01272#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFF1273 1274/* TPC0_CFG_TPC_INTR_MASK */1275#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 01276#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFF1277 1278/* TPC0_CFG_WQ_CREDITS */1279#define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 01280#define TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF1281#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 41282#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x701283 1284/* TPC0_CFG_ARUSER_LO */1285#define TPC0_CFG_ARUSER_LO_V_SHIFT 01286#define TPC0_CFG_ARUSER_LO_V_MASK 0x7FF1287 1288/* TPC0_CFG_ARUSER_HI */1289#define TPC0_CFG_ARUSER_HI_V_SHIFT 111290#define TPC0_CFG_ARUSER_HI_V_MASK 0x18001291#define TPC0_CFG_ARUSER_HI_RSRV_SHIFT 131292#define TPC0_CFG_ARUSER_HI_RSRV_MASK 0xFFFFE0001293 1294/* TPC0_CFG_AWUSER_LO */1295#define TPC0_CFG_AWUSER_LO_V_SHIFT 01296#define TPC0_CFG_AWUSER_LO_V_MASK 0x7FF1297 1298/* TPC0_CFG_AWUSER_HI */1299#define TPC0_CFG_AWUSER_HI_V_SHIFT 111300#define TPC0_CFG_AWUSER_HI_V_MASK 0x18001301#define TPC0_CFG_AWUSER_HI_RSRV_SHIFT 131302#define TPC0_CFG_AWUSER_HI_RSRV_MASK 0xFFFFE0001303 1304/* TPC0_CFG_OPCODE_EXEC */1305#define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 01306#define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F1307#define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 71308#define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x801309#define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 81310#define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F001311#define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 151312#define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x80001313#define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 161314#define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F00001315#define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 231316#define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x8000001317#define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 241318#define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F0000001319#define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 311320#define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x800000001321 1322/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */1323#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 01324#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF1325 1326/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */1327#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 01328#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF1329 1330/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */1331#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 01332#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF1333 1334/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */1335#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 01336#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF1337 1338/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */1339#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 01340#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF1341 1342/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */1343#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 01344#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF1345 1346/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */1347#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 01348#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF1349 1350/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */1351#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 01352#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF1353 1354/* TPC0_CFG_TSB_CFG_MAX_SIZE */1355#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 01356#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF1357#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 161358#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF00001359 1360/* TPC0_CFG_TSB_CFG */1361#define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT 01362#define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK 0x11363#define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 11364#define TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE1365 1366/* TPC0_CFG_DBGMEM_ADD */1367#define TPC0_CFG_DBGMEM_ADD_V_SHIFT 01368#define TPC0_CFG_DBGMEM_ADD_V_MASK 0xFFFFFFFF1369 1370/* TPC0_CFG_DBGMEM_DATA_WR */1371#define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT 01372#define TPC0_CFG_DBGMEM_DATA_WR_V_MASK 0xFFFFFFFF1373 1374/* TPC0_CFG_DBGMEM_DATA_RD */1375#define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT 01376#define TPC0_CFG_DBGMEM_DATA_RD_V_MASK 0xFFFFFFFF1377 1378/* TPC0_CFG_DBGMEM_CTRL */1379#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT 01380#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK 0x11381 1382/* TPC0_CFG_DBGMEM_RC */1383#define TPC0_CFG_DBGMEM_RC_VALID_SHIFT 01384#define TPC0_CFG_DBGMEM_RC_VALID_MASK 0x11385 1386/* TPC0_CFG_TSB_INFLIGHT_CNTR */1387#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 01388#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF1389 1390/* TPC0_CFG_WQ_INFLIGHT_CNTR */1391#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 01392#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF1393#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 161394#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0xF00001395 1396/* TPC0_CFG_WQ_LBW_TOTAL_CNTR */1397#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 01398#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF1399 1400/* TPC0_CFG_WQ_HBW_TOTAL_CNTR */1401#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 01402#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF1403 1404/* TPC0_CFG_IRQ_OCCOUPY_CNTR */1405#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 01406#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF1407 1408/* TPC0_CFG_FUNC_MBIST_CNTRL */1409#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 01410#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x11411#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 11412#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x21413#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 21414#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x41415#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 161416#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF00001417 1418/* TPC0_CFG_FUNC_MBIST_PAT */1419#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 01420#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x31421#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 21422#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC1423#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 41424#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x301425#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 61426#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC01427#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 81428#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x3001429#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 101430#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC001431 1432/* TPC0_CFG_FUNC_MBIST_MEM */1433#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 01434#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF1435#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 121436#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x70001437#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 161438#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF00001439#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 281440#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x700000001441 1442/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */1443#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 01444#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1445 1446/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */1447#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 01448#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1449 1450/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */1451#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 01452#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF1453 1454/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */1455#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 01456#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x71457#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81458#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001459#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 161460#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x700001461#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 191462#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x800001463#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 201464#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001465#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 211466#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x6000001467 1468/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */1469#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 01470#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF1471 1472/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */1473#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 01474#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1475 1476/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */1477#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 01478#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF1479 1480/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */1481#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 01482#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1483 1484/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */1485#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 01486#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF1487 1488/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */1489#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 01490#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1491 1492/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */1493#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 01494#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF1495 1496/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */1497#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 01498#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1499 1500/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */1501#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 01502#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF1503 1504/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */1505#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 01506#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1507 1508/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */1509#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 01510#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1511 1512/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */1513#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 01514#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1515 1516/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */1517#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 01518#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF1519 1520/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */1521#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 01522#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x71523#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81524#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001525#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 161526#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x700001527#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 191528#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x800001529#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 201530#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001531#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 211532#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x6000001533 1534/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */1535#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 01536#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF1537 1538/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */1539#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 01540#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1541 1542/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */1543#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 01544#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF1545 1546/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */1547#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 01548#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1549 1550/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */1551#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 01552#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF1553 1554/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */1555#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 01556#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1557 1558/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */1559#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 01560#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF1561 1562/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */1563#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 01564#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1565 1566/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */1567#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 01568#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF1569 1570/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */1571#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 01572#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1573 1574/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */1575#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 01576#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1577 1578/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */1579#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 01580#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1581 1582/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */1583#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 01584#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF1585 1586/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */1587#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 01588#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x71589#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81590#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001591#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 161592#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x700001593#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 191594#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x800001595#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 201596#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001597#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 211598#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x6000001599 1600/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */1601#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 01602#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF1603 1604/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */1605#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 01606#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1607 1608/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */1609#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 01610#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF1611 1612/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */1613#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 01614#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1615 1616/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */1617#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 01618#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF1619 1620/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */1621#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 01622#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1623 1624/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */1625#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 01626#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF1627 1628/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */1629#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 01630#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1631 1632/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */1633#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 01634#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF1635 1636/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */1637#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 01638#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1639 1640/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */1641#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 01642#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1643 1644/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */1645#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 01646#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1647 1648/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */1649#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 01650#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF1651 1652/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */1653#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 01654#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x71655#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81656#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001657#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 161658#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x700001659#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 191660#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x800001661#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 201662#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001663#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 211664#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x6000001665 1666/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */1667#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 01668#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF1669 1670/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */1671#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 01672#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1673 1674/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */1675#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 01676#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF1677 1678/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */1679#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 01680#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1681 1682/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */1683#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 01684#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF1685 1686/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */1687#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 01688#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1689 1690/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */1691#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 01692#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF1693 1694/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */1695#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 01696#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1697 1698/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */1699#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 01700#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF1701 1702/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */1703#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 01704#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1705 1706/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */1707#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 01708#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1709 1710/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */1711#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 01712#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1713 1714/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */1715#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 01716#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF1717 1718/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */1719#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 01720#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x71721#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81722#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001723#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 161724#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x700001725#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 191726#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x800001727#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 201728#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001729#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 211730#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x6000001731 1732/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */1733#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 01734#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF1735 1736/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */1737#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 01738#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1739 1740/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */1741#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 01742#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF1743 1744/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */1745#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 01746#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1747 1748/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */1749#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 01750#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF1751 1752/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */1753#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 01754#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1755 1756/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */1757#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 01758#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF1759 1760/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */1761#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 01762#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1763 1764/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */1765#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 01766#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF1767 1768/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */1769#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 01770#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1771 1772/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */1773#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 01774#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1775 1776/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */1777#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 01778#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1779 1780/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */1781#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 01782#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF1783 1784/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */1785#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 01786#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x71787#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81788#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001789#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 161790#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x700001791#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 191792#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x800001793#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 201794#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001795#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 211796#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x6000001797 1798/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */1799#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 01800#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF1801 1802/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */1803#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 01804#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1805 1806/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */1807#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 01808#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF1809 1810/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */1811#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 01812#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1813 1814/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */1815#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 01816#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF1817 1818/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */1819#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 01820#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1821 1822/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */1823#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 01824#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF1825 1826/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */1827#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 01828#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1829 1830/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */1831#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 01832#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF1833 1834/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */1835#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 01836#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1837 1838/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */1839#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 01840#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1841 1842/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */1843#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 01844#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1845 1846/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */1847#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 01848#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF1849 1850/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */1851#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 01852#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x71853#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81854#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001855#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 161856#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x700001857#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 191858#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x800001859#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 201860#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001861#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 211862#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x6000001863 1864/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */1865#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 01866#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF1867 1868/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */1869#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 01870#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1871 1872/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */1873#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 01874#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF1875 1876/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */1877#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 01878#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1879 1880/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */1881#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 01882#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF1883 1884/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */1885#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 01886#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1887 1888/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */1889#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 01890#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF1891 1892/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */1893#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 01894#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1895 1896/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */1897#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 01898#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF1899 1900/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */1901#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 01902#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1903 1904/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */1905#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 01906#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1907 1908/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */1909#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 01910#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1911 1912/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */1913#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 01914#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF1915 1916/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */1917#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 01918#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x71919#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81920#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001921#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 161922#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x700001923#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 191924#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x800001925#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 201926#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001927#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 211928#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x6000001929 1930/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */1931#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 01932#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF1933 1934/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */1935#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 01936#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF1937 1938/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */1939#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 01940#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF1941 1942/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */1943#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 01944#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF1945 1946/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */1947#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 01948#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF1949 1950/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */1951#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 01952#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF1953 1954/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */1955#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 01956#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF1957 1958/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */1959#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 01960#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF1961 1962/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */1963#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 01964#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF1965 1966/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */1967#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 01968#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF1969 1970/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */1971#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 01972#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF1973 1974/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */1975#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 01976#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF1977 1978/* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */1979#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT 01980#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF1981 1982/* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */1983#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 01984#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x71985#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 81986#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F001987#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 161988#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x700001989#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 191990#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x800001991#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 201992#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000001993#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 211994#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x6000001995 1996/* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */1997#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT 01998#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF1999 2000/* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */2001#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT 02002#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF2003 2004/* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */2005#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT 02006#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF2007 2008/* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */2009#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT 02010#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF2011 2012/* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */2013#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT 02014#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF2015 2016/* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */2017#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT 02018#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF2019 2020/* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */2021#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT 02022#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF2023 2024/* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */2025#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT 02026#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF2027 2028/* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */2029#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT 02030#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF2031 2032/* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */2033#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT 02034#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF2035 2036/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */2037#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 02038#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF2039 2040/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */2041#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 02042#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF2043 2044/* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */2045#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT 02046#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF2047 2048/* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */2049#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 02050#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x72051#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 82052#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F002053#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 162054#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x700002055#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 192056#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x800002057#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 202058#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000002059#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 212060#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x6000002061 2062/* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */2063#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT 02064#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF2065 2066/* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */2067#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT 02068#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF2069 2070/* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */2071#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT 02072#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF2073 2074/* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */2075#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT 02076#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF2077 2078/* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */2079#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT 02080#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF2081 2082/* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */2083#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT 02084#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF2085 2086/* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */2087#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT 02088#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF2089 2090/* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */2091#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT 02092#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF2093 2094/* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */2095#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT 02096#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF2097 2098/* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */2099#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT 02100#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF2101 2102/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */2103#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 02104#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF2105 2106/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */2107#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 02108#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF2109 2110/* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */2111#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT 02112#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF2113 2114/* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */2115#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 02116#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x72117#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 82118#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F002119#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 162120#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x700002121#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 192122#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x800002123#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 202124#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000002125#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 212126#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x6000002127 2128/* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */2129#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT 02130#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF2131 2132/* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */2133#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT 02134#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF2135 2136/* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */2137#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT 02138#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF2139 2140/* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */2141#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT 02142#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF2143 2144/* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */2145#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT 02146#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF2147 2148/* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */2149#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT 02150#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF2151 2152/* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */2153#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT 02154#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF2155 2156/* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */2157#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT 02158#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF2159 2160/* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */2161#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT 02162#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF2163 2164/* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */2165#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT 02166#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF2167 2168/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */2169#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 02170#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF2171 2172/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */2173#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 02174#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF2175 2176/* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */2177#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT 02178#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF2179 2180/* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */2181#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 02182#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x72183#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 82184#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F002185#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 162186#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x700002187#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 192188#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x800002189#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 202190#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000002191#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 212192#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x6000002193 2194/* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */2195#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT 02196#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF2197 2198/* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */2199#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT 02200#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF2201 2202/* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */2203#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT 02204#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF2205 2206/* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */2207#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT 02208#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF2209 2210/* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */2211#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT 02212#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF2213 2214/* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */2215#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT 02216#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF2217 2218/* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */2219#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT 02220#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF2221 2222/* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */2223#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT 02224#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF2225 2226/* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */2227#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT 02228#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF2229 2230/* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */2231#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT 02232#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF2233 2234/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */2235#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 02236#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF2237 2238/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */2239#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 02240#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF2241 2242/* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */2243#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT 02244#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF2245 2246/* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */2247#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 02248#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x72249#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 82250#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F002251#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 162252#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x700002253#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 192254#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x800002255#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 202256#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000002257#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 212258#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x6000002259 2260/* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */2261#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT 02262#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF2263 2264/* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */2265#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT 02266#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF2267 2268/* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */2269#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT 02270#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF2271 2272/* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */2273#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT 02274#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF2275 2276/* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */2277#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT 02278#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF2279 2280/* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */2281#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT 02282#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF2283 2284/* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */2285#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT 02286#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF2287 2288/* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */2289#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT 02290#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF2291 2292/* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */2293#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT 02294#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF2295 2296/* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */2297#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT 02298#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF2299 2300/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */2301#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 02302#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF2303 2304/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */2305#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 02306#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF2307 2308/* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */2309#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT 02310#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF2311 2312/* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */2313#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 02314#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x72315#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 82316#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F002317#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 162318#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x700002319#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 192320#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x800002321#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 202322#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000002323#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 212324#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x6000002325 2326/* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */2327#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT 02328#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF2329 2330/* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */2331#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT 02332#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF2333 2334/* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */2335#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT 02336#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF2337 2338/* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */2339#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT 02340#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF2341 2342/* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */2343#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT 02344#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF2345 2346/* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */2347#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT 02348#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF2349 2350/* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */2351#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT 02352#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF2353 2354/* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */2355#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT 02356#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF2357 2358/* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */2359#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT 02360#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF2361 2362/* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */2363#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT 02364#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF2365 2366/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */2367#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 02368#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF2369 2370/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */2371#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 02372#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF2373 2374/* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */2375#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT 02376#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF2377 2378/* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */2379#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 02380#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x72381#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 82382#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F002383#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 162384#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x700002385#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 192386#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x800002387#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 202388#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000002389#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 212390#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x6000002391 2392/* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */2393#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT 02394#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF2395 2396/* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */2397#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT 02398#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF2399 2400/* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */2401#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT 02402#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF2403 2404/* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */2405#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT 02406#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF2407 2408/* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */2409#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT 02410#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF2411 2412/* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */2413#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT 02414#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF2415 2416/* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */2417#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT 02418#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF2419 2420/* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */2421#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT 02422#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF2423 2424/* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */2425#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT 02426#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF2427 2428/* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */2429#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT 02430#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF2431 2432/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */2433#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 02434#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF2435 2436/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */2437#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 02438#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF2439 2440/* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */2441#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT 02442#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF2443 2444/* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */2445#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 02446#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x72447#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 82448#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F002449#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 162450#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x700002451#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 192452#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x800002453#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 202454#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x1000002455#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 212456#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x6000002457 2458/* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */2459#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT 02460#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF2461 2462/* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */2463#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT 02464#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF2465 2466/* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */2467#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT 02468#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF2469 2470/* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */2471#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT 02472#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF2473 2474/* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */2475#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT 02476#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF2477 2478/* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */2479#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT 02480#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF2481 2482/* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */2483#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT 02484#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF2485 2486/* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */2487#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT 02488#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF2489 2490/* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */2491#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT 02492#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF2493 2494/* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */2495#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT 02496#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF2497 2498/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */2499#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 02500#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF2501#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT 162502#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF00002503#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 292504#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE00000002505 2506/* TPC0_CFG_QM_SYNC_OBJECT_ADDR */2507#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT 02508#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF2509 2510/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */2511#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 02512#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF2513 2514/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */2515#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 02516#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF2517 2518/* TPC0_CFG_QM_TID_BASE_DIM_0 */2519#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 02520#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF2521 2522/* TPC0_CFG_QM_TID_SIZE_DIM_0 */2523#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 02524#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF2525 2526/* TPC0_CFG_QM_TID_BASE_DIM_1 */2527#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 02528#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF2529 2530/* TPC0_CFG_QM_TID_SIZE_DIM_1 */2531#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 02532#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF2533 2534/* TPC0_CFG_QM_TID_BASE_DIM_2 */2535#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 02536#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF2537 2538/* TPC0_CFG_QM_TID_SIZE_DIM_2 */2539#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 02540#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF2541 2542/* TPC0_CFG_QM_TID_BASE_DIM_3 */2543#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 02544#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF2545 2546/* TPC0_CFG_QM_TID_SIZE_DIM_3 */2547#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 02548#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF2549 2550/* TPC0_CFG_QM_TID_BASE_DIM_4 */2551#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 02552#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF2553 2554/* TPC0_CFG_QM_TID_SIZE_DIM_4 */2555#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 02556#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF2557 2558/* TPC0_CFG_QM_KERNEL_CONFIG */2559#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 02560#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x12561#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 12562#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x22563#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 22564#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC2565#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 82566#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF002567#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 162568#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF00002569 2570/* TPC0_CFG_QM_KERNEL_ID */2571#define TPC0_CFG_QM_KERNEL_ID_V_SHIFT 02572#define TPC0_CFG_QM_KERNEL_ID_V_MASK 0xFFFF2573 2574/* TPC0_CFG_QM_SRF */2575#define TPC0_CFG_QM_SRF_V_SHIFT 02576#define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF2577 2578#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */2579