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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC0_QM_MASKS_H_14#define ASIC_REG_TPC0_QM_MASKS_H_15 16/*17 *****************************************18 * TPC0_QM (Prototype: QMAN)19 *****************************************20 */21 22/* TPC0_QM_GLBL_CFG0 */23#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 024#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF25#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 426#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F027#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 928#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0029 30/* TPC0_QM_GLBL_CFG1 */31#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 032#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF33#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 434#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F035#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 936#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0037#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 1638#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF000039#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 2040#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F0000041#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 2542#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E00000043 44/* TPC0_QM_GLBL_PROT */45#define TPC0_QM_GLBL_PROT_PQF_SHIFT 046#define TPC0_QM_GLBL_PROT_PQF_MASK 0xF47#define TPC0_QM_GLBL_PROT_CQF_SHIFT 448#define TPC0_QM_GLBL_PROT_CQF_MASK 0x1F049#define TPC0_QM_GLBL_PROT_CP_SHIFT 950#define TPC0_QM_GLBL_PROT_CP_MASK 0x3E0051#define TPC0_QM_GLBL_PROT_ERR_SHIFT 1452#define TPC0_QM_GLBL_PROT_ERR_MASK 0x400053#define TPC0_QM_GLBL_PROT_ARB_SHIFT 1554#define TPC0_QM_GLBL_PROT_ARB_MASK 0x800055 56/* TPC0_QM_GLBL_ERR_CFG */57#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 058#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF59#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 460#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F061#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 962#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E0063#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 1664#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF000065#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 2066#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F0000067#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 2568#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E00000069#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 3170#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x8000000071 72/* TPC0_QM_GLBL_SECURE_PROPS */73#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 074#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF75#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 076#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF77#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 078#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF79#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 080#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF81#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 082#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF83#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 1084#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x40085#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 1086#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x40087#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 1088#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x40089#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 1090#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x40091#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 1092#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x40093 94/* TPC0_QM_GLBL_NON_SECURE_PROPS */95#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 096#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF97#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 098#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF99#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0100#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF101#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0102#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF103#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0104#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF105#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10106#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400107#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10108#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400109#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10110#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400111#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10112#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400113#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10114#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400115 116/* TPC0_QM_GLBL_STS0 */117#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0118#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF119#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4120#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0121#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 9122#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00123#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16124#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000125#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20126#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000127#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25128#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000129#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31130#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000131 132/* TPC0_QM_GLBL_STS1 */133#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0134#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1135#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1136#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2137#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2138#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4139#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3140#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8141#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4142#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10143#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5144#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20145#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6146#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40147#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8148#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100149#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9150#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200151#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10152#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400153#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11154#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800155#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12156#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000157#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13158#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000159#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14160#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000161#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15162#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000163 164/* TPC0_QM_GLBL_STS1_4 */165#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1166#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2167#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2168#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4169#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3170#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8171#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4172#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10173#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5174#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20175#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6176#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40177#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8178#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100179#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9180#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200181#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10182#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400183#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11184#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800185#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12186#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000187#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13188#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000189#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14190#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000191#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15192#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000193 194/* TPC0_QM_GLBL_MSG_EN */195#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0196#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1197#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1198#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2199#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2200#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4201#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3202#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8203#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4204#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10205#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5206#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20207#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6208#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40209#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8210#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100211#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9212#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200213#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10214#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400215#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11216#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800217#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12218#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000219#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13220#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000221#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14222#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000223#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15224#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000225 226/* TPC0_QM_GLBL_MSG_EN_4 */227#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1228#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2229#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2230#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4231#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3232#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8233#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4234#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10235#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5236#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20237#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6238#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40239#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8240#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100241#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9242#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200243#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10244#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400245#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11246#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800247#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12248#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000249#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13250#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000251#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14252#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000253#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15254#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000255 256/* TPC0_QM_PQ_BASE_LO */257#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0258#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF259 260/* TPC0_QM_PQ_BASE_HI */261#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0262#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF263 264/* TPC0_QM_PQ_SIZE */265#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0266#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF267 268/* TPC0_QM_PQ_PI */269#define TPC0_QM_PQ_PI_VAL_SHIFT 0270#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF271 272/* TPC0_QM_PQ_CI */273#define TPC0_QM_PQ_CI_VAL_SHIFT 0274#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF275 276/* TPC0_QM_PQ_CFG0 */277#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0278#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1279 280/* TPC0_QM_PQ_CFG1 */281#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0282#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF283#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16284#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000285 286/* TPC0_QM_PQ_ARUSER_31_11 */287#define TPC0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0288#define TPC0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF289 290/* TPC0_QM_PQ_STS0 */291#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0292#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF293#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16294#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000295 296/* TPC0_QM_PQ_STS1 */297#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0298#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF299#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30300#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000301#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31302#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000303 304/* TPC0_QM_CQ_CFG0 */305#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0306#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1307 308/* TPC0_QM_CQ_CFG1 */309#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0310#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF311#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16312#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000313 314/* TPC0_QM_CQ_ARUSER_31_11 */315#define TPC0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0316#define TPC0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF317 318/* TPC0_QM_CQ_STS0 */319#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0320#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF321#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16322#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000323 324/* TPC0_QM_CQ_STS1 */325#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0326#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF327#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30328#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000329#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31330#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000331 332/* TPC0_QM_CQ_PTR_LO_0 */333#define TPC0_QM_CQ_PTR_LO_0_VAL_SHIFT 0334#define TPC0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF335 336/* TPC0_QM_CQ_PTR_HI_0 */337#define TPC0_QM_CQ_PTR_HI_0_VAL_SHIFT 0338#define TPC0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF339 340/* TPC0_QM_CQ_TSIZE_0 */341#define TPC0_QM_CQ_TSIZE_0_VAL_SHIFT 0342#define TPC0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF343 344/* TPC0_QM_CQ_CTL_0 */345#define TPC0_QM_CQ_CTL_0_RPT_SHIFT 0346#define TPC0_QM_CQ_CTL_0_RPT_MASK 0xFFFF347#define TPC0_QM_CQ_CTL_0_CTL_SHIFT 16348#define TPC0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000349 350/* TPC0_QM_CQ_PTR_LO_1 */351#define TPC0_QM_CQ_PTR_LO_1_VAL_SHIFT 0352#define TPC0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF353 354/* TPC0_QM_CQ_PTR_HI_1 */355#define TPC0_QM_CQ_PTR_HI_1_VAL_SHIFT 0356#define TPC0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF357 358/* TPC0_QM_CQ_TSIZE_1 */359#define TPC0_QM_CQ_TSIZE_1_VAL_SHIFT 0360#define TPC0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF361 362/* TPC0_QM_CQ_CTL_1 */363#define TPC0_QM_CQ_CTL_1_RPT_SHIFT 0364#define TPC0_QM_CQ_CTL_1_RPT_MASK 0xFFFF365#define TPC0_QM_CQ_CTL_1_CTL_SHIFT 16366#define TPC0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000367 368/* TPC0_QM_CQ_PTR_LO_2 */369#define TPC0_QM_CQ_PTR_LO_2_VAL_SHIFT 0370#define TPC0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF371 372/* TPC0_QM_CQ_PTR_HI_2 */373#define TPC0_QM_CQ_PTR_HI_2_VAL_SHIFT 0374#define TPC0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF375 376/* TPC0_QM_CQ_TSIZE_2 */377#define TPC0_QM_CQ_TSIZE_2_VAL_SHIFT 0378#define TPC0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF379 380/* TPC0_QM_CQ_CTL_2 */381#define TPC0_QM_CQ_CTL_2_RPT_SHIFT 0382#define TPC0_QM_CQ_CTL_2_RPT_MASK 0xFFFF383#define TPC0_QM_CQ_CTL_2_CTL_SHIFT 16384#define TPC0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000385 386/* TPC0_QM_CQ_PTR_LO_3 */387#define TPC0_QM_CQ_PTR_LO_3_VAL_SHIFT 0388#define TPC0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF389 390/* TPC0_QM_CQ_PTR_HI_3 */391#define TPC0_QM_CQ_PTR_HI_3_VAL_SHIFT 0392#define TPC0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF393 394/* TPC0_QM_CQ_TSIZE_3 */395#define TPC0_QM_CQ_TSIZE_3_VAL_SHIFT 0396#define TPC0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF397 398/* TPC0_QM_CQ_CTL_3 */399#define TPC0_QM_CQ_CTL_3_RPT_SHIFT 0400#define TPC0_QM_CQ_CTL_3_RPT_MASK 0xFFFF401#define TPC0_QM_CQ_CTL_3_CTL_SHIFT 16402#define TPC0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000403 404/* TPC0_QM_CQ_PTR_LO_4 */405#define TPC0_QM_CQ_PTR_LO_4_VAL_SHIFT 0406#define TPC0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF407 408/* TPC0_QM_CQ_PTR_HI_4 */409#define TPC0_QM_CQ_PTR_HI_4_VAL_SHIFT 0410#define TPC0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF411 412/* TPC0_QM_CQ_TSIZE_4 */413#define TPC0_QM_CQ_TSIZE_4_VAL_SHIFT 0414#define TPC0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF415 416/* TPC0_QM_CQ_CTL_4 */417#define TPC0_QM_CQ_CTL_4_RPT_SHIFT 0418#define TPC0_QM_CQ_CTL_4_RPT_MASK 0xFFFF419#define TPC0_QM_CQ_CTL_4_CTL_SHIFT 16420#define TPC0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000421 422/* TPC0_QM_CQ_PTR_LO_STS */423#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0424#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF425 426/* TPC0_QM_CQ_PTR_HI_STS */427#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0428#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF429 430/* TPC0_QM_CQ_TSIZE_STS */431#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0432#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF433 434/* TPC0_QM_CQ_CTL_STS */435#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0436#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF437#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16438#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000439 440/* TPC0_QM_CQ_IFIFO_CNT */441#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0442#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3443 444/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */445#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0446#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF447 448/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */449#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0450#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF451 452/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */453#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0454#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF455 456/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */457#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0458#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF459 460/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */461#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0462#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF463 464/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */465#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0466#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF467 468/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */469#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0470#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF471 472/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */473#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0474#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF475 476/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */477#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0478#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF479 480/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */481#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0482#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF483 484/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */485#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0486#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF487 488/* TPC0_QM_CP_FENCE0_RDATA */489#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0490#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF491 492/* TPC0_QM_CP_FENCE1_RDATA */493#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0494#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF495 496/* TPC0_QM_CP_FENCE2_RDATA */497#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0498#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF499 500/* TPC0_QM_CP_FENCE3_RDATA */501#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0502#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF503 504/* TPC0_QM_CP_FENCE0_CNT */505#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0506#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF507 508/* TPC0_QM_CP_FENCE1_CNT */509#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0510#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF511 512/* TPC0_QM_CP_FENCE2_CNT */513#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0514#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF515 516/* TPC0_QM_CP_FENCE3_CNT */517#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0518#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF519 520/* TPC0_QM_CP_STS */521#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0522#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF523#define TPC0_QM_CP_STS_ERDY_SHIFT 16524#define TPC0_QM_CP_STS_ERDY_MASK 0x10000525#define TPC0_QM_CP_STS_RRDY_SHIFT 17526#define TPC0_QM_CP_STS_RRDY_MASK 0x20000527#define TPC0_QM_CP_STS_MRDY_SHIFT 18528#define TPC0_QM_CP_STS_MRDY_MASK 0x40000529#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19530#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000531#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20532#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000533#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22534#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000535 536/* TPC0_QM_CP_CURRENT_INST_LO */537#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0538#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF539 540/* TPC0_QM_CP_CURRENT_INST_HI */541#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0542#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF543 544/* TPC0_QM_CP_BARRIER_CFG */545#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0546#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF547#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16548#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000549 550/* TPC0_QM_CP_DBG_0 */551#define TPC0_QM_CP_DBG_0_CS_SHIFT 0552#define TPC0_QM_CP_DBG_0_CS_MASK 0xF553#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4554#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10555#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5556#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20557#define TPC0_QM_CP_DBG_0_MREB_STALL_SHIFT 6558#define TPC0_QM_CP_DBG_0_MREB_STALL_MASK 0x40559#define TPC0_QM_CP_DBG_0_STALL_SHIFT 7560#define TPC0_QM_CP_DBG_0_STALL_MASK 0x80561 562/* TPC0_QM_CP_ARUSER_31_11 */563#define TPC0_QM_CP_ARUSER_31_11_VAL_SHIFT 0564#define TPC0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF565 566/* TPC0_QM_CP_AWUSER_31_11 */567#define TPC0_QM_CP_AWUSER_31_11_VAL_SHIFT 0568#define TPC0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF569 570/* TPC0_QM_ARB_CFG_0 */571#define TPC0_QM_ARB_CFG_0_TYPE_SHIFT 0572#define TPC0_QM_ARB_CFG_0_TYPE_MASK 0x1573#define TPC0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4574#define TPC0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10575#define TPC0_QM_ARB_CFG_0_EN_SHIFT 8576#define TPC0_QM_ARB_CFG_0_EN_MASK 0x100577#define TPC0_QM_ARB_CFG_0_MASK_SHIFT 12578#define TPC0_QM_ARB_CFG_0_MASK_MASK 0xF000579#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16580#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000581 582/* TPC0_QM_ARB_CHOISE_Q_PUSH */583#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0584#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3585 586/* TPC0_QM_ARB_WRR_WEIGHT */587#define TPC0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0588#define TPC0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF589 590/* TPC0_QM_ARB_CFG_1 */591#define TPC0_QM_ARB_CFG_1_CLR_SHIFT 0592#define TPC0_QM_ARB_CFG_1_CLR_MASK 0x1593 594/* TPC0_QM_ARB_MST_AVAIL_CRED */595#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0596#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F597 598/* TPC0_QM_ARB_MST_CRED_INC */599#define TPC0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0600#define TPC0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF601 602/* TPC0_QM_ARB_MST_CHOISE_PUSH_OFST */603#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0604#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF605 606/* TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST */607#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0608#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF609 610/* TPC0_QM_ARB_MST_SLAVE_EN */611#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0612#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF613 614/* TPC0_QM_ARB_MST_QUIET_PER */615#define TPC0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0616#define TPC0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF617 618/* TPC0_QM_ARB_SLV_CHOISE_WDT */619#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0620#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF621 622/* TPC0_QM_ARB_SLV_ID */623#define TPC0_QM_ARB_SLV_ID_VAL_SHIFT 0624#define TPC0_QM_ARB_SLV_ID_VAL_MASK 0x1F625 626/* TPC0_QM_ARB_MSG_MAX_INFLIGHT */627#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0628#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F629 630/* TPC0_QM_ARB_MSG_AWUSER_31_11 */631#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0632#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF633 634/* TPC0_QM_ARB_MSG_AWUSER_SEC_PROP */635#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0636#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF637#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10638#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400639 640/* TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */641#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0642#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF643#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10644#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400645 646/* TPC0_QM_ARB_BASE_LO */647#define TPC0_QM_ARB_BASE_LO_VAL_SHIFT 0648#define TPC0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF649 650/* TPC0_QM_ARB_BASE_HI */651#define TPC0_QM_ARB_BASE_HI_VAL_SHIFT 0652#define TPC0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF653 654/* TPC0_QM_ARB_STATE_STS */655#define TPC0_QM_ARB_STATE_STS_VAL_SHIFT 0656#define TPC0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF657 658/* TPC0_QM_ARB_CHOISE_FULLNESS_STS */659#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0660#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F661 662/* TPC0_QM_ARB_MSG_STS */663#define TPC0_QM_ARB_MSG_STS_FULL_SHIFT 0664#define TPC0_QM_ARB_MSG_STS_FULL_MASK 0x1665#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1666#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2667 668/* TPC0_QM_ARB_SLV_CHOISE_Q_HEAD */669#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0670#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3671 672/* TPC0_QM_ARB_ERR_CAUSE */673#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0674#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1675#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1676#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2677#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2678#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4679 680/* TPC0_QM_ARB_ERR_MSG_EN */681#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0682#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1683#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1684#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2685#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2686#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4687 688/* TPC0_QM_ARB_ERR_STS_DRP */689#define TPC0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0690#define TPC0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3691 692/* TPC0_QM_ARB_MST_CRED_STS */693#define TPC0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0694#define TPC0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F695 696/* TPC0_QM_CGM_CFG */697#define TPC0_QM_CGM_CFG_IDLE_TH_SHIFT 0698#define TPC0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF699#define TPC0_QM_CGM_CFG_G2F_TH_SHIFT 16700#define TPC0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000701#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24702#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000703#define TPC0_QM_CGM_CFG_EN_SHIFT 31704#define TPC0_QM_CGM_CFG_EN_MASK 0x80000000705 706/* TPC0_QM_CGM_STS */707#define TPC0_QM_CGM_STS_ST_SHIFT 0708#define TPC0_QM_CGM_STS_ST_MASK 0x3709#define TPC0_QM_CGM_STS_CG_SHIFT 4710#define TPC0_QM_CGM_STS_CG_MASK 0x10711#define TPC0_QM_CGM_STS_AGENT_IDLE_SHIFT 8712#define TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100713#define TPC0_QM_CGM_STS_AXI_IDLE_SHIFT 9714#define TPC0_QM_CGM_STS_AXI_IDLE_MASK 0x200715#define TPC0_QM_CGM_STS_CP_IDLE_SHIFT 10716#define TPC0_QM_CGM_STS_CP_IDLE_MASK 0x400717 718/* TPC0_QM_CGM_CFG1 */719#define TPC0_QM_CGM_CFG1_MASK_TH_SHIFT 0720#define TPC0_QM_CGM_CFG1_MASK_TH_MASK 0xFF721 722/* TPC0_QM_LOCAL_RANGE_BASE */723#define TPC0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0724#define TPC0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF725 726/* TPC0_QM_LOCAL_RANGE_SIZE */727#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0728#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF729 730/* TPC0_QM_CSMR_STRICT_PRIO_CFG */731#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0732#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1733 734/* TPC0_QM_HBW_RD_RATE_LIM_CFG_1 */735#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0736#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF737#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31738#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000739 740/* TPC0_QM_LBW_WR_RATE_LIM_CFG_0 */741#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0742#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF743#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16744#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000745 746/* TPC0_QM_LBW_WR_RATE_LIM_CFG_1 */747#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0748#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF749#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31750#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000751 752/* TPC0_QM_HBW_RD_RATE_LIM_CFG_0 */753#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0754#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF755#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16756#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000757 758/* TPC0_QM_GLBL_AXCACHE */759#define TPC0_QM_GLBL_AXCACHE_AR_SHIFT 0760#define TPC0_QM_GLBL_AXCACHE_AR_MASK 0xF761#define TPC0_QM_GLBL_AXCACHE_AW_SHIFT 16762#define TPC0_QM_GLBL_AXCACHE_AW_MASK 0xF0000763 764/* TPC0_QM_IND_GW_APB_CFG */765#define TPC0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0766#define TPC0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF767#define TPC0_QM_IND_GW_APB_CFG_CMD_SHIFT 31768#define TPC0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000769 770/* TPC0_QM_IND_GW_APB_WDATA */771#define TPC0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0772#define TPC0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF773 774/* TPC0_QM_IND_GW_APB_RDATA */775#define TPC0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0776#define TPC0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF777 778/* TPC0_QM_IND_GW_APB_STATUS */779#define TPC0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0780#define TPC0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1781#define TPC0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1782#define TPC0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2783 784/* TPC0_QM_GLBL_ERR_ADDR_LO */785#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0786#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF787 788/* TPC0_QM_GLBL_ERR_ADDR_HI */789#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0790#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF791 792/* TPC0_QM_GLBL_ERR_WDATA */793#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0794#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF795 796/* TPC0_QM_GLBL_MEM_INIT_BUSY */797#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0798#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF799 800#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */801