1227 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC1_CFG_REGS_H_14#define ASIC_REG_TPC1_CFG_REGS_H_15 16/*17 *****************************************18 * TPC1_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE4640023 24#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE4640425 26#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE4640827 28#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C29 30#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE4641031 32#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE4641433 34#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE4641835 36#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE4641C37 38#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE4642039 40#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE4642441 42#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE4642843 44#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE4642C45 46#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE4643047 48#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE4643449 50#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE4643851 52#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE4643C53 54#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE4644055 56#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE4644457 58#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE4644859 60#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE4644C61 62#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE4645063 64#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE4645465 66#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE4645867 68#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE4645C69 70#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE4646071 72#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE4646473 74#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE4646875 76#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE4646C77 78#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE4647079 80#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE4647481 82#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE4647883 84#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE4647C85 86#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE4648087 88#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE4648489 90#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE4648891 92#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE4648C93 94#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE4649095 96#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE4649497 98#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE4649899 100#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE4649C101 102#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464A0103 104#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464A4105 106#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464A8107 108#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464AC109 110#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464B0111 112#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464B4113 114#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464B8115 116#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464BC117 118#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE464C0119 120#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE464C4121 122#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE464C8123 124#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE464CC125 126#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE464D0127 128#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE464D4129 130#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE464D8131 132#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE464DC133 134#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE464E0135 136#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE464E4137 138#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE464E8139 140#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE464EC141 142#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE464F0143 144#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE464F4145 146#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE464F8147 148#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE464FC149 150#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46500151 152#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE46504153 154#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46508155 156#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE4650C157 158#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46510159 160#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46514161 162#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE46518163 164#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE4651C165 166#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46520167 168#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46524169 170#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE46528171 172#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE4652C173 174#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46530175 176#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE46534177 178#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE46538179 180#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE4653C181 182#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE46540183 184#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE46544185 186#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE46548187 188#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE4654C189 190#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE46550191 192#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE46554193 194#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE46558195 196#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE4655C197 198#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE46560199 200#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE46564201 202#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE46568203 204#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE4656C205 206#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE46570207 208#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE46574209 210#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE46578211 212#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE4657C213 214#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46580215 216#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE46584217 218#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46588219 220#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE4658C221 222#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE46590223 224#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46594225 226#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46598227 228#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE4659C229 230#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE465A0231 232#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE465A4233 234#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE465A8235 236#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE465AC237 238#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE465B0239 240#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE465B4241 242#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE465B8243 244#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE465BC245 246#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE465C0247 248#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE465C4249 250#define mmTPC1_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE465C8251 252#define mmTPC1_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE465CC253 254#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE465D0255 256#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE465D4257 258#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE465D8259 260#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE465DC261 262#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE465E0263 264#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE465E4265 266#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE465E8267 268#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE465EC269 270#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE465F0271 272#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE465F4273 274#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE465F8275 276#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE465FC277 278#define mmTPC1_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE46600279 280#define mmTPC1_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE46604281 282#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE46608283 284#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE4660C285 286#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE46610287 288#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE46614289 290#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE46618291 292#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE4661C293 294#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE46620295 296#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE46624297 298#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE46628299 300#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE4662C301 302#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE46630303 304#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE46634305 306#define mmTPC1_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE46638307 308#define mmTPC1_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE4663C309 310#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE46640311 312#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE46644313 314#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE46648315 316#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE4664C317 318#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE46650319 320#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE46654321 322#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE46658323 324#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE4665C325 326#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE46660327 328#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE46664329 330#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE46668331 332#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE4666C333 334#define mmTPC1_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE46670335 336#define mmTPC1_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE46674337 338#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE46678339 340#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE4667C341 342#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE46680343 344#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE46684345 346#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE46688347 348#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE4668C349 350#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE46690351 352#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE46694353 354#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE46698355 356#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE4669C357 358#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE466A0359 360#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE466A4361 362#define mmTPC1_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE466A8363 364#define mmTPC1_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE466AC365 366#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE466B0367 368#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE466B4369 370#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE466B8371 372#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE466BC373 374#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE466C0375 376#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE466C4377 378#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE466C8379 380#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE466CC381 382#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE466D0383 384#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE466D4385 386#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE466D8387 388#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE466DC389 390#define mmTPC1_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE466E0391 392#define mmTPC1_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE466E4393 394#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE466E8395 396#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE466EC397 398#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE466F0399 400#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE466F4401 402#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE466F8403 404#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE466FC405 406#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE46700407 408#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE46704409 410#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE46708411 412#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE4670C413 414#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE46710415 416#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE46714417 418#define mmTPC1_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE46718419 420#define mmTPC1_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE4671C421 422#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE46720423 424#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE46724425 426#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE46728427 428#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE4672C429 430#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE46730431 432#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE46734433 434#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE46738435 436#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE4673C437 438#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE46740439 440#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE46744441 442#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE46748443 444#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE4674C445 446#define mmTPC1_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE46750447 448#define mmTPC1_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE46754449 450#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE46758451 452#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE4675C453 454#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE46760455 456#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE46764457 458#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE46768459 460#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE4676C461 462#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE46770463 464#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE46774465 466#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE46778467 468#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE4677C469 470#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46780471 472#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE46784473 474#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46788475 476#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE4678C477 478#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46790479 480#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE46794481 482#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46798483 484#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE4679C485 486#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE467A0487 488#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE467A4489 490#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE467A8491 492#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE467AC493 494#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE467B0495 496#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE467B4497 498#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE467B8499 500#define mmTPC1_CFG_KERNEL_KERNEL_ID 0xE467BC501 502#define mmTPC1_CFG_KERNEL_SRF_0 0xE467C0503 504#define mmTPC1_CFG_KERNEL_SRF_1 0xE467C4505 506#define mmTPC1_CFG_KERNEL_SRF_2 0xE467C8507 508#define mmTPC1_CFG_KERNEL_SRF_3 0xE467CC509 510#define mmTPC1_CFG_KERNEL_SRF_4 0xE467D0511 512#define mmTPC1_CFG_KERNEL_SRF_5 0xE467D4513 514#define mmTPC1_CFG_KERNEL_SRF_6 0xE467D8515 516#define mmTPC1_CFG_KERNEL_SRF_7 0xE467DC517 518#define mmTPC1_CFG_KERNEL_SRF_8 0xE467E0519 520#define mmTPC1_CFG_KERNEL_SRF_9 0xE467E4521 522#define mmTPC1_CFG_KERNEL_SRF_10 0xE467E8523 524#define mmTPC1_CFG_KERNEL_SRF_11 0xE467EC525 526#define mmTPC1_CFG_KERNEL_SRF_12 0xE467F0527 528#define mmTPC1_CFG_KERNEL_SRF_13 0xE467F4529 530#define mmTPC1_CFG_KERNEL_SRF_14 0xE467F8531 532#define mmTPC1_CFG_KERNEL_SRF_15 0xE467FC533 534#define mmTPC1_CFG_KERNEL_SRF_16 0xE46800535 536#define mmTPC1_CFG_KERNEL_SRF_17 0xE46804537 538#define mmTPC1_CFG_KERNEL_SRF_18 0xE46808539 540#define mmTPC1_CFG_KERNEL_SRF_19 0xE4680C541 542#define mmTPC1_CFG_KERNEL_SRF_20 0xE46810543 544#define mmTPC1_CFG_KERNEL_SRF_21 0xE46814545 546#define mmTPC1_CFG_KERNEL_SRF_22 0xE46818547 548#define mmTPC1_CFG_KERNEL_SRF_23 0xE4681C549 550#define mmTPC1_CFG_KERNEL_SRF_24 0xE46820551 552#define mmTPC1_CFG_KERNEL_SRF_25 0xE46824553 554#define mmTPC1_CFG_KERNEL_SRF_26 0xE46828555 556#define mmTPC1_CFG_KERNEL_SRF_27 0xE4682C557 558#define mmTPC1_CFG_KERNEL_SRF_28 0xE46830559 560#define mmTPC1_CFG_KERNEL_SRF_29 0xE46834561 562#define mmTPC1_CFG_KERNEL_SRF_30 0xE46838563 564#define mmTPC1_CFG_KERNEL_SRF_31 0xE4683C565 566#define mmTPC1_CFG_ROUND_CSR 0xE468FC567 568#define mmTPC1_CFG_PROT 0xE46900569 570#define mmTPC1_CFG_SEMAPHORE 0xE46908571 572#define mmTPC1_CFG_VFLAGS 0xE4690C573 574#define mmTPC1_CFG_SFLAGS 0xE46910575 576#define mmTPC1_CFG_LFSR_POLYNOM 0xE46918577 578#define mmTPC1_CFG_STATUS 0xE4691C579 580#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46920581 582#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46924583 584#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4692C585 586#define mmTPC1_CFG_TPC_CMD 0xE46930587 588#define mmTPC1_CFG_TPC_EXECUTE 0xE46938589 590#define mmTPC1_CFG_TPC_STALL 0xE4693C591 592#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46940593 594#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46944595 596#define mmTPC1_CFG_RD_RATE_LIMIT 0xE46948597 598#define mmTPC1_CFG_WR_RATE_LIMIT 0xE46950599 600#define mmTPC1_CFG_MSS_CONFIG 0xE46954601 602#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46958603 604#define mmTPC1_CFG_TPC_INTR_MASK 0xE4695C605 606#define mmTPC1_CFG_WQ_CREDITS 0xE46960607 608#define mmTPC1_CFG_ARUSER_LO 0xE46964609 610#define mmTPC1_CFG_ARUSER_HI 0xE46968611 612#define mmTPC1_CFG_AWUSER_LO 0xE4696C613 614#define mmTPC1_CFG_AWUSER_HI 0xE46970615 616#define mmTPC1_CFG_OPCODE_EXEC 0xE46974617 618#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE46978619 620#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE4697C621 622#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE46980623 624#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE46984625 626#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE46988627 628#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE4698C629 630#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE46990631 632#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE46994633 634#define mmTPC1_CFG_TSB_CFG_MAX_SIZE 0xE46998635 636#define mmTPC1_CFG_TSB_CFG 0xE4699C637 638#define mmTPC1_CFG_DBGMEM_ADD 0xE469A0639 640#define mmTPC1_CFG_DBGMEM_DATA_WR 0xE469A4641 642#define mmTPC1_CFG_DBGMEM_DATA_RD 0xE469A8643 644#define mmTPC1_CFG_DBGMEM_CTRL 0xE469AC645 646#define mmTPC1_CFG_DBGMEM_RC 0xE469B0647 648#define mmTPC1_CFG_TSB_INFLIGHT_CNTR 0xE469B4649 650#define mmTPC1_CFG_WQ_INFLIGHT_CNTR 0xE469B8651 652#define mmTPC1_CFG_WQ_LBW_TOTAL_CNTR 0xE469BC653 654#define mmTPC1_CFG_WQ_HBW_TOTAL_CNTR 0xE469C0655 656#define mmTPC1_CFG_IRQ_OCCOUPY_CNTR 0xE469C4657 658#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE469D0659 660#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE469D4661 662#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE469D8663 664#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE469DC665 666#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE469E0667 668#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE469E4669 670#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE469E8671 672#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE469EC673 674#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE469F0675 676#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE469F4677 678#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE469F8679 680#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE469FC681 682#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00683 684#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04685 686#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08687 688#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C689 690#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10691 692#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14693 694#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A18695 696#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A1C697 698#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A20699 700#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A24701 702#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A28703 704#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A2C705 706#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A30707 708#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A34709 710#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A38711 712#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A3C713 714#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A40715 716#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A44717 718#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A48719 720#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A4C721 722#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A50723 724#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A54725 726#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A58727 728#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A5C729 730#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A60731 732#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A64733 734#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A68735 736#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A6C737 738#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A70739 740#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A74741 742#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46A78743 744#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46A7C745 746#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46A80747 748#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46A84749 750#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46A88751 752#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46A8C753 754#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46A90755 756#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46A94757 758#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46A98759 760#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46A9C761 762#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AA0763 764#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46AA4765 766#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AA8767 768#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AAC769 770#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AB0771 772#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AB4773 774#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AB8775 776#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46ABC777 778#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46AC0779 780#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46AC4781 782#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46AC8783 784#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46ACC785 786#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46AD0787 788#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46AD4789 790#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46AD8791 792#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46ADC793 794#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46AE0795 796#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46AE4797 798#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46AE8799 800#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46AEC801 802#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46AF0803 804#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46AF4805 806#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46AF8807 808#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46AFC809 810#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B00811 812#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B04813 814#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B08815 816#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B0C817 818#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B10819 820#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B14821 822#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B18823 824#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B1C825 826#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B20827 828#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B24829 830#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B28831 832#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B2C833 834#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B30835 836#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B34837 838#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46B38839 840#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46B3C841 842#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46B40843 844#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46B44845 846#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46B48847 848#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46B4C849 850#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46B50851 852#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46B54853 854#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46B58855 856#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46B5C857 858#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46B60859 860#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46B64861 862#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46B68863 864#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46B6C865 866#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46B70867 868#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46B74869 870#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46B78871 872#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46B7C873 874#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46B80875 876#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46B84877 878#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46B88879 880#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46B8C881 882#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46B90883 884#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46B94885 886#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46B98887 888#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46B9C889 890#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46BA0891 892#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46BA4893 894#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46BA8895 896#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46BAC897 898#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46BB0899 900#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46BB4901 902#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46BB8903 904#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46BBC905 906#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE46BC0907 908#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE46BC4909 910#define mmTPC1_CFG_QM_TENSOR_8_PADDING_VALUE 0xE46BC8911 912#define mmTPC1_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE46BCC913 914#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE46BD0915 916#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE46BD4917 918#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE46BD8919 920#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE46BDC921 922#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE46BE0923 924#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE46BE4925 926#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE46BE8927 928#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE46BEC929 930#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE46BF0931 932#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE46BF4933 934#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE46BF8935 936#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE46BFC937 938#define mmTPC1_CFG_QM_TENSOR_9_PADDING_VALUE 0xE46C00939 940#define mmTPC1_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE46C04941 942#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE46C08943 944#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE46C0C945 946#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE46C10947 948#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE46C14949 950#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE46C18951 952#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE46C1C953 954#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE46C20955 956#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE46C24957 958#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE46C28959 960#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE46C2C961 962#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE46C30963 964#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE46C34965 966#define mmTPC1_CFG_QM_TENSOR_10_PADDING_VALUE 0xE46C38967 968#define mmTPC1_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE46C3C969 970#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE46C40971 972#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE46C44973 974#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE46C48975 976#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE46C4C977 978#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE46C50979 980#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE46C54981 982#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE46C58983 984#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE46C5C985 986#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE46C60987 988#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE46C64989 990#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE46C68991 992#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE46C6C993 994#define mmTPC1_CFG_QM_TENSOR_11_PADDING_VALUE 0xE46C70995 996#define mmTPC1_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE46C74997 998#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE46C78999 1000#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE46C7C1001 1002#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE46C801003 1004#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE46C841005 1006#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE46C881007 1008#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE46C8C1009 1010#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE46C901011 1012#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE46C941013 1014#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE46C981015 1016#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE46C9C1017 1018#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE46CA01019 1020#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE46CA41021 1022#define mmTPC1_CFG_QM_TENSOR_12_PADDING_VALUE 0xE46CA81023 1024#define mmTPC1_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE46CAC1025 1026#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE46CB01027 1028#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE46CB41029 1030#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE46CB81031 1032#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE46CBC1033 1034#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE46CC01035 1036#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE46CC41037 1038#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE46CC81039 1040#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE46CCC1041 1042#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE46CD01043 1044#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE46CD41045 1046#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE46CD81047 1048#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE46CDC1049 1050#define mmTPC1_CFG_QM_TENSOR_13_PADDING_VALUE 0xE46CE01051 1052#define mmTPC1_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE46CE41053 1054#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE46CE81055 1056#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE46CEC1057 1058#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE46CF01059 1060#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE46CF41061 1062#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE46CF81063 1064#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE46CFC1065 1066#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE46D001067 1068#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE46D041069 1070#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE46D081071 1072#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE46D0C1073 1074#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE46D101075 1076#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE46D141077 1078#define mmTPC1_CFG_QM_TENSOR_14_PADDING_VALUE 0xE46D181079 1080#define mmTPC1_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE46D1C1081 1082#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE46D201083 1084#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE46D241085 1086#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE46D281087 1088#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE46D2C1089 1090#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE46D301091 1092#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE46D341093 1094#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE46D381095 1096#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE46D3C1097 1098#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE46D401099 1100#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE46D441101 1102#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE46D481103 1104#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE46D4C1105 1106#define mmTPC1_CFG_QM_TENSOR_15_PADDING_VALUE 0xE46D501107 1108#define mmTPC1_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE46D541109 1110#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE46D581111 1112#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE46D5C1113 1114#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE46D601115 1116#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE46D641117 1118#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE46D681119 1120#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE46D6C1121 1122#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE46D701123 1124#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE46D741125 1126#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE46D781127 1128#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE46D7C1129 1130#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D801131 1132#define mmTPC1_CFG_QM_SYNC_OBJECT_ADDR 0xE46D841133 1134#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46D881135 1136#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46D8C1137 1138#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46D901139 1140#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46D941141 1142#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46D981143 1144#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46D9C1145 1146#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46DA01147 1148#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46DA41149 1150#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46DA81151 1152#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46DAC1153 1154#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46DB01155 1156#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46DB41157 1158#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46DB81159 1160#define mmTPC1_CFG_QM_KERNEL_ID 0xE46DBC1161 1162#define mmTPC1_CFG_QM_SRF_0 0xE46DC01163 1164#define mmTPC1_CFG_QM_SRF_1 0xE46DC41165 1166#define mmTPC1_CFG_QM_SRF_2 0xE46DC81167 1168#define mmTPC1_CFG_QM_SRF_3 0xE46DCC1169 1170#define mmTPC1_CFG_QM_SRF_4 0xE46DD01171 1172#define mmTPC1_CFG_QM_SRF_5 0xE46DD41173 1174#define mmTPC1_CFG_QM_SRF_6 0xE46DD81175 1176#define mmTPC1_CFG_QM_SRF_7 0xE46DDC1177 1178#define mmTPC1_CFG_QM_SRF_8 0xE46DE01179 1180#define mmTPC1_CFG_QM_SRF_9 0xE46DE41181 1182#define mmTPC1_CFG_QM_SRF_10 0xE46DE81183 1184#define mmTPC1_CFG_QM_SRF_11 0xE46DEC1185 1186#define mmTPC1_CFG_QM_SRF_12 0xE46DF01187 1188#define mmTPC1_CFG_QM_SRF_13 0xE46DF41189 1190#define mmTPC1_CFG_QM_SRF_14 0xE46DF81191 1192#define mmTPC1_CFG_QM_SRF_15 0xE46DFC1193 1194#define mmTPC1_CFG_QM_SRF_16 0xE46E001195 1196#define mmTPC1_CFG_QM_SRF_17 0xE46E041197 1198#define mmTPC1_CFG_QM_SRF_18 0xE46E081199 1200#define mmTPC1_CFG_QM_SRF_19 0xE46E0C1201 1202#define mmTPC1_CFG_QM_SRF_20 0xE46E101203 1204#define mmTPC1_CFG_QM_SRF_21 0xE46E141205 1206#define mmTPC1_CFG_QM_SRF_22 0xE46E181207 1208#define mmTPC1_CFG_QM_SRF_23 0xE46E1C1209 1210#define mmTPC1_CFG_QM_SRF_24 0xE46E201211 1212#define mmTPC1_CFG_QM_SRF_25 0xE46E241213 1214#define mmTPC1_CFG_QM_SRF_26 0xE46E281215 1216#define mmTPC1_CFG_QM_SRF_27 0xE46E2C1217 1218#define mmTPC1_CFG_QM_SRF_28 0xE46E301219 1220#define mmTPC1_CFG_QM_SRF_29 0xE46E341221 1222#define mmTPC1_CFG_QM_SRF_30 0xE46E381223 1224#define mmTPC1_CFG_QM_SRF_31 0xE46E3C1225 1226#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */1227