1227 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC2_CFG_REGS_H_14#define ASIC_REG_TPC2_CFG_REGS_H_15 16/*17 *****************************************18 * TPC2_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE8640023 24#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE8640425 26#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE8640827 28#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C29 30#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE8641031 32#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE8641433 34#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE8641835 36#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8641C37 38#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE8642039 40#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE8642441 42#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE8642843 44#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8642C45 46#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE8643047 48#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE8643449 50#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE8643851 52#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8643C53 54#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE8644055 56#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE8644457 58#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE8644859 60#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8644C61 62#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE8645063 64#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE8645465 66#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE8645867 68#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8645C69 70#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE8646071 72#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE8646473 74#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE8646875 76#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8646C77 78#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE8647079 80#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE8647481 82#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE8647883 84#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE8647C85 86#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE8648087 88#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE8648489 90#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE8648891 92#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE8648C93 94#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE8649095 96#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE8649497 98#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE8649899 100#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE8649C101 102#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864A0103 104#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864A4105 106#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864A8107 108#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864AC109 110#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864B0111 112#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864B4113 114#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864B8115 116#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864BC117 118#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE864C0119 120#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE864C4121 122#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE864C8123 124#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE864CC125 126#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE864D0127 128#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE864D4129 130#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE864D8131 132#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE864DC133 134#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE864E0135 136#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE864E4137 138#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE864E8139 140#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE864EC141 142#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE864F0143 144#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE864F4145 146#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE864F8147 148#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE864FC149 150#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86500151 152#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE86504153 154#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86508155 156#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE8650C157 158#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86510159 160#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86514161 162#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE86518163 164#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE8651C165 166#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86520167 168#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86524169 170#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE86528171 172#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE8652C173 174#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86530175 176#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE86534177 178#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE86538179 180#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE8653C181 182#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE86540183 184#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE86544185 186#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE86548187 188#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE8654C189 190#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE86550191 192#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE86554193 194#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE86558195 196#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE8655C197 198#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE86560199 200#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE86564201 202#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE86568203 204#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE8656C205 206#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE86570207 208#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE86574209 210#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE86578211 212#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE8657C213 214#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86580215 216#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE86584217 218#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86588219 220#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE8658C221 222#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE86590223 224#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86594225 226#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86598227 228#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE8659C229 230#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE865A0231 232#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE865A4233 234#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE865A8235 236#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE865AC237 238#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE865B0239 240#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE865B4241 242#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE865B8243 244#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE865BC245 246#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE865C0247 248#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE865C4249 250#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE865C8251 252#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE865CC253 254#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE865D0255 256#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE865D4257 258#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE865D8259 260#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE865DC261 262#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE865E0263 264#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE865E4265 266#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE865E8267 268#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE865EC269 270#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE865F0271 272#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE865F4273 274#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE865F8275 276#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE865FC277 278#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE86600279 280#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE86604281 282#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE86608283 284#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE8660C285 286#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE86610287 288#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE86614289 290#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE86618291 292#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE8661C293 294#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE86620295 296#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE86624297 298#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE86628299 300#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE8662C301 302#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE86630303 304#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE86634305 306#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE86638307 308#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE8663C309 310#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE86640311 312#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE86644313 314#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE86648315 316#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE8664C317 318#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE86650319 320#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE86654321 322#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE86658323 324#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE8665C325 326#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE86660327 328#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE86664329 330#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE86668331 332#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE8666C333 334#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE86670335 336#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE86674337 338#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE86678339 340#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE8667C341 342#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE86680343 344#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE86684345 346#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE86688347 348#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE8668C349 350#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE86690351 352#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE86694353 354#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE86698355 356#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE8669C357 358#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE866A0359 360#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE866A4361 362#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE866A8363 364#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE866AC365 366#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE866B0367 368#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE866B4369 370#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE866B8371 372#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE866BC373 374#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE866C0375 376#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE866C4377 378#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE866C8379 380#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE866CC381 382#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE866D0383 384#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE866D4385 386#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE866D8387 388#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE866DC389 390#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE866E0391 392#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE866E4393 394#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE866E8395 396#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE866EC397 398#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE866F0399 400#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE866F4401 402#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE866F8403 404#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE866FC405 406#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE86700407 408#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE86704409 410#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE86708411 412#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE8670C413 414#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE86710415 416#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE86714417 418#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE86718419 420#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE8671C421 422#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE86720423 424#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE86724425 426#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE86728427 428#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE8672C429 430#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE86730431 432#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE86734433 434#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE86738435 436#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE8673C437 438#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE86740439 440#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE86744441 442#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE86748443 444#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE8674C445 446#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE86750447 448#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE86754449 450#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE86758451 452#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE8675C453 454#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE86760455 456#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE86764457 458#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE86768459 460#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE8676C461 462#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE86770463 464#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE86774465 466#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE86778467 468#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE8677C469 470#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86780471 472#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE86784473 474#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86788475 476#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE8678C477 478#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86790479 480#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE86794481 482#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86798483 484#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE8679C485 486#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE867A0487 488#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE867A4489 490#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE867A8491 492#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE867AC493 494#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE867B0495 496#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE867B4497 498#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE867B8499 500#define mmTPC2_CFG_KERNEL_KERNEL_ID 0xE867BC501 502#define mmTPC2_CFG_KERNEL_SRF_0 0xE867C0503 504#define mmTPC2_CFG_KERNEL_SRF_1 0xE867C4505 506#define mmTPC2_CFG_KERNEL_SRF_2 0xE867C8507 508#define mmTPC2_CFG_KERNEL_SRF_3 0xE867CC509 510#define mmTPC2_CFG_KERNEL_SRF_4 0xE867D0511 512#define mmTPC2_CFG_KERNEL_SRF_5 0xE867D4513 514#define mmTPC2_CFG_KERNEL_SRF_6 0xE867D8515 516#define mmTPC2_CFG_KERNEL_SRF_7 0xE867DC517 518#define mmTPC2_CFG_KERNEL_SRF_8 0xE867E0519 520#define mmTPC2_CFG_KERNEL_SRF_9 0xE867E4521 522#define mmTPC2_CFG_KERNEL_SRF_10 0xE867E8523 524#define mmTPC2_CFG_KERNEL_SRF_11 0xE867EC525 526#define mmTPC2_CFG_KERNEL_SRF_12 0xE867F0527 528#define mmTPC2_CFG_KERNEL_SRF_13 0xE867F4529 530#define mmTPC2_CFG_KERNEL_SRF_14 0xE867F8531 532#define mmTPC2_CFG_KERNEL_SRF_15 0xE867FC533 534#define mmTPC2_CFG_KERNEL_SRF_16 0xE86800535 536#define mmTPC2_CFG_KERNEL_SRF_17 0xE86804537 538#define mmTPC2_CFG_KERNEL_SRF_18 0xE86808539 540#define mmTPC2_CFG_KERNEL_SRF_19 0xE8680C541 542#define mmTPC2_CFG_KERNEL_SRF_20 0xE86810543 544#define mmTPC2_CFG_KERNEL_SRF_21 0xE86814545 546#define mmTPC2_CFG_KERNEL_SRF_22 0xE86818547 548#define mmTPC2_CFG_KERNEL_SRF_23 0xE8681C549 550#define mmTPC2_CFG_KERNEL_SRF_24 0xE86820551 552#define mmTPC2_CFG_KERNEL_SRF_25 0xE86824553 554#define mmTPC2_CFG_KERNEL_SRF_26 0xE86828555 556#define mmTPC2_CFG_KERNEL_SRF_27 0xE8682C557 558#define mmTPC2_CFG_KERNEL_SRF_28 0xE86830559 560#define mmTPC2_CFG_KERNEL_SRF_29 0xE86834561 562#define mmTPC2_CFG_KERNEL_SRF_30 0xE86838563 564#define mmTPC2_CFG_KERNEL_SRF_31 0xE8683C565 566#define mmTPC2_CFG_ROUND_CSR 0xE868FC567 568#define mmTPC2_CFG_PROT 0xE86900569 570#define mmTPC2_CFG_SEMAPHORE 0xE86908571 572#define mmTPC2_CFG_VFLAGS 0xE8690C573 574#define mmTPC2_CFG_SFLAGS 0xE86910575 576#define mmTPC2_CFG_LFSR_POLYNOM 0xE86918577 578#define mmTPC2_CFG_STATUS 0xE8691C579 580#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86920581 582#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86924583 584#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8692C585 586#define mmTPC2_CFG_TPC_CMD 0xE86930587 588#define mmTPC2_CFG_TPC_EXECUTE 0xE86938589 590#define mmTPC2_CFG_TPC_STALL 0xE8693C591 592#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86940593 594#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86944595 596#define mmTPC2_CFG_RD_RATE_LIMIT 0xE86948597 598#define mmTPC2_CFG_WR_RATE_LIMIT 0xE86950599 600#define mmTPC2_CFG_MSS_CONFIG 0xE86954601 602#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86958603 604#define mmTPC2_CFG_TPC_INTR_MASK 0xE8695C605 606#define mmTPC2_CFG_WQ_CREDITS 0xE86960607 608#define mmTPC2_CFG_ARUSER_LO 0xE86964609 610#define mmTPC2_CFG_ARUSER_HI 0xE86968611 612#define mmTPC2_CFG_AWUSER_LO 0xE8696C613 614#define mmTPC2_CFG_AWUSER_HI 0xE86970615 616#define mmTPC2_CFG_OPCODE_EXEC 0xE86974617 618#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE86978619 620#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE8697C621 622#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE86980623 624#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE86984625 626#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE86988627 628#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE8698C629 630#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE86990631 632#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE86994633 634#define mmTPC2_CFG_TSB_CFG_MAX_SIZE 0xE86998635 636#define mmTPC2_CFG_TSB_CFG 0xE8699C637 638#define mmTPC2_CFG_DBGMEM_ADD 0xE869A0639 640#define mmTPC2_CFG_DBGMEM_DATA_WR 0xE869A4641 642#define mmTPC2_CFG_DBGMEM_DATA_RD 0xE869A8643 644#define mmTPC2_CFG_DBGMEM_CTRL 0xE869AC645 646#define mmTPC2_CFG_DBGMEM_RC 0xE869B0647 648#define mmTPC2_CFG_TSB_INFLIGHT_CNTR 0xE869B4649 650#define mmTPC2_CFG_WQ_INFLIGHT_CNTR 0xE869B8651 652#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR 0xE869BC653 654#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR 0xE869C0655 656#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR 0xE869C4657 658#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE869D0659 660#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE869D4661 662#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE869D8663 664#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE869DC665 666#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE869E0667 668#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE869E4669 670#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE869E8671 672#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE869EC673 674#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE869F0675 676#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE869F4677 678#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE869F8679 680#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE869FC681 682#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00683 684#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04685 686#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08687 688#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C689 690#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10691 692#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14693 694#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A18695 696#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A1C697 698#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A20699 700#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A24701 702#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A28703 704#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A2C705 706#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A30707 708#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A34709 710#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A38711 712#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A3C713 714#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A40715 716#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A44717 718#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A48719 720#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A4C721 722#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A50723 724#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A54725 726#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A58727 728#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A5C729 730#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A60731 732#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A64733 734#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A68735 736#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A6C737 738#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A70739 740#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A74741 742#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86A78743 744#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86A7C745 746#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86A80747 748#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86A84749 750#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86A88751 752#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86A8C753 754#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86A90755 756#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86A94757 758#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86A98759 760#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86A9C761 762#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AA0763 764#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86AA4765 766#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AA8767 768#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AAC769 770#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AB0771 772#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AB4773 774#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AB8775 776#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86ABC777 778#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86AC0779 780#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86AC4781 782#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86AC8783 784#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86ACC785 786#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86AD0787 788#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86AD4789 790#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86AD8791 792#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86ADC793 794#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86AE0795 796#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86AE4797 798#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86AE8799 800#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86AEC801 802#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86AF0803 804#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86AF4805 806#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86AF8807 808#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86AFC809 810#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B00811 812#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B04813 814#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B08815 816#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B0C817 818#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B10819 820#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B14821 822#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B18823 824#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B1C825 826#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B20827 828#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B24829 830#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B28831 832#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B2C833 834#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B30835 836#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B34837 838#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86B38839 840#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86B3C841 842#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86B40843 844#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86B44845 846#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86B48847 848#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86B4C849 850#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86B50851 852#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86B54853 854#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86B58855 856#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86B5C857 858#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86B60859 860#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86B64861 862#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86B68863 864#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86B6C865 866#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86B70867 868#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86B74869 870#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86B78871 872#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86B7C873 874#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86B80875 876#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86B84877 878#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86B88879 880#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86B8C881 882#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86B90883 884#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86B94885 886#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86B98887 888#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86B9C889 890#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86BA0891 892#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86BA4893 894#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86BA8895 896#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86BAC897 898#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86BB0899 900#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86BB4901 902#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86BB8903 904#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86BBC905 906#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE86BC0907 908#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE86BC4909 910#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE 0xE86BC8911 912#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE86BCC913 914#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE86BD0915 916#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE86BD4917 918#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE86BD8919 920#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE86BDC921 922#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE86BE0923 924#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE86BE4925 926#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE86BE8927 928#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE86BEC929 930#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE86BF0931 932#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE86BF4933 934#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE86BF8935 936#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE86BFC937 938#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE 0xE86C00939 940#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE86C04941 942#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE86C08943 944#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE86C0C945 946#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE86C10947 948#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE86C14949 950#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE86C18951 952#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE86C1C953 954#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE86C20955 956#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE86C24957 958#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE86C28959 960#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE86C2C961 962#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE86C30963 964#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE86C34965 966#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE 0xE86C38967 968#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE86C3C969 970#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE86C40971 972#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE86C44973 974#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE86C48975 976#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE86C4C977 978#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE86C50979 980#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE86C54981 982#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE86C58983 984#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE86C5C985 986#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE86C60987 988#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE86C64989 990#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE86C68991 992#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE86C6C993 994#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE 0xE86C70995 996#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE86C74997 998#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE86C78999 1000#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE86C7C1001 1002#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE86C801003 1004#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE86C841005 1006#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE86C881007 1008#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE86C8C1009 1010#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE86C901011 1012#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE86C941013 1014#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE86C981015 1016#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE86C9C1017 1018#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE86CA01019 1020#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE86CA41021 1022#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE 0xE86CA81023 1024#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE86CAC1025 1026#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE86CB01027 1028#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE86CB41029 1030#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE86CB81031 1032#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE86CBC1033 1034#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE86CC01035 1036#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE86CC41037 1038#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE86CC81039 1040#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE86CCC1041 1042#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE86CD01043 1044#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE86CD41045 1046#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE86CD81047 1048#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE86CDC1049 1050#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE 0xE86CE01051 1052#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE86CE41053 1054#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE86CE81055 1056#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE86CEC1057 1058#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE86CF01059 1060#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE86CF41061 1062#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE86CF81063 1064#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE86CFC1065 1066#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE86D001067 1068#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE86D041069 1070#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE86D081071 1072#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE86D0C1073 1074#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE86D101075 1076#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE86D141077 1078#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE 0xE86D181079 1080#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE86D1C1081 1082#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE86D201083 1084#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE86D241085 1086#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE86D281087 1088#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE86D2C1089 1090#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE86D301091 1092#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE86D341093 1094#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE86D381095 1096#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE86D3C1097 1098#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE86D401099 1100#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE86D441101 1102#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE86D481103 1104#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE86D4C1105 1106#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE 0xE86D501107 1108#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE86D541109 1110#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE86D581111 1112#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE86D5C1113 1114#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE86D601115 1116#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE86D641117 1118#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE86D681119 1120#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE86D6C1121 1122#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE86D701123 1124#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE86D741125 1126#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE86D781127 1128#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE86D7C1129 1130#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D801131 1132#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR 0xE86D841133 1134#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86D881135 1136#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86D8C1137 1138#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86D901139 1140#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86D941141 1142#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86D981143 1144#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86D9C1145 1146#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86DA01147 1148#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86DA41149 1150#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86DA81151 1152#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86DAC1153 1154#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86DB01155 1156#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86DB41157 1158#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86DB81159 1160#define mmTPC2_CFG_QM_KERNEL_ID 0xE86DBC1161 1162#define mmTPC2_CFG_QM_SRF_0 0xE86DC01163 1164#define mmTPC2_CFG_QM_SRF_1 0xE86DC41165 1166#define mmTPC2_CFG_QM_SRF_2 0xE86DC81167 1168#define mmTPC2_CFG_QM_SRF_3 0xE86DCC1169 1170#define mmTPC2_CFG_QM_SRF_4 0xE86DD01171 1172#define mmTPC2_CFG_QM_SRF_5 0xE86DD41173 1174#define mmTPC2_CFG_QM_SRF_6 0xE86DD81175 1176#define mmTPC2_CFG_QM_SRF_7 0xE86DDC1177 1178#define mmTPC2_CFG_QM_SRF_8 0xE86DE01179 1180#define mmTPC2_CFG_QM_SRF_9 0xE86DE41181 1182#define mmTPC2_CFG_QM_SRF_10 0xE86DE81183 1184#define mmTPC2_CFG_QM_SRF_11 0xE86DEC1185 1186#define mmTPC2_CFG_QM_SRF_12 0xE86DF01187 1188#define mmTPC2_CFG_QM_SRF_13 0xE86DF41189 1190#define mmTPC2_CFG_QM_SRF_14 0xE86DF81191 1192#define mmTPC2_CFG_QM_SRF_15 0xE86DFC1193 1194#define mmTPC2_CFG_QM_SRF_16 0xE86E001195 1196#define mmTPC2_CFG_QM_SRF_17 0xE86E041197 1198#define mmTPC2_CFG_QM_SRF_18 0xE86E081199 1200#define mmTPC2_CFG_QM_SRF_19 0xE86E0C1201 1202#define mmTPC2_CFG_QM_SRF_20 0xE86E101203 1204#define mmTPC2_CFG_QM_SRF_21 0xE86E141205 1206#define mmTPC2_CFG_QM_SRF_22 0xE86E181207 1208#define mmTPC2_CFG_QM_SRF_23 0xE86E1C1209 1210#define mmTPC2_CFG_QM_SRF_24 0xE86E201211 1212#define mmTPC2_CFG_QM_SRF_25 0xE86E241213 1214#define mmTPC2_CFG_QM_SRF_26 0xE86E281215 1216#define mmTPC2_CFG_QM_SRF_27 0xE86E2C1217 1218#define mmTPC2_CFG_QM_SRF_28 0xE86E301219 1220#define mmTPC2_CFG_QM_SRF_29 0xE86E341221 1222#define mmTPC2_CFG_QM_SRF_30 0xE86E381223 1224#define mmTPC2_CFG_QM_SRF_31 0xE86E3C1225 1226#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */1227