1227 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC4_CFG_REGS_H_14#define ASIC_REG_TPC4_CFG_REGS_H_15 16/*17 *****************************************18 * TPC4_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF0640023 24#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF0640425 26#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF0640827 28#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C29 30#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF0641031 32#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF0641433 34#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF0641835 36#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF0641C37 38#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF0642039 40#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF0642441 42#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF0642843 44#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF0642C45 46#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF0643047 48#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF0643449 50#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF0643851 52#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF0643C53 54#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF0644055 56#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF0644457 58#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF0644859 60#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF0644C61 62#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF0645063 64#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF0645465 66#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF0645867 68#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF0645C69 70#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF0646071 72#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF0646473 74#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF0646875 76#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF0646C77 78#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF0647079 80#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF0647481 82#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF0647883 84#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF0647C85 86#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF0648087 88#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF0648489 90#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF0648891 92#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF0648C93 94#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF0649095 96#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF0649497 98#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF0649899 100#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF0649C101 102#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064A0103 104#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064A4105 106#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064A8107 108#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064AC109 110#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064B0111 112#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064B4113 114#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064B8115 116#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064BC117 118#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF064C0119 120#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF064C4121 122#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF064C8123 124#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF064CC125 126#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF064D0127 128#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF064D4129 130#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF064D8131 132#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF064DC133 134#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF064E0135 136#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF064E4137 138#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF064E8139 140#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF064EC141 142#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF064F0143 144#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF064F4145 146#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF064F8147 148#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF064FC149 150#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06500151 152#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF06504153 154#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06508155 156#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF0650C157 158#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06510159 160#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06514161 162#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF06518163 164#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF0651C165 166#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06520167 168#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06524169 170#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF06528171 172#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF0652C173 174#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06530175 176#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF06534177 178#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF06538179 180#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF0653C181 182#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF06540183 184#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF06544185 186#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF06548187 188#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF0654C189 190#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF06550191 192#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF06554193 194#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF06558195 196#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF0655C197 198#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF06560199 200#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF06564201 202#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF06568203 204#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF0656C205 206#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF06570207 208#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF06574209 210#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF06578211 212#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF0657C213 214#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06580215 216#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF06584217 218#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06588219 220#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF0658C221 222#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF06590223 224#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06594225 226#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06598227 228#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF0659C229 230#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF065A0231 232#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF065A4233 234#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF065A8235 236#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF065AC237 238#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF065B0239 240#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF065B4241 242#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF065B8243 244#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF065BC245 246#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF065C0247 248#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF065C4249 250#define mmTPC4_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF065C8251 252#define mmTPC4_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF065CC253 254#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF065D0255 256#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF065D4257 258#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF065D8259 260#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF065DC261 262#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF065E0263 264#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF065E4265 266#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF065E8267 268#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF065EC269 270#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF065F0271 272#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF065F4273 274#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF065F8275 276#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF065FC277 278#define mmTPC4_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF06600279 280#define mmTPC4_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF06604281 282#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF06608283 284#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF0660C285 286#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF06610287 288#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF06614289 290#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF06618291 292#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF0661C293 294#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF06620295 296#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF06624297 298#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF06628299 300#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF0662C301 302#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF06630303 304#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF06634305 306#define mmTPC4_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF06638307 308#define mmTPC4_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF0663C309 310#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF06640311 312#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF06644313 314#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF06648315 316#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF0664C317 318#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF06650319 320#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF06654321 322#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF06658323 324#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF0665C325 326#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF06660327 328#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF06664329 330#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF06668331 332#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF0666C333 334#define mmTPC4_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF06670335 336#define mmTPC4_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF06674337 338#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF06678339 340#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF0667C341 342#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF06680343 344#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF06684345 346#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF06688347 348#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF0668C349 350#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF06690351 352#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF06694353 354#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF06698355 356#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF0669C357 358#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF066A0359 360#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF066A4361 362#define mmTPC4_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF066A8363 364#define mmTPC4_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF066AC365 366#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF066B0367 368#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF066B4369 370#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF066B8371 372#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF066BC373 374#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF066C0375 376#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF066C4377 378#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF066C8379 380#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF066CC381 382#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF066D0383 384#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF066D4385 386#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF066D8387 388#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF066DC389 390#define mmTPC4_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF066E0391 392#define mmTPC4_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF066E4393 394#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF066E8395 396#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF066EC397 398#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF066F0399 400#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF066F4401 402#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF066F8403 404#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF066FC405 406#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF06700407 408#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF06704409 410#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF06708411 412#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF0670C413 414#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF06710415 416#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF06714417 418#define mmTPC4_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF06718419 420#define mmTPC4_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF0671C421 422#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF06720423 424#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF06724425 426#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF06728427 428#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF0672C429 430#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF06730431 432#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF06734433 434#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF06738435 436#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF0673C437 438#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF06740439 440#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF06744441 442#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF06748443 444#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF0674C445 446#define mmTPC4_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF06750447 448#define mmTPC4_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF06754449 450#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF06758451 452#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF0675C453 454#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF06760455 456#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF06764457 458#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF06768459 460#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF0676C461 462#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF06770463 464#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF06774465 466#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF06778467 468#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF0677C469 470#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06780471 472#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF06784473 474#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06788475 476#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF0678C477 478#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06790479 480#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF06794481 482#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06798483 484#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF0679C485 486#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF067A0487 488#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF067A4489 490#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF067A8491 492#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF067AC493 494#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF067B0495 496#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF067B4497 498#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF067B8499 500#define mmTPC4_CFG_KERNEL_KERNEL_ID 0xF067BC501 502#define mmTPC4_CFG_KERNEL_SRF_0 0xF067C0503 504#define mmTPC4_CFG_KERNEL_SRF_1 0xF067C4505 506#define mmTPC4_CFG_KERNEL_SRF_2 0xF067C8507 508#define mmTPC4_CFG_KERNEL_SRF_3 0xF067CC509 510#define mmTPC4_CFG_KERNEL_SRF_4 0xF067D0511 512#define mmTPC4_CFG_KERNEL_SRF_5 0xF067D4513 514#define mmTPC4_CFG_KERNEL_SRF_6 0xF067D8515 516#define mmTPC4_CFG_KERNEL_SRF_7 0xF067DC517 518#define mmTPC4_CFG_KERNEL_SRF_8 0xF067E0519 520#define mmTPC4_CFG_KERNEL_SRF_9 0xF067E4521 522#define mmTPC4_CFG_KERNEL_SRF_10 0xF067E8523 524#define mmTPC4_CFG_KERNEL_SRF_11 0xF067EC525 526#define mmTPC4_CFG_KERNEL_SRF_12 0xF067F0527 528#define mmTPC4_CFG_KERNEL_SRF_13 0xF067F4529 530#define mmTPC4_CFG_KERNEL_SRF_14 0xF067F8531 532#define mmTPC4_CFG_KERNEL_SRF_15 0xF067FC533 534#define mmTPC4_CFG_KERNEL_SRF_16 0xF06800535 536#define mmTPC4_CFG_KERNEL_SRF_17 0xF06804537 538#define mmTPC4_CFG_KERNEL_SRF_18 0xF06808539 540#define mmTPC4_CFG_KERNEL_SRF_19 0xF0680C541 542#define mmTPC4_CFG_KERNEL_SRF_20 0xF06810543 544#define mmTPC4_CFG_KERNEL_SRF_21 0xF06814545 546#define mmTPC4_CFG_KERNEL_SRF_22 0xF06818547 548#define mmTPC4_CFG_KERNEL_SRF_23 0xF0681C549 550#define mmTPC4_CFG_KERNEL_SRF_24 0xF06820551 552#define mmTPC4_CFG_KERNEL_SRF_25 0xF06824553 554#define mmTPC4_CFG_KERNEL_SRF_26 0xF06828555 556#define mmTPC4_CFG_KERNEL_SRF_27 0xF0682C557 558#define mmTPC4_CFG_KERNEL_SRF_28 0xF06830559 560#define mmTPC4_CFG_KERNEL_SRF_29 0xF06834561 562#define mmTPC4_CFG_KERNEL_SRF_30 0xF06838563 564#define mmTPC4_CFG_KERNEL_SRF_31 0xF0683C565 566#define mmTPC4_CFG_ROUND_CSR 0xF068FC567 568#define mmTPC4_CFG_PROT 0xF06900569 570#define mmTPC4_CFG_SEMAPHORE 0xF06908571 572#define mmTPC4_CFG_VFLAGS 0xF0690C573 574#define mmTPC4_CFG_SFLAGS 0xF06910575 576#define mmTPC4_CFG_LFSR_POLYNOM 0xF06918577 578#define mmTPC4_CFG_STATUS 0xF0691C579 580#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06920581 582#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06924583 584#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0692C585 586#define mmTPC4_CFG_TPC_CMD 0xF06930587 588#define mmTPC4_CFG_TPC_EXECUTE 0xF06938589 590#define mmTPC4_CFG_TPC_STALL 0xF0693C591 592#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06940593 594#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06944595 596#define mmTPC4_CFG_RD_RATE_LIMIT 0xF06948597 598#define mmTPC4_CFG_WR_RATE_LIMIT 0xF06950599 600#define mmTPC4_CFG_MSS_CONFIG 0xF06954601 602#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06958603 604#define mmTPC4_CFG_TPC_INTR_MASK 0xF0695C605 606#define mmTPC4_CFG_WQ_CREDITS 0xF06960607 608#define mmTPC4_CFG_ARUSER_LO 0xF06964609 610#define mmTPC4_CFG_ARUSER_HI 0xF06968611 612#define mmTPC4_CFG_AWUSER_LO 0xF0696C613 614#define mmTPC4_CFG_AWUSER_HI 0xF06970615 616#define mmTPC4_CFG_OPCODE_EXEC 0xF06974617 618#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF06978619 620#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF0697C621 622#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF06980623 624#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF06984625 626#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF06988627 628#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF0698C629 630#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF06990631 632#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF06994633 634#define mmTPC4_CFG_TSB_CFG_MAX_SIZE 0xF06998635 636#define mmTPC4_CFG_TSB_CFG 0xF0699C637 638#define mmTPC4_CFG_DBGMEM_ADD 0xF069A0639 640#define mmTPC4_CFG_DBGMEM_DATA_WR 0xF069A4641 642#define mmTPC4_CFG_DBGMEM_DATA_RD 0xF069A8643 644#define mmTPC4_CFG_DBGMEM_CTRL 0xF069AC645 646#define mmTPC4_CFG_DBGMEM_RC 0xF069B0647 648#define mmTPC4_CFG_TSB_INFLIGHT_CNTR 0xF069B4649 650#define mmTPC4_CFG_WQ_INFLIGHT_CNTR 0xF069B8651 652#define mmTPC4_CFG_WQ_LBW_TOTAL_CNTR 0xF069BC653 654#define mmTPC4_CFG_WQ_HBW_TOTAL_CNTR 0xF069C0655 656#define mmTPC4_CFG_IRQ_OCCOUPY_CNTR 0xF069C4657 658#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF069D0659 660#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF069D4661 662#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF069D8663 664#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF069DC665 666#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF069E0667 668#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF069E4669 670#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF069E8671 672#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF069EC673 674#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF069F0675 676#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF069F4677 678#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF069F8679 680#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF069FC681 682#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00683 684#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04685 686#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08687 688#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C689 690#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10691 692#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14693 694#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A18695 696#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A1C697 698#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A20699 700#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A24701 702#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A28703 704#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A2C705 706#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A30707 708#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A34709 710#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A38711 712#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A3C713 714#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A40715 716#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A44717 718#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A48719 720#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A4C721 722#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A50723 724#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A54725 726#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A58727 728#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A5C729 730#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A60731 732#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A64733 734#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A68735 736#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A6C737 738#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A70739 740#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A74741 742#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06A78743 744#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06A7C745 746#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06A80747 748#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06A84749 750#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06A88751 752#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06A8C753 754#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06A90755 756#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06A94757 758#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06A98759 760#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06A9C761 762#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AA0763 764#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06AA4765 766#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AA8767 768#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AAC769 770#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AB0771 772#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AB4773 774#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AB8775 776#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06ABC777 778#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06AC0779 780#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06AC4781 782#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06AC8783 784#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06ACC785 786#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06AD0787 788#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06AD4789 790#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06AD8791 792#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06ADC793 794#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06AE0795 796#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06AE4797 798#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06AE8799 800#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06AEC801 802#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06AF0803 804#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06AF4805 806#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06AF8807 808#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06AFC809 810#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B00811 812#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B04813 814#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B08815 816#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B0C817 818#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B10819 820#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B14821 822#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B18823 824#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B1C825 826#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B20827 828#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B24829 830#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B28831 832#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B2C833 834#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B30835 836#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B34837 838#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06B38839 840#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06B3C841 842#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06B40843 844#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06B44845 846#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06B48847 848#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06B4C849 850#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06B50851 852#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06B54853 854#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06B58855 856#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06B5C857 858#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06B60859 860#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06B64861 862#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06B68863 864#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06B6C865 866#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06B70867 868#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06B74869 870#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06B78871 872#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06B7C873 874#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06B80875 876#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06B84877 878#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06B88879 880#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06B8C881 882#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06B90883 884#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06B94885 886#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06B98887 888#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06B9C889 890#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06BA0891 892#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06BA4893 894#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06BA8895 896#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06BAC897 898#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06BB0899 900#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06BB4901 902#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06BB8903 904#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06BBC905 906#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF06BC0907 908#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF06BC4909 910#define mmTPC4_CFG_QM_TENSOR_8_PADDING_VALUE 0xF06BC8911 912#define mmTPC4_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF06BCC913 914#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF06BD0915 916#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF06BD4917 918#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF06BD8919 920#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF06BDC921 922#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF06BE0923 924#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF06BE4925 926#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF06BE8927 928#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF06BEC929 930#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF06BF0931 932#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF06BF4933 934#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF06BF8935 936#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF06BFC937 938#define mmTPC4_CFG_QM_TENSOR_9_PADDING_VALUE 0xF06C00939 940#define mmTPC4_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF06C04941 942#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF06C08943 944#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF06C0C945 946#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF06C10947 948#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF06C14949 950#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF06C18951 952#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF06C1C953 954#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF06C20955 956#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF06C24957 958#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF06C28959 960#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF06C2C961 962#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF06C30963 964#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF06C34965 966#define mmTPC4_CFG_QM_TENSOR_10_PADDING_VALUE 0xF06C38967 968#define mmTPC4_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF06C3C969 970#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF06C40971 972#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF06C44973 974#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF06C48975 976#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF06C4C977 978#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF06C50979 980#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF06C54981 982#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF06C58983 984#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF06C5C985 986#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF06C60987 988#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF06C64989 990#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF06C68991 992#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF06C6C993 994#define mmTPC4_CFG_QM_TENSOR_11_PADDING_VALUE 0xF06C70995 996#define mmTPC4_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF06C74997 998#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF06C78999 1000#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF06C7C1001 1002#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF06C801003 1004#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF06C841005 1006#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF06C881007 1008#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF06C8C1009 1010#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF06C901011 1012#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF06C941013 1014#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF06C981015 1016#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF06C9C1017 1018#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF06CA01019 1020#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF06CA41021 1022#define mmTPC4_CFG_QM_TENSOR_12_PADDING_VALUE 0xF06CA81023 1024#define mmTPC4_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF06CAC1025 1026#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF06CB01027 1028#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF06CB41029 1030#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF06CB81031 1032#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF06CBC1033 1034#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF06CC01035 1036#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF06CC41037 1038#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF06CC81039 1040#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF06CCC1041 1042#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF06CD01043 1044#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF06CD41045 1046#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF06CD81047 1048#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF06CDC1049 1050#define mmTPC4_CFG_QM_TENSOR_13_PADDING_VALUE 0xF06CE01051 1052#define mmTPC4_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF06CE41053 1054#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF06CE81055 1056#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF06CEC1057 1058#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF06CF01059 1060#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF06CF41061 1062#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF06CF81063 1064#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF06CFC1065 1066#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF06D001067 1068#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF06D041069 1070#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF06D081071 1072#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF06D0C1073 1074#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF06D101075 1076#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF06D141077 1078#define mmTPC4_CFG_QM_TENSOR_14_PADDING_VALUE 0xF06D181079 1080#define mmTPC4_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF06D1C1081 1082#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF06D201083 1084#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF06D241085 1086#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF06D281087 1088#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF06D2C1089 1090#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF06D301091 1092#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF06D341093 1094#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF06D381095 1096#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF06D3C1097 1098#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF06D401099 1100#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF06D441101 1102#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF06D481103 1104#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF06D4C1105 1106#define mmTPC4_CFG_QM_TENSOR_15_PADDING_VALUE 0xF06D501107 1108#define mmTPC4_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF06D541109 1110#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF06D581111 1112#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF06D5C1113 1114#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF06D601115 1116#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF06D641117 1118#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF06D681119 1120#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF06D6C1121 1122#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF06D701123 1124#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF06D741125 1126#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF06D781127 1128#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF06D7C1129 1130#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D801131 1132#define mmTPC4_CFG_QM_SYNC_OBJECT_ADDR 0xF06D841133 1134#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06D881135 1136#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06D8C1137 1138#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06D901139 1140#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06D941141 1142#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06D981143 1144#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06D9C1145 1146#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06DA01147 1148#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06DA41149 1150#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06DA81151 1152#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06DAC1153 1154#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06DB01155 1156#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06DB41157 1158#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06DB81159 1160#define mmTPC4_CFG_QM_KERNEL_ID 0xF06DBC1161 1162#define mmTPC4_CFG_QM_SRF_0 0xF06DC01163 1164#define mmTPC4_CFG_QM_SRF_1 0xF06DC41165 1166#define mmTPC4_CFG_QM_SRF_2 0xF06DC81167 1168#define mmTPC4_CFG_QM_SRF_3 0xF06DCC1169 1170#define mmTPC4_CFG_QM_SRF_4 0xF06DD01171 1172#define mmTPC4_CFG_QM_SRF_5 0xF06DD41173 1174#define mmTPC4_CFG_QM_SRF_6 0xF06DD81175 1176#define mmTPC4_CFG_QM_SRF_7 0xF06DDC1177 1178#define mmTPC4_CFG_QM_SRF_8 0xF06DE01179 1180#define mmTPC4_CFG_QM_SRF_9 0xF06DE41181 1182#define mmTPC4_CFG_QM_SRF_10 0xF06DE81183 1184#define mmTPC4_CFG_QM_SRF_11 0xF06DEC1185 1186#define mmTPC4_CFG_QM_SRF_12 0xF06DF01187 1188#define mmTPC4_CFG_QM_SRF_13 0xF06DF41189 1190#define mmTPC4_CFG_QM_SRF_14 0xF06DF81191 1192#define mmTPC4_CFG_QM_SRF_15 0xF06DFC1193 1194#define mmTPC4_CFG_QM_SRF_16 0xF06E001195 1196#define mmTPC4_CFG_QM_SRF_17 0xF06E041197 1198#define mmTPC4_CFG_QM_SRF_18 0xF06E081199 1200#define mmTPC4_CFG_QM_SRF_19 0xF06E0C1201 1202#define mmTPC4_CFG_QM_SRF_20 0xF06E101203 1204#define mmTPC4_CFG_QM_SRF_21 0xF06E141205 1206#define mmTPC4_CFG_QM_SRF_22 0xF06E181207 1208#define mmTPC4_CFG_QM_SRF_23 0xF06E1C1209 1210#define mmTPC4_CFG_QM_SRF_24 0xF06E201211 1212#define mmTPC4_CFG_QM_SRF_25 0xF06E241213 1214#define mmTPC4_CFG_QM_SRF_26 0xF06E281215 1216#define mmTPC4_CFG_QM_SRF_27 0xF06E2C1217 1218#define mmTPC4_CFG_QM_SRF_28 0xF06E301219 1220#define mmTPC4_CFG_QM_SRF_29 0xF06E341221 1222#define mmTPC4_CFG_QM_SRF_30 0xF06E381223 1224#define mmTPC4_CFG_QM_SRF_31 0xF06E3C1225 1226#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */1227