1227 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC5_CFG_REGS_H_14#define ASIC_REG_TPC5_CFG_REGS_H_15 16/*17 *****************************************18 * TPC5_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF4640023 24#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF4640425 26#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF4640827 28#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C29 30#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF4641031 32#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF4641433 34#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF4641835 36#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4641C37 38#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF4642039 40#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF4642441 42#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF4642843 44#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4642C45 46#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF4643047 48#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF4643449 50#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF4643851 52#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4643C53 54#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF4644055 56#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF4644457 58#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF4644859 60#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4644C61 62#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF4645063 64#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF4645465 66#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF4645867 68#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4645C69 70#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF4646071 72#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF4646473 74#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF4646875 76#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4646C77 78#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF4647079 80#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF4647481 82#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF4647883 84#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF4647C85 86#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF4648087 88#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF4648489 90#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF4648891 92#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF4648C93 94#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF4649095 96#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF4649497 98#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF4649899 100#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF4649C101 102#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464A0103 104#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464A4105 106#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464A8107 108#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464AC109 110#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464B0111 112#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464B4113 114#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464B8115 116#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464BC117 118#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF464C0119 120#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF464C4121 122#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF464C8123 124#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF464CC125 126#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF464D0127 128#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF464D4129 130#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF464D8131 132#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF464DC133 134#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF464E0135 136#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF464E4137 138#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF464E8139 140#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF464EC141 142#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF464F0143 144#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF464F4145 146#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF464F8147 148#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF464FC149 150#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46500151 152#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF46504153 154#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46508155 156#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF4650C157 158#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46510159 160#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46514161 162#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF46518163 164#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF4651C165 166#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46520167 168#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46524169 170#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF46528171 172#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF4652C173 174#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46530175 176#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF46534177 178#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF46538179 180#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF4653C181 182#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF46540183 184#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF46544185 186#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF46548187 188#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF4654C189 190#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF46550191 192#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF46554193 194#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF46558195 196#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF4655C197 198#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF46560199 200#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF46564201 202#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF46568203 204#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF4656C205 206#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF46570207 208#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF46574209 210#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF46578211 212#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF4657C213 214#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46580215 216#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF46584217 218#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46588219 220#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF4658C221 222#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF46590223 224#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46594225 226#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46598227 228#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF4659C229 230#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF465A0231 232#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF465A4233 234#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF465A8235 236#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF465AC237 238#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF465B0239 240#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF465B4241 242#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF465B8243 244#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF465BC245 246#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF465C0247 248#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF465C4249 250#define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF465C8251 252#define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF465CC253 254#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF465D0255 256#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF465D4257 258#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF465D8259 260#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF465DC261 262#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF465E0263 264#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF465E4265 266#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF465E8267 268#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF465EC269 270#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF465F0271 272#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF465F4273 274#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF465F8275 276#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF465FC277 278#define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF46600279 280#define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF46604281 282#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF46608283 284#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF4660C285 286#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF46610287 288#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF46614289 290#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF46618291 292#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF4661C293 294#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF46620295 296#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF46624297 298#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF46628299 300#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF4662C301 302#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF46630303 304#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF46634305 306#define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF46638307 308#define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF4663C309 310#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF46640311 312#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF46644313 314#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF46648315 316#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF4664C317 318#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF46650319 320#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF46654321 322#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF46658323 324#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF4665C325 326#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF46660327 328#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF46664329 330#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF46668331 332#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF4666C333 334#define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF46670335 336#define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF46674337 338#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF46678339 340#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF4667C341 342#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF46680343 344#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF46684345 346#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF46688347 348#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF4668C349 350#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF46690351 352#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF46694353 354#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF46698355 356#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF4669C357 358#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF466A0359 360#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF466A4361 362#define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF466A8363 364#define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF466AC365 366#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF466B0367 368#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF466B4369 370#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF466B8371 372#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF466BC373 374#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF466C0375 376#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF466C4377 378#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF466C8379 380#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF466CC381 382#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF466D0383 384#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF466D4385 386#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF466D8387 388#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF466DC389 390#define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF466E0391 392#define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF466E4393 394#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF466E8395 396#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF466EC397 398#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF466F0399 400#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF466F4401 402#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF466F8403 404#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF466FC405 406#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF46700407 408#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF46704409 410#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF46708411 412#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF4670C413 414#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF46710415 416#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF46714417 418#define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF46718419 420#define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF4671C421 422#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF46720423 424#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF46724425 426#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF46728427 428#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF4672C429 430#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF46730431 432#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF46734433 434#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF46738435 436#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF4673C437 438#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF46740439 440#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF46744441 442#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF46748443 444#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF4674C445 446#define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF46750447 448#define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF46754449 450#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF46758451 452#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF4675C453 454#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF46760455 456#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF46764457 458#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF46768459 460#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF4676C461 462#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF46770463 464#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF46774465 466#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF46778467 468#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF4677C469 470#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46780471 472#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF46784473 474#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46788475 476#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF4678C477 478#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46790479 480#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF46794481 482#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46798483 484#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF4679C485 486#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF467A0487 488#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF467A4489 490#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF467A8491 492#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF467AC493 494#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF467B0495 496#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF467B4497 498#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF467B8499 500#define mmTPC5_CFG_KERNEL_KERNEL_ID 0xF467BC501 502#define mmTPC5_CFG_KERNEL_SRF_0 0xF467C0503 504#define mmTPC5_CFG_KERNEL_SRF_1 0xF467C4505 506#define mmTPC5_CFG_KERNEL_SRF_2 0xF467C8507 508#define mmTPC5_CFG_KERNEL_SRF_3 0xF467CC509 510#define mmTPC5_CFG_KERNEL_SRF_4 0xF467D0511 512#define mmTPC5_CFG_KERNEL_SRF_5 0xF467D4513 514#define mmTPC5_CFG_KERNEL_SRF_6 0xF467D8515 516#define mmTPC5_CFG_KERNEL_SRF_7 0xF467DC517 518#define mmTPC5_CFG_KERNEL_SRF_8 0xF467E0519 520#define mmTPC5_CFG_KERNEL_SRF_9 0xF467E4521 522#define mmTPC5_CFG_KERNEL_SRF_10 0xF467E8523 524#define mmTPC5_CFG_KERNEL_SRF_11 0xF467EC525 526#define mmTPC5_CFG_KERNEL_SRF_12 0xF467F0527 528#define mmTPC5_CFG_KERNEL_SRF_13 0xF467F4529 530#define mmTPC5_CFG_KERNEL_SRF_14 0xF467F8531 532#define mmTPC5_CFG_KERNEL_SRF_15 0xF467FC533 534#define mmTPC5_CFG_KERNEL_SRF_16 0xF46800535 536#define mmTPC5_CFG_KERNEL_SRF_17 0xF46804537 538#define mmTPC5_CFG_KERNEL_SRF_18 0xF46808539 540#define mmTPC5_CFG_KERNEL_SRF_19 0xF4680C541 542#define mmTPC5_CFG_KERNEL_SRF_20 0xF46810543 544#define mmTPC5_CFG_KERNEL_SRF_21 0xF46814545 546#define mmTPC5_CFG_KERNEL_SRF_22 0xF46818547 548#define mmTPC5_CFG_KERNEL_SRF_23 0xF4681C549 550#define mmTPC5_CFG_KERNEL_SRF_24 0xF46820551 552#define mmTPC5_CFG_KERNEL_SRF_25 0xF46824553 554#define mmTPC5_CFG_KERNEL_SRF_26 0xF46828555 556#define mmTPC5_CFG_KERNEL_SRF_27 0xF4682C557 558#define mmTPC5_CFG_KERNEL_SRF_28 0xF46830559 560#define mmTPC5_CFG_KERNEL_SRF_29 0xF46834561 562#define mmTPC5_CFG_KERNEL_SRF_30 0xF46838563 564#define mmTPC5_CFG_KERNEL_SRF_31 0xF4683C565 566#define mmTPC5_CFG_ROUND_CSR 0xF468FC567 568#define mmTPC5_CFG_PROT 0xF46900569 570#define mmTPC5_CFG_SEMAPHORE 0xF46908571 572#define mmTPC5_CFG_VFLAGS 0xF4690C573 574#define mmTPC5_CFG_SFLAGS 0xF46910575 576#define mmTPC5_CFG_LFSR_POLYNOM 0xF46918577 578#define mmTPC5_CFG_STATUS 0xF4691C579 580#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46920581 582#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46924583 584#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4692C585 586#define mmTPC5_CFG_TPC_CMD 0xF46930587 588#define mmTPC5_CFG_TPC_EXECUTE 0xF46938589 590#define mmTPC5_CFG_TPC_STALL 0xF4693C591 592#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46940593 594#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46944595 596#define mmTPC5_CFG_RD_RATE_LIMIT 0xF46948597 598#define mmTPC5_CFG_WR_RATE_LIMIT 0xF46950599 600#define mmTPC5_CFG_MSS_CONFIG 0xF46954601 602#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46958603 604#define mmTPC5_CFG_TPC_INTR_MASK 0xF4695C605 606#define mmTPC5_CFG_WQ_CREDITS 0xF46960607 608#define mmTPC5_CFG_ARUSER_LO 0xF46964609 610#define mmTPC5_CFG_ARUSER_HI 0xF46968611 612#define mmTPC5_CFG_AWUSER_LO 0xF4696C613 614#define mmTPC5_CFG_AWUSER_HI 0xF46970615 616#define mmTPC5_CFG_OPCODE_EXEC 0xF46974617 618#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF46978619 620#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF4697C621 622#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF46980623 624#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF46984625 626#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF46988627 628#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF4698C629 630#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF46990631 632#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF46994633 634#define mmTPC5_CFG_TSB_CFG_MAX_SIZE 0xF46998635 636#define mmTPC5_CFG_TSB_CFG 0xF4699C637 638#define mmTPC5_CFG_DBGMEM_ADD 0xF469A0639 640#define mmTPC5_CFG_DBGMEM_DATA_WR 0xF469A4641 642#define mmTPC5_CFG_DBGMEM_DATA_RD 0xF469A8643 644#define mmTPC5_CFG_DBGMEM_CTRL 0xF469AC645 646#define mmTPC5_CFG_DBGMEM_RC 0xF469B0647 648#define mmTPC5_CFG_TSB_INFLIGHT_CNTR 0xF469B4649 650#define mmTPC5_CFG_WQ_INFLIGHT_CNTR 0xF469B8651 652#define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR 0xF469BC653 654#define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR 0xF469C0655 656#define mmTPC5_CFG_IRQ_OCCOUPY_CNTR 0xF469C4657 658#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF469D0659 660#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF469D4661 662#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF469D8663 664#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF469DC665 666#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF469E0667 668#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF469E4669 670#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF469E8671 672#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF469EC673 674#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF469F0675 676#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF469F4677 678#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF469F8679 680#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF469FC681 682#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00683 684#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04685 686#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08687 688#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C689 690#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10691 692#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14693 694#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A18695 696#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A1C697 698#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A20699 700#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A24701 702#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A28703 704#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A2C705 706#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A30707 708#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A34709 710#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A38711 712#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A3C713 714#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A40715 716#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A44717 718#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A48719 720#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A4C721 722#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A50723 724#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A54725 726#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A58727 728#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A5C729 730#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A60731 732#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A64733 734#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A68735 736#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A6C737 738#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A70739 740#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A74741 742#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46A78743 744#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46A7C745 746#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46A80747 748#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46A84749 750#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46A88751 752#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46A8C753 754#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46A90755 756#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46A94757 758#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46A98759 760#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46A9C761 762#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AA0763 764#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46AA4765 766#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AA8767 768#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AAC769 770#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AB0771 772#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AB4773 774#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AB8775 776#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46ABC777 778#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46AC0779 780#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46AC4781 782#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46AC8783 784#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46ACC785 786#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46AD0787 788#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46AD4789 790#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46AD8791 792#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46ADC793 794#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46AE0795 796#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46AE4797 798#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46AE8799 800#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46AEC801 802#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46AF0803 804#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46AF4805 806#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46AF8807 808#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46AFC809 810#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B00811 812#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B04813 814#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B08815 816#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B0C817 818#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B10819 820#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B14821 822#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B18823 824#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B1C825 826#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B20827 828#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B24829 830#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B28831 832#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B2C833 834#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B30835 836#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B34837 838#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46B38839 840#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46B3C841 842#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46B40843 844#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46B44845 846#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46B48847 848#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46B4C849 850#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46B50851 852#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46B54853 854#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46B58855 856#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46B5C857 858#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46B60859 860#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46B64861 862#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46B68863 864#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46B6C865 866#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46B70867 868#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46B74869 870#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46B78871 872#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46B7C873 874#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46B80875 876#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46B84877 878#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46B88879 880#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46B8C881 882#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46B90883 884#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46B94885 886#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46B98887 888#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46B9C889 890#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46BA0891 892#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46BA4893 894#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46BA8895 896#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46BAC897 898#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46BB0899 900#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46BB4901 902#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46BB8903 904#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46BBC905 906#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF46BC0907 908#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF46BC4909 910#define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE 0xF46BC8911 912#define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF46BCC913 914#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF46BD0915 916#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF46BD4917 918#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF46BD8919 920#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF46BDC921 922#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF46BE0923 924#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF46BE4925 926#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF46BE8927 928#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF46BEC929 930#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF46BF0931 932#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF46BF4933 934#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF46BF8935 936#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF46BFC937 938#define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE 0xF46C00939 940#define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF46C04941 942#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF46C08943 944#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF46C0C945 946#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF46C10947 948#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF46C14949 950#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF46C18951 952#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF46C1C953 954#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF46C20955 956#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF46C24957 958#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF46C28959 960#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF46C2C961 962#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF46C30963 964#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF46C34965 966#define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE 0xF46C38967 968#define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF46C3C969 970#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF46C40971 972#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF46C44973 974#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF46C48975 976#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF46C4C977 978#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF46C50979 980#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF46C54981 982#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF46C58983 984#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF46C5C985 986#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF46C60987 988#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF46C64989 990#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF46C68991 992#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF46C6C993 994#define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE 0xF46C70995 996#define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF46C74997 998#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF46C78999 1000#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF46C7C1001 1002#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF46C801003 1004#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF46C841005 1006#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF46C881007 1008#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF46C8C1009 1010#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF46C901011 1012#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF46C941013 1014#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF46C981015 1016#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF46C9C1017 1018#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF46CA01019 1020#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF46CA41021 1022#define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE 0xF46CA81023 1024#define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF46CAC1025 1026#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF46CB01027 1028#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF46CB41029 1030#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF46CB81031 1032#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF46CBC1033 1034#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF46CC01035 1036#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF46CC41037 1038#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF46CC81039 1040#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF46CCC1041 1042#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF46CD01043 1044#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF46CD41045 1046#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF46CD81047 1048#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF46CDC1049 1050#define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE 0xF46CE01051 1052#define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF46CE41053 1054#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF46CE81055 1056#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF46CEC1057 1058#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF46CF01059 1060#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF46CF41061 1062#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF46CF81063 1064#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF46CFC1065 1066#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF46D001067 1068#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF46D041069 1070#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF46D081071 1072#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF46D0C1073 1074#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF46D101075 1076#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF46D141077 1078#define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE 0xF46D181079 1080#define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF46D1C1081 1082#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF46D201083 1084#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF46D241085 1086#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF46D281087 1088#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF46D2C1089 1090#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF46D301091 1092#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF46D341093 1094#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF46D381095 1096#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF46D3C1097 1098#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF46D401099 1100#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF46D441101 1102#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF46D481103 1104#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF46D4C1105 1106#define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE 0xF46D501107 1108#define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF46D541109 1110#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF46D581111 1112#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF46D5C1113 1114#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF46D601115 1116#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF46D641117 1118#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF46D681119 1120#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF46D6C1121 1122#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF46D701123 1124#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF46D741125 1126#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF46D781127 1128#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF46D7C1129 1130#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D801131 1132#define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR 0xF46D841133 1134#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46D881135 1136#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46D8C1137 1138#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46D901139 1140#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46D941141 1142#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46D981143 1144#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46D9C1145 1146#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46DA01147 1148#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46DA41149 1150#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46DA81151 1152#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46DAC1153 1154#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46DB01155 1156#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46DB41157 1158#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46DB81159 1160#define mmTPC5_CFG_QM_KERNEL_ID 0xF46DBC1161 1162#define mmTPC5_CFG_QM_SRF_0 0xF46DC01163 1164#define mmTPC5_CFG_QM_SRF_1 0xF46DC41165 1166#define mmTPC5_CFG_QM_SRF_2 0xF46DC81167 1168#define mmTPC5_CFG_QM_SRF_3 0xF46DCC1169 1170#define mmTPC5_CFG_QM_SRF_4 0xF46DD01171 1172#define mmTPC5_CFG_QM_SRF_5 0xF46DD41173 1174#define mmTPC5_CFG_QM_SRF_6 0xF46DD81175 1176#define mmTPC5_CFG_QM_SRF_7 0xF46DDC1177 1178#define mmTPC5_CFG_QM_SRF_8 0xF46DE01179 1180#define mmTPC5_CFG_QM_SRF_9 0xF46DE41181 1182#define mmTPC5_CFG_QM_SRF_10 0xF46DE81183 1184#define mmTPC5_CFG_QM_SRF_11 0xF46DEC1185 1186#define mmTPC5_CFG_QM_SRF_12 0xF46DF01187 1188#define mmTPC5_CFG_QM_SRF_13 0xF46DF41189 1190#define mmTPC5_CFG_QM_SRF_14 0xF46DF81191 1192#define mmTPC5_CFG_QM_SRF_15 0xF46DFC1193 1194#define mmTPC5_CFG_QM_SRF_16 0xF46E001195 1196#define mmTPC5_CFG_QM_SRF_17 0xF46E041197 1198#define mmTPC5_CFG_QM_SRF_18 0xF46E081199 1200#define mmTPC5_CFG_QM_SRF_19 0xF46E0C1201 1202#define mmTPC5_CFG_QM_SRF_20 0xF46E101203 1204#define mmTPC5_CFG_QM_SRF_21 0xF46E141205 1206#define mmTPC5_CFG_QM_SRF_22 0xF46E181207 1208#define mmTPC5_CFG_QM_SRF_23 0xF46E1C1209 1210#define mmTPC5_CFG_QM_SRF_24 0xF46E201211 1212#define mmTPC5_CFG_QM_SRF_25 0xF46E241213 1214#define mmTPC5_CFG_QM_SRF_26 0xF46E281215 1216#define mmTPC5_CFG_QM_SRF_27 0xF46E2C1217 1218#define mmTPC5_CFG_QM_SRF_28 0xF46E301219 1220#define mmTPC5_CFG_QM_SRF_29 0xF46E341221 1222#define mmTPC5_CFG_QM_SRF_30 0xF46E381223 1224#define mmTPC5_CFG_QM_SRF_31 0xF46E3C1225 1226#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */1227