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1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC5_QM_REGS_H_14#define ASIC_REG_TPC5_QM_REGS_H_15 16/*17 *****************************************18 * TPC5_QM (Prototype: QMAN)19 *****************************************20 */21 22#define mmTPC5_QM_GLBL_CFG0 0xF4800023 24#define mmTPC5_QM_GLBL_CFG1 0xF4800425 26#define mmTPC5_QM_GLBL_PROT 0xF4800827 28#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C29 30#define mmTPC5_QM_GLBL_SECURE_PROPS_0 0xF4801031 32#define mmTPC5_QM_GLBL_SECURE_PROPS_1 0xF4801433 34#define mmTPC5_QM_GLBL_SECURE_PROPS_2 0xF4801835 36#define mmTPC5_QM_GLBL_SECURE_PROPS_3 0xF4801C37 38#define mmTPC5_QM_GLBL_SECURE_PROPS_4 0xF4802039 40#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 0xF4802441 42#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 0xF4802843 44#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 0xF4802C45 46#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 0xF4803047 48#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 0xF4803449 50#define mmTPC5_QM_GLBL_STS0 0xF4803851 52#define mmTPC5_QM_GLBL_STS1_0 0xF4804053 54#define mmTPC5_QM_GLBL_STS1_1 0xF4804455 56#define mmTPC5_QM_GLBL_STS1_2 0xF4804857 58#define mmTPC5_QM_GLBL_STS1_3 0xF4804C59 60#define mmTPC5_QM_GLBL_STS1_4 0xF4805061 62#define mmTPC5_QM_GLBL_MSG_EN_0 0xF4805463 64#define mmTPC5_QM_GLBL_MSG_EN_1 0xF4805865 66#define mmTPC5_QM_GLBL_MSG_EN_2 0xF4805C67 68#define mmTPC5_QM_GLBL_MSG_EN_3 0xF4806069 70#define mmTPC5_QM_GLBL_MSG_EN_4 0xF4806871 72#define mmTPC5_QM_PQ_BASE_LO_0 0xF4807073 74#define mmTPC5_QM_PQ_BASE_LO_1 0xF4807475 76#define mmTPC5_QM_PQ_BASE_LO_2 0xF4807877 78#define mmTPC5_QM_PQ_BASE_LO_3 0xF4807C79 80#define mmTPC5_QM_PQ_BASE_HI_0 0xF4808081 82#define mmTPC5_QM_PQ_BASE_HI_1 0xF4808483 84#define mmTPC5_QM_PQ_BASE_HI_2 0xF4808885 86#define mmTPC5_QM_PQ_BASE_HI_3 0xF4808C87 88#define mmTPC5_QM_PQ_SIZE_0 0xF4809089 90#define mmTPC5_QM_PQ_SIZE_1 0xF4809491 92#define mmTPC5_QM_PQ_SIZE_2 0xF4809893 94#define mmTPC5_QM_PQ_SIZE_3 0xF4809C95 96#define mmTPC5_QM_PQ_PI_0 0xF480A097 98#define mmTPC5_QM_PQ_PI_1 0xF480A499 100#define mmTPC5_QM_PQ_PI_2 0xF480A8101 102#define mmTPC5_QM_PQ_PI_3 0xF480AC103 104#define mmTPC5_QM_PQ_CI_0 0xF480B0105 106#define mmTPC5_QM_PQ_CI_1 0xF480B4107 108#define mmTPC5_QM_PQ_CI_2 0xF480B8109 110#define mmTPC5_QM_PQ_CI_3 0xF480BC111 112#define mmTPC5_QM_PQ_CFG0_0 0xF480C0113 114#define mmTPC5_QM_PQ_CFG0_1 0xF480C4115 116#define mmTPC5_QM_PQ_CFG0_2 0xF480C8117 118#define mmTPC5_QM_PQ_CFG0_3 0xF480CC119 120#define mmTPC5_QM_PQ_CFG1_0 0xF480D0121 122#define mmTPC5_QM_PQ_CFG1_1 0xF480D4123 124#define mmTPC5_QM_PQ_CFG1_2 0xF480D8125 126#define mmTPC5_QM_PQ_CFG1_3 0xF480DC127 128#define mmTPC5_QM_PQ_ARUSER_31_11_0 0xF480E0129 130#define mmTPC5_QM_PQ_ARUSER_31_11_1 0xF480E4131 132#define mmTPC5_QM_PQ_ARUSER_31_11_2 0xF480E8133 134#define mmTPC5_QM_PQ_ARUSER_31_11_3 0xF480EC135 136#define mmTPC5_QM_PQ_STS0_0 0xF480F0137 138#define mmTPC5_QM_PQ_STS0_1 0xF480F4139 140#define mmTPC5_QM_PQ_STS0_2 0xF480F8141 142#define mmTPC5_QM_PQ_STS0_3 0xF480FC143 144#define mmTPC5_QM_PQ_STS1_0 0xF48100145 146#define mmTPC5_QM_PQ_STS1_1 0xF48104147 148#define mmTPC5_QM_PQ_STS1_2 0xF48108149 150#define mmTPC5_QM_PQ_STS1_3 0xF4810C151 152#define mmTPC5_QM_CQ_CFG0_0 0xF48110153 154#define mmTPC5_QM_CQ_CFG0_1 0xF48114155 156#define mmTPC5_QM_CQ_CFG0_2 0xF48118157 158#define mmTPC5_QM_CQ_CFG0_3 0xF4811C159 160#define mmTPC5_QM_CQ_CFG0_4 0xF48120161 162#define mmTPC5_QM_CQ_CFG1_0 0xF48124163 164#define mmTPC5_QM_CQ_CFG1_1 0xF48128165 166#define mmTPC5_QM_CQ_CFG1_2 0xF4812C167 168#define mmTPC5_QM_CQ_CFG1_3 0xF48130169 170#define mmTPC5_QM_CQ_CFG1_4 0xF48134171 172#define mmTPC5_QM_CQ_ARUSER_31_11_0 0xF48138173 174#define mmTPC5_QM_CQ_ARUSER_31_11_1 0xF4813C175 176#define mmTPC5_QM_CQ_ARUSER_31_11_2 0xF48140177 178#define mmTPC5_QM_CQ_ARUSER_31_11_3 0xF48144179 180#define mmTPC5_QM_CQ_ARUSER_31_11_4 0xF48148181 182#define mmTPC5_QM_CQ_STS0_0 0xF4814C183 184#define mmTPC5_QM_CQ_STS0_1 0xF48150185 186#define mmTPC5_QM_CQ_STS0_2 0xF48154187 188#define mmTPC5_QM_CQ_STS0_3 0xF48158189 190#define mmTPC5_QM_CQ_STS0_4 0xF4815C191 192#define mmTPC5_QM_CQ_STS1_0 0xF48160193 194#define mmTPC5_QM_CQ_STS1_1 0xF48164195 196#define mmTPC5_QM_CQ_STS1_2 0xF48168197 198#define mmTPC5_QM_CQ_STS1_3 0xF4816C199 200#define mmTPC5_QM_CQ_STS1_4 0xF48170201 202#define mmTPC5_QM_CQ_PTR_LO_0 0xF48174203 204#define mmTPC5_QM_CQ_PTR_HI_0 0xF48178205 206#define mmTPC5_QM_CQ_TSIZE_0 0xF4817C207 208#define mmTPC5_QM_CQ_CTL_0 0xF48180209 210#define mmTPC5_QM_CQ_PTR_LO_1 0xF48184211 212#define mmTPC5_QM_CQ_PTR_HI_1 0xF48188213 214#define mmTPC5_QM_CQ_TSIZE_1 0xF4818C215 216#define mmTPC5_QM_CQ_CTL_1 0xF48190217 218#define mmTPC5_QM_CQ_PTR_LO_2 0xF48194219 220#define mmTPC5_QM_CQ_PTR_HI_2 0xF48198221 222#define mmTPC5_QM_CQ_TSIZE_2 0xF4819C223 224#define mmTPC5_QM_CQ_CTL_2 0xF481A0225 226#define mmTPC5_QM_CQ_PTR_LO_3 0xF481A4227 228#define mmTPC5_QM_CQ_PTR_HI_3 0xF481A8229 230#define mmTPC5_QM_CQ_TSIZE_3 0xF481AC231 232#define mmTPC5_QM_CQ_CTL_3 0xF481B0233 234#define mmTPC5_QM_CQ_PTR_LO_4 0xF481B4235 236#define mmTPC5_QM_CQ_PTR_HI_4 0xF481B8237 238#define mmTPC5_QM_CQ_TSIZE_4 0xF481BC239 240#define mmTPC5_QM_CQ_CTL_4 0xF481C0241 242#define mmTPC5_QM_CQ_PTR_LO_STS_0 0xF481C4243 244#define mmTPC5_QM_CQ_PTR_LO_STS_1 0xF481C8245 246#define mmTPC5_QM_CQ_PTR_LO_STS_2 0xF481CC247 248#define mmTPC5_QM_CQ_PTR_LO_STS_3 0xF481D0249 250#define mmTPC5_QM_CQ_PTR_LO_STS_4 0xF481D4251 252#define mmTPC5_QM_CQ_PTR_HI_STS_0 0xF481D8253 254#define mmTPC5_QM_CQ_PTR_HI_STS_1 0xF481DC255 256#define mmTPC5_QM_CQ_PTR_HI_STS_2 0xF481E0257 258#define mmTPC5_QM_CQ_PTR_HI_STS_3 0xF481E4259 260#define mmTPC5_QM_CQ_PTR_HI_STS_4 0xF481E8261 262#define mmTPC5_QM_CQ_TSIZE_STS_0 0xF481EC263 264#define mmTPC5_QM_CQ_TSIZE_STS_1 0xF481F0265 266#define mmTPC5_QM_CQ_TSIZE_STS_2 0xF481F4267 268#define mmTPC5_QM_CQ_TSIZE_STS_3 0xF481F8269 270#define mmTPC5_QM_CQ_TSIZE_STS_4 0xF481FC271 272#define mmTPC5_QM_CQ_CTL_STS_0 0xF48200273 274#define mmTPC5_QM_CQ_CTL_STS_1 0xF48204275 276#define mmTPC5_QM_CQ_CTL_STS_2 0xF48208277 278#define mmTPC5_QM_CQ_CTL_STS_3 0xF4820C279 280#define mmTPC5_QM_CQ_CTL_STS_4 0xF48210281 282#define mmTPC5_QM_CQ_IFIFO_CNT_0 0xF48214283 284#define mmTPC5_QM_CQ_IFIFO_CNT_1 0xF48218285 286#define mmTPC5_QM_CQ_IFIFO_CNT_2 0xF4821C287 288#define mmTPC5_QM_CQ_IFIFO_CNT_3 0xF48220289 290#define mmTPC5_QM_CQ_IFIFO_CNT_4 0xF48224291 292#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 0xF48228293 294#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 0xF4822C295 296#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 0xF48230297 298#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 0xF48234299 300#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 0xF48238301 302#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 0xF4823C303 304#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 0xF48240305 306#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 0xF48244307 308#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 0xF48248309 310#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 0xF4824C311 312#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 0xF48250313 314#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 0xF48254315 316#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 0xF48258317 318#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 0xF4825C319 320#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 0xF48260321 322#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 0xF48264323 324#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 0xF48268325 326#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 0xF4826C327 328#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 0xF48270329 330#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 0xF48274331 332#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 0xF48278333 334#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 0xF4827C335 336#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 0xF48280337 338#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 0xF48284339 340#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 0xF48288341 342#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 0xF4828C343 344#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 0xF48290345 346#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 0xF48294347 348#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 0xF48298349 350#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 0xF4829C351 352#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 0xF482A0353 354#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 0xF482A4355 356#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 0xF482A8357 358#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 0xF482AC359 360#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 0xF482B0361 362#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 0xF482B4363 364#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 0xF482B8365 366#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 0xF482BC367 368#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 0xF482C0369 370#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 0xF482C4371 372#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 0xF482C8373 374#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 0xF482CC375 376#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 0xF482D0377 378#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 0xF482D4379 380#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 0xF482D8381 382#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF482E0383 384#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF482E4385 386#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF482E8387 388#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF482EC389 390#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF482F0391 392#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF482F4393 394#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF482F8395 396#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF482FC397 398#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF48300399 400#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF48304401 402#define mmTPC5_QM_CP_FENCE0_RDATA_0 0xF48308403 404#define mmTPC5_QM_CP_FENCE0_RDATA_1 0xF4830C405 406#define mmTPC5_QM_CP_FENCE0_RDATA_2 0xF48310407 408#define mmTPC5_QM_CP_FENCE0_RDATA_3 0xF48314409 410#define mmTPC5_QM_CP_FENCE0_RDATA_4 0xF48318411 412#define mmTPC5_QM_CP_FENCE1_RDATA_0 0xF4831C413 414#define mmTPC5_QM_CP_FENCE1_RDATA_1 0xF48320415 416#define mmTPC5_QM_CP_FENCE1_RDATA_2 0xF48324417 418#define mmTPC5_QM_CP_FENCE1_RDATA_3 0xF48328419 420#define mmTPC5_QM_CP_FENCE1_RDATA_4 0xF4832C421 422#define mmTPC5_QM_CP_FENCE2_RDATA_0 0xF48330423 424#define mmTPC5_QM_CP_FENCE2_RDATA_1 0xF48334425 426#define mmTPC5_QM_CP_FENCE2_RDATA_2 0xF48338427 428#define mmTPC5_QM_CP_FENCE2_RDATA_3 0xF4833C429 430#define mmTPC5_QM_CP_FENCE2_RDATA_4 0xF48340431 432#define mmTPC5_QM_CP_FENCE3_RDATA_0 0xF48344433 434#define mmTPC5_QM_CP_FENCE3_RDATA_1 0xF48348435 436#define mmTPC5_QM_CP_FENCE3_RDATA_2 0xF4834C437 438#define mmTPC5_QM_CP_FENCE3_RDATA_3 0xF48350439 440#define mmTPC5_QM_CP_FENCE3_RDATA_4 0xF48354441 442#define mmTPC5_QM_CP_FENCE0_CNT_0 0xF48358443 444#define mmTPC5_QM_CP_FENCE0_CNT_1 0xF4835C445 446#define mmTPC5_QM_CP_FENCE0_CNT_2 0xF48360447 448#define mmTPC5_QM_CP_FENCE0_CNT_3 0xF48364449 450#define mmTPC5_QM_CP_FENCE0_CNT_4 0xF48368451 452#define mmTPC5_QM_CP_FENCE1_CNT_0 0xF4836C453 454#define mmTPC5_QM_CP_FENCE1_CNT_1 0xF48370455 456#define mmTPC5_QM_CP_FENCE1_CNT_2 0xF48374457 458#define mmTPC5_QM_CP_FENCE1_CNT_3 0xF48378459 460#define mmTPC5_QM_CP_FENCE1_CNT_4 0xF4837C461 462#define mmTPC5_QM_CP_FENCE2_CNT_0 0xF48380463 464#define mmTPC5_QM_CP_FENCE2_CNT_1 0xF48384465 466#define mmTPC5_QM_CP_FENCE2_CNT_2 0xF48388467 468#define mmTPC5_QM_CP_FENCE2_CNT_3 0xF4838C469 470#define mmTPC5_QM_CP_FENCE2_CNT_4 0xF48390471 472#define mmTPC5_QM_CP_FENCE3_CNT_0 0xF48394473 474#define mmTPC5_QM_CP_FENCE3_CNT_1 0xF48398475 476#define mmTPC5_QM_CP_FENCE3_CNT_2 0xF4839C477 478#define mmTPC5_QM_CP_FENCE3_CNT_3 0xF483A0479 480#define mmTPC5_QM_CP_FENCE3_CNT_4 0xF483A4481 482#define mmTPC5_QM_CP_STS_0 0xF483A8483 484#define mmTPC5_QM_CP_STS_1 0xF483AC485 486#define mmTPC5_QM_CP_STS_2 0xF483B0487 488#define mmTPC5_QM_CP_STS_3 0xF483B4489 490#define mmTPC5_QM_CP_STS_4 0xF483B8491 492#define mmTPC5_QM_CP_CURRENT_INST_LO_0 0xF483BC493 494#define mmTPC5_QM_CP_CURRENT_INST_LO_1 0xF483C0495 496#define mmTPC5_QM_CP_CURRENT_INST_LO_2 0xF483C4497 498#define mmTPC5_QM_CP_CURRENT_INST_LO_3 0xF483C8499 500#define mmTPC5_QM_CP_CURRENT_INST_LO_4 0xF483CC501 502#define mmTPC5_QM_CP_CURRENT_INST_HI_0 0xF483D0503 504#define mmTPC5_QM_CP_CURRENT_INST_HI_1 0xF483D4505 506#define mmTPC5_QM_CP_CURRENT_INST_HI_2 0xF483D8507 508#define mmTPC5_QM_CP_CURRENT_INST_HI_3 0xF483DC509 510#define mmTPC5_QM_CP_CURRENT_INST_HI_4 0xF483E0511 512#define mmTPC5_QM_CP_BARRIER_CFG_0 0xF483F4513 514#define mmTPC5_QM_CP_BARRIER_CFG_1 0xF483F8515 516#define mmTPC5_QM_CP_BARRIER_CFG_2 0xF483FC517 518#define mmTPC5_QM_CP_BARRIER_CFG_3 0xF48400519 520#define mmTPC5_QM_CP_BARRIER_CFG_4 0xF48404521 522#define mmTPC5_QM_CP_DBG_0_0 0xF48408523 524#define mmTPC5_QM_CP_DBG_0_1 0xF4840C525 526#define mmTPC5_QM_CP_DBG_0_2 0xF48410527 528#define mmTPC5_QM_CP_DBG_0_3 0xF48414529 530#define mmTPC5_QM_CP_DBG_0_4 0xF48418531 532#define mmTPC5_QM_CP_ARUSER_31_11_0 0xF4841C533 534#define mmTPC5_QM_CP_ARUSER_31_11_1 0xF48420535 536#define mmTPC5_QM_CP_ARUSER_31_11_2 0xF48424537 538#define mmTPC5_QM_CP_ARUSER_31_11_3 0xF48428539 540#define mmTPC5_QM_CP_ARUSER_31_11_4 0xF4842C541 542#define mmTPC5_QM_CP_AWUSER_31_11_0 0xF48430543 544#define mmTPC5_QM_CP_AWUSER_31_11_1 0xF48434545 546#define mmTPC5_QM_CP_AWUSER_31_11_2 0xF48438547 548#define mmTPC5_QM_CP_AWUSER_31_11_3 0xF4843C549 550#define mmTPC5_QM_CP_AWUSER_31_11_4 0xF48440551 552#define mmTPC5_QM_ARB_CFG_0 0xF48A00553 554#define mmTPC5_QM_ARB_CHOISE_Q_PUSH 0xF48A04555 556#define mmTPC5_QM_ARB_WRR_WEIGHT_0 0xF48A08557 558#define mmTPC5_QM_ARB_WRR_WEIGHT_1 0xF48A0C559 560#define mmTPC5_QM_ARB_WRR_WEIGHT_2 0xF48A10561 562#define mmTPC5_QM_ARB_WRR_WEIGHT_3 0xF48A14563 564#define mmTPC5_QM_ARB_CFG_1 0xF48A18565 566#define mmTPC5_QM_ARB_MST_AVAIL_CRED_0 0xF48A20567 568#define mmTPC5_QM_ARB_MST_AVAIL_CRED_1 0xF48A24569 570#define mmTPC5_QM_ARB_MST_AVAIL_CRED_2 0xF48A28571 572#define mmTPC5_QM_ARB_MST_AVAIL_CRED_3 0xF48A2C573 574#define mmTPC5_QM_ARB_MST_AVAIL_CRED_4 0xF48A30575 576#define mmTPC5_QM_ARB_MST_AVAIL_CRED_5 0xF48A34577 578#define mmTPC5_QM_ARB_MST_AVAIL_CRED_6 0xF48A38579 580#define mmTPC5_QM_ARB_MST_AVAIL_CRED_7 0xF48A3C581 582#define mmTPC5_QM_ARB_MST_AVAIL_CRED_8 0xF48A40583 584#define mmTPC5_QM_ARB_MST_AVAIL_CRED_9 0xF48A44585 586#define mmTPC5_QM_ARB_MST_AVAIL_CRED_10 0xF48A48587 588#define mmTPC5_QM_ARB_MST_AVAIL_CRED_11 0xF48A4C589 590#define mmTPC5_QM_ARB_MST_AVAIL_CRED_12 0xF48A50591 592#define mmTPC5_QM_ARB_MST_AVAIL_CRED_13 0xF48A54593 594#define mmTPC5_QM_ARB_MST_AVAIL_CRED_14 0xF48A58595 596#define mmTPC5_QM_ARB_MST_AVAIL_CRED_15 0xF48A5C597 598#define mmTPC5_QM_ARB_MST_AVAIL_CRED_16 0xF48A60599 600#define mmTPC5_QM_ARB_MST_AVAIL_CRED_17 0xF48A64601 602#define mmTPC5_QM_ARB_MST_AVAIL_CRED_18 0xF48A68603 604#define mmTPC5_QM_ARB_MST_AVAIL_CRED_19 0xF48A6C605 606#define mmTPC5_QM_ARB_MST_AVAIL_CRED_20 0xF48A70607 608#define mmTPC5_QM_ARB_MST_AVAIL_CRED_21 0xF48A74609 610#define mmTPC5_QM_ARB_MST_AVAIL_CRED_22 0xF48A78611 612#define mmTPC5_QM_ARB_MST_AVAIL_CRED_23 0xF48A7C613 614#define mmTPC5_QM_ARB_MST_AVAIL_CRED_24 0xF48A80615 616#define mmTPC5_QM_ARB_MST_AVAIL_CRED_25 0xF48A84617 618#define mmTPC5_QM_ARB_MST_AVAIL_CRED_26 0xF48A88619 620#define mmTPC5_QM_ARB_MST_AVAIL_CRED_27 0xF48A8C621 622#define mmTPC5_QM_ARB_MST_AVAIL_CRED_28 0xF48A90623 624#define mmTPC5_QM_ARB_MST_AVAIL_CRED_29 0xF48A94625 626#define mmTPC5_QM_ARB_MST_AVAIL_CRED_30 0xF48A98627 628#define mmTPC5_QM_ARB_MST_AVAIL_CRED_31 0xF48A9C629 630#define mmTPC5_QM_ARB_MST_CRED_INC 0xF48AA0631 632#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF48AA4633 634#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF48AA8635 636#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF48AAC637 638#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF48AB0639 640#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF48AB4641 642#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF48AB8643 644#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF48ABC645 646#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF48AC0647 648#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF48AC4649 650#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF48AC8651 652#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF48ACC653 654#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF48AD0655 656#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF48AD4657 658#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF48AD8659 660#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF48ADC661 662#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF48AE0663 664#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF48AE4665 666#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF48AE8667 668#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF48AEC669 670#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF48AF0671 672#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF48AF4673 674#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF48AF8675 676#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF48AFC677 678#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF48B00679 680#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF48B04681 682#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF48B08683 684#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF48B0C685 686#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF48B10687 688#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF48B14689 690#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF48B18691 692#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF48B1C693 694#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF48B20695 696#define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF48B28697 698#define mmTPC5_QM_ARB_MST_SLAVE_EN 0xF48B2C699 700#define mmTPC5_QM_ARB_MST_QUIET_PER 0xF48B34701 702#define mmTPC5_QM_ARB_SLV_CHOISE_WDT 0xF48B38703 704#define mmTPC5_QM_ARB_SLV_ID 0xF48B3C705 706#define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT 0xF48B44707 708#define mmTPC5_QM_ARB_MSG_AWUSER_31_11 0xF48B48709 710#define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP 0xF48B4C711 712#define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF48B50713 714#define mmTPC5_QM_ARB_BASE_LO 0xF48B54715 716#define mmTPC5_QM_ARB_BASE_HI 0xF48B58717 718#define mmTPC5_QM_ARB_STATE_STS 0xF48B80719 720#define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS 0xF48B84721 722#define mmTPC5_QM_ARB_MSG_STS 0xF48B88723 724#define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD 0xF48B8C725 726#define mmTPC5_QM_ARB_ERR_CAUSE 0xF48B9C727 728#define mmTPC5_QM_ARB_ERR_MSG_EN 0xF48BA0729 730#define mmTPC5_QM_ARB_ERR_STS_DRP 0xF48BA8731 732#define mmTPC5_QM_ARB_MST_CRED_STS_0 0xF48BB0733 734#define mmTPC5_QM_ARB_MST_CRED_STS_1 0xF48BB4735 736#define mmTPC5_QM_ARB_MST_CRED_STS_2 0xF48BB8737 738#define mmTPC5_QM_ARB_MST_CRED_STS_3 0xF48BBC739 740#define mmTPC5_QM_ARB_MST_CRED_STS_4 0xF48BC0741 742#define mmTPC5_QM_ARB_MST_CRED_STS_5 0xF48BC4743 744#define mmTPC5_QM_ARB_MST_CRED_STS_6 0xF48BC8745 746#define mmTPC5_QM_ARB_MST_CRED_STS_7 0xF48BCC747 748#define mmTPC5_QM_ARB_MST_CRED_STS_8 0xF48BD0749 750#define mmTPC5_QM_ARB_MST_CRED_STS_9 0xF48BD4751 752#define mmTPC5_QM_ARB_MST_CRED_STS_10 0xF48BD8753 754#define mmTPC5_QM_ARB_MST_CRED_STS_11 0xF48BDC755 756#define mmTPC5_QM_ARB_MST_CRED_STS_12 0xF48BE0757 758#define mmTPC5_QM_ARB_MST_CRED_STS_13 0xF48BE4759 760#define mmTPC5_QM_ARB_MST_CRED_STS_14 0xF48BE8761 762#define mmTPC5_QM_ARB_MST_CRED_STS_15 0xF48BEC763 764#define mmTPC5_QM_ARB_MST_CRED_STS_16 0xF48BF0765 766#define mmTPC5_QM_ARB_MST_CRED_STS_17 0xF48BF4767 768#define mmTPC5_QM_ARB_MST_CRED_STS_18 0xF48BF8769 770#define mmTPC5_QM_ARB_MST_CRED_STS_19 0xF48BFC771 772#define mmTPC5_QM_ARB_MST_CRED_STS_20 0xF48C00773 774#define mmTPC5_QM_ARB_MST_CRED_STS_21 0xF48C04775 776#define mmTPC5_QM_ARB_MST_CRED_STS_22 0xF48C08777 778#define mmTPC5_QM_ARB_MST_CRED_STS_23 0xF48C0C779 780#define mmTPC5_QM_ARB_MST_CRED_STS_24 0xF48C10781 782#define mmTPC5_QM_ARB_MST_CRED_STS_25 0xF48C14783 784#define mmTPC5_QM_ARB_MST_CRED_STS_26 0xF48C18785 786#define mmTPC5_QM_ARB_MST_CRED_STS_27 0xF48C1C787 788#define mmTPC5_QM_ARB_MST_CRED_STS_28 0xF48C20789 790#define mmTPC5_QM_ARB_MST_CRED_STS_29 0xF48C24791 792#define mmTPC5_QM_ARB_MST_CRED_STS_30 0xF48C28793 794#define mmTPC5_QM_ARB_MST_CRED_STS_31 0xF48C2C795 796#define mmTPC5_QM_CGM_CFG 0xF48C70797 798#define mmTPC5_QM_CGM_STS 0xF48C74799 800#define mmTPC5_QM_CGM_CFG1 0xF48C78801 802#define mmTPC5_QM_LOCAL_RANGE_BASE 0xF48C80803 804#define mmTPC5_QM_LOCAL_RANGE_SIZE 0xF48C84805 806#define mmTPC5_QM_CSMR_STRICT_PRIO_CFG 0xF48C90807 808#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 0xF48C94809 810#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 0xF48C98811 812#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 0xF48C9C813 814#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 0xF48CA0815 816#define mmTPC5_QM_GLBL_AXCACHE 0xF48CA4817 818#define mmTPC5_QM_IND_GW_APB_CFG 0xF48CB0819 820#define mmTPC5_QM_IND_GW_APB_WDATA 0xF48CB4821 822#define mmTPC5_QM_IND_GW_APB_RDATA 0xF48CB8823 824#define mmTPC5_QM_IND_GW_APB_STATUS 0xF48CBC825 826#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48CD0827 828#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48CD4829 830#define mmTPC5_QM_GLBL_ERR_WDATA 0xF48CD8831 832#define mmTPC5_QM_GLBL_MEM_INIT_BUSY 0xF48D00833 834#endif /* ASIC_REG_TPC5_QM_REGS_H_ */835