1227 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_TPC6_CFG_REGS_H_14#define ASIC_REG_TPC6_CFG_REGS_H_15 16/*17 *****************************************18 * TPC6_CFG (Prototype: TPC)19 *****************************************20 */21 22#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF8640023 24#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF8640425 26#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF8640827 28#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C29 30#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF8641031 32#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF8641433 34#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF8641835 36#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF8641C37 38#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF8642039 40#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF8642441 42#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF8642843 44#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF8642C45 46#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF8643047 48#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF8643449 50#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF8643851 52#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF8643C53 54#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF8644055 56#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF8644457 58#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF8644859 60#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF8644C61 62#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF8645063 64#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF8645465 66#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF8645867 68#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF8645C69 70#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF8646071 72#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF8646473 74#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF8646875 76#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF8646C77 78#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF8647079 80#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF8647481 82#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF8647883 84#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF8647C85 86#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF8648087 88#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF8648489 90#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF8648891 92#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF8648C93 94#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF8649095 96#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF8649497 98#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF8649899 100#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF8649C101 102#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864A0103 104#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864A4105 106#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864A8107 108#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864AC109 110#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864B0111 112#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864B4113 114#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864B8115 116#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864BC117 118#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF864C0119 120#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF864C4121 122#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF864C8123 124#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF864CC125 126#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF864D0127 128#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF864D4129 130#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF864D8131 132#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF864DC133 134#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF864E0135 136#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF864E4137 138#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF864E8139 140#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF864EC141 142#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF864F0143 144#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF864F4145 146#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF864F8147 148#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF864FC149 150#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86500151 152#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF86504153 154#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86508155 156#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF8650C157 158#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86510159 160#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86514161 162#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF86518163 164#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF8651C165 166#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86520167 168#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86524169 170#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF86528171 172#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF8652C173 174#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86530175 176#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF86534177 178#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF86538179 180#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF8653C181 182#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF86540183 184#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF86544185 186#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF86548187 188#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF8654C189 190#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF86550191 192#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF86554193 194#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF86558195 196#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF8655C197 198#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF86560199 200#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF86564201 202#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF86568203 204#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF8656C205 206#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF86570207 208#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF86574209 210#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF86578211 212#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF8657C213 214#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86580215 216#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF86584217 218#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86588219 220#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF8658C221 222#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF86590223 224#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86594225 226#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86598227 228#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF8659C229 230#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF865A0231 232#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF865A4233 234#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF865A8235 236#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF865AC237 238#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF865B0239 240#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF865B4241 242#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF865B8243 244#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF865BC245 246#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF865C0247 248#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF865C4249 250#define mmTPC6_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF865C8251 252#define mmTPC6_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF865CC253 254#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF865D0255 256#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF865D4257 258#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF865D8259 260#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF865DC261 262#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF865E0263 264#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF865E4265 266#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF865E8267 268#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF865EC269 270#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF865F0271 272#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF865F4273 274#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF865F8275 276#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF865FC277 278#define mmTPC6_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF86600279 280#define mmTPC6_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF86604281 282#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF86608283 284#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF8660C285 286#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF86610287 288#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF86614289 290#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF86618291 292#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF8661C293 294#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF86620295 296#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF86624297 298#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF86628299 300#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF8662C301 302#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF86630303 304#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF86634305 306#define mmTPC6_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF86638307 308#define mmTPC6_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF8663C309 310#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF86640311 312#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF86644313 314#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF86648315 316#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF8664C317 318#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF86650319 320#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF86654321 322#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF86658323 324#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF8665C325 326#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF86660327 328#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF86664329 330#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF86668331 332#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF8666C333 334#define mmTPC6_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF86670335 336#define mmTPC6_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF86674337 338#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF86678339 340#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF8667C341 342#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF86680343 344#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF86684345 346#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF86688347 348#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF8668C349 350#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF86690351 352#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF86694353 354#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF86698355 356#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF8669C357 358#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF866A0359 360#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF866A4361 362#define mmTPC6_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF866A8363 364#define mmTPC6_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF866AC365 366#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF866B0367 368#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF866B4369 370#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF866B8371 372#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF866BC373 374#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF866C0375 376#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF866C4377 378#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF866C8379 380#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF866CC381 382#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF866D0383 384#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF866D4385 386#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF866D8387 388#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF866DC389 390#define mmTPC6_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF866E0391 392#define mmTPC6_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF866E4393 394#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF866E8395 396#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF866EC397 398#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF866F0399 400#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF866F4401 402#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF866F8403 404#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF866FC405 406#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF86700407 408#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF86704409 410#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF86708411 412#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF8670C413 414#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF86710415 416#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF86714417 418#define mmTPC6_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF86718419 420#define mmTPC6_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF8671C421 422#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF86720423 424#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF86724425 426#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF86728427 428#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF8672C429 430#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF86730431 432#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF86734433 434#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF86738435 436#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF8673C437 438#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF86740439 440#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF86744441 442#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF86748443 444#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF8674C445 446#define mmTPC6_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF86750447 448#define mmTPC6_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF86754449 450#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF86758451 452#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF8675C453 454#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF86760455 456#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF86764457 458#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF86768459 460#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF8676C461 462#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF86770463 464#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF86774465 466#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF86778467 468#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF8677C469 470#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86780471 472#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF86784473 474#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86788475 476#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF8678C477 478#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86790479 480#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF86794481 482#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86798483 484#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF8679C485 486#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF867A0487 488#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF867A4489 490#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF867A8491 492#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF867AC493 494#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF867B0495 496#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF867B4497 498#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF867B8499 500#define mmTPC6_CFG_KERNEL_KERNEL_ID 0xF867BC501 502#define mmTPC6_CFG_KERNEL_SRF_0 0xF867C0503 504#define mmTPC6_CFG_KERNEL_SRF_1 0xF867C4505 506#define mmTPC6_CFG_KERNEL_SRF_2 0xF867C8507 508#define mmTPC6_CFG_KERNEL_SRF_3 0xF867CC509 510#define mmTPC6_CFG_KERNEL_SRF_4 0xF867D0511 512#define mmTPC6_CFG_KERNEL_SRF_5 0xF867D4513 514#define mmTPC6_CFG_KERNEL_SRF_6 0xF867D8515 516#define mmTPC6_CFG_KERNEL_SRF_7 0xF867DC517 518#define mmTPC6_CFG_KERNEL_SRF_8 0xF867E0519 520#define mmTPC6_CFG_KERNEL_SRF_9 0xF867E4521 522#define mmTPC6_CFG_KERNEL_SRF_10 0xF867E8523 524#define mmTPC6_CFG_KERNEL_SRF_11 0xF867EC525 526#define mmTPC6_CFG_KERNEL_SRF_12 0xF867F0527 528#define mmTPC6_CFG_KERNEL_SRF_13 0xF867F4529 530#define mmTPC6_CFG_KERNEL_SRF_14 0xF867F8531 532#define mmTPC6_CFG_KERNEL_SRF_15 0xF867FC533 534#define mmTPC6_CFG_KERNEL_SRF_16 0xF86800535 536#define mmTPC6_CFG_KERNEL_SRF_17 0xF86804537 538#define mmTPC6_CFG_KERNEL_SRF_18 0xF86808539 540#define mmTPC6_CFG_KERNEL_SRF_19 0xF8680C541 542#define mmTPC6_CFG_KERNEL_SRF_20 0xF86810543 544#define mmTPC6_CFG_KERNEL_SRF_21 0xF86814545 546#define mmTPC6_CFG_KERNEL_SRF_22 0xF86818547 548#define mmTPC6_CFG_KERNEL_SRF_23 0xF8681C549 550#define mmTPC6_CFG_KERNEL_SRF_24 0xF86820551 552#define mmTPC6_CFG_KERNEL_SRF_25 0xF86824553 554#define mmTPC6_CFG_KERNEL_SRF_26 0xF86828555 556#define mmTPC6_CFG_KERNEL_SRF_27 0xF8682C557 558#define mmTPC6_CFG_KERNEL_SRF_28 0xF86830559 560#define mmTPC6_CFG_KERNEL_SRF_29 0xF86834561 562#define mmTPC6_CFG_KERNEL_SRF_30 0xF86838563 564#define mmTPC6_CFG_KERNEL_SRF_31 0xF8683C565 566#define mmTPC6_CFG_ROUND_CSR 0xF868FC567 568#define mmTPC6_CFG_PROT 0xF86900569 570#define mmTPC6_CFG_SEMAPHORE 0xF86908571 572#define mmTPC6_CFG_VFLAGS 0xF8690C573 574#define mmTPC6_CFG_SFLAGS 0xF86910575 576#define mmTPC6_CFG_LFSR_POLYNOM 0xF86918577 578#define mmTPC6_CFG_STATUS 0xF8691C579 580#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86920581 582#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86924583 584#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8692C585 586#define mmTPC6_CFG_TPC_CMD 0xF86930587 588#define mmTPC6_CFG_TPC_EXECUTE 0xF86938589 590#define mmTPC6_CFG_TPC_STALL 0xF8693C591 592#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86940593 594#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86944595 596#define mmTPC6_CFG_RD_RATE_LIMIT 0xF86948597 598#define mmTPC6_CFG_WR_RATE_LIMIT 0xF86950599 600#define mmTPC6_CFG_MSS_CONFIG 0xF86954601 602#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86958603 604#define mmTPC6_CFG_TPC_INTR_MASK 0xF8695C605 606#define mmTPC6_CFG_WQ_CREDITS 0xF86960607 608#define mmTPC6_CFG_ARUSER_LO 0xF86964609 610#define mmTPC6_CFG_ARUSER_HI 0xF86968611 612#define mmTPC6_CFG_AWUSER_LO 0xF8696C613 614#define mmTPC6_CFG_AWUSER_HI 0xF86970615 616#define mmTPC6_CFG_OPCODE_EXEC 0xF86974617 618#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF86978619 620#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF8697C621 622#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF86980623 624#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF86984625 626#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF86988627 628#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF8698C629 630#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF86990631 632#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF86994633 634#define mmTPC6_CFG_TSB_CFG_MAX_SIZE 0xF86998635 636#define mmTPC6_CFG_TSB_CFG 0xF8699C637 638#define mmTPC6_CFG_DBGMEM_ADD 0xF869A0639 640#define mmTPC6_CFG_DBGMEM_DATA_WR 0xF869A4641 642#define mmTPC6_CFG_DBGMEM_DATA_RD 0xF869A8643 644#define mmTPC6_CFG_DBGMEM_CTRL 0xF869AC645 646#define mmTPC6_CFG_DBGMEM_RC 0xF869B0647 648#define mmTPC6_CFG_TSB_INFLIGHT_CNTR 0xF869B4649 650#define mmTPC6_CFG_WQ_INFLIGHT_CNTR 0xF869B8651 652#define mmTPC6_CFG_WQ_LBW_TOTAL_CNTR 0xF869BC653 654#define mmTPC6_CFG_WQ_HBW_TOTAL_CNTR 0xF869C0655 656#define mmTPC6_CFG_IRQ_OCCOUPY_CNTR 0xF869C4657 658#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF869D0659 660#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF869D4661 662#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF869D8663 664#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF869DC665 666#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF869E0667 668#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF869E4669 670#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF869E8671 672#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF869EC673 674#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF869F0675 676#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF869F4677 678#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF869F8679 680#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF869FC681 682#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00683 684#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04685 686#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08687 688#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C689 690#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10691 692#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14693 694#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A18695 696#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A1C697 698#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A20699 700#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A24701 702#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A28703 704#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A2C705 706#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A30707 708#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A34709 710#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A38711 712#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A3C713 714#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A40715 716#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A44717 718#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A48719 720#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A4C721 722#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A50723 724#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A54725 726#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A58727 728#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A5C729 730#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A60731 732#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A64733 734#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A68735 736#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A6C737 738#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A70739 740#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A74741 742#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86A78743 744#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86A7C745 746#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86A80747 748#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86A84749 750#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86A88751 752#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86A8C753 754#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86A90755 756#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86A94757 758#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86A98759 760#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86A9C761 762#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AA0763 764#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86AA4765 766#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AA8767 768#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AAC769 770#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AB0771 772#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AB4773 774#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AB8775 776#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86ABC777 778#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86AC0779 780#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86AC4781 782#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86AC8783 784#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86ACC785 786#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86AD0787 788#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86AD4789 790#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86AD8791 792#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86ADC793 794#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86AE0795 796#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86AE4797 798#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86AE8799 800#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86AEC801 802#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86AF0803 804#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86AF4805 806#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86AF8807 808#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86AFC809 810#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B00811 812#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B04813 814#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B08815 816#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B0C817 818#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B10819 820#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B14821 822#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B18823 824#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B1C825 826#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B20827 828#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B24829 830#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B28831 832#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B2C833 834#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B30835 836#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B34837 838#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86B38839 840#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86B3C841 842#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86B40843 844#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86B44845 846#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86B48847 848#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86B4C849 850#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86B50851 852#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86B54853 854#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86B58855 856#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86B5C857 858#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86B60859 860#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86B64861 862#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86B68863 864#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86B6C865 866#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86B70867 868#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86B74869 870#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86B78871 872#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86B7C873 874#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86B80875 876#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86B84877 878#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86B88879 880#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86B8C881 882#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86B90883 884#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86B94885 886#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86B98887 888#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86B9C889 890#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86BA0891 892#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86BA4893 894#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86BA8895 896#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86BAC897 898#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86BB0899 900#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86BB4901 902#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86BB8903 904#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86BBC905 906#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF86BC0907 908#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF86BC4909 910#define mmTPC6_CFG_QM_TENSOR_8_PADDING_VALUE 0xF86BC8911 912#define mmTPC6_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF86BCC913 914#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF86BD0915 916#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF86BD4917 918#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF86BD8919 920#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF86BDC921 922#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF86BE0923 924#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF86BE4925 926#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF86BE8927 928#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF86BEC929 930#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF86BF0931 932#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF86BF4933 934#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF86BF8935 936#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF86BFC937 938#define mmTPC6_CFG_QM_TENSOR_9_PADDING_VALUE 0xF86C00939 940#define mmTPC6_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF86C04941 942#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF86C08943 944#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF86C0C945 946#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF86C10947 948#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF86C14949 950#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF86C18951 952#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF86C1C953 954#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF86C20955 956#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF86C24957 958#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF86C28959 960#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF86C2C961 962#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF86C30963 964#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF86C34965 966#define mmTPC6_CFG_QM_TENSOR_10_PADDING_VALUE 0xF86C38967 968#define mmTPC6_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF86C3C969 970#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF86C40971 972#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF86C44973 974#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF86C48975 976#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF86C4C977 978#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF86C50979 980#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF86C54981 982#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF86C58983 984#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF86C5C985 986#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF86C60987 988#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF86C64989 990#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF86C68991 992#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF86C6C993 994#define mmTPC6_CFG_QM_TENSOR_11_PADDING_VALUE 0xF86C70995 996#define mmTPC6_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF86C74997 998#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF86C78999 1000#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF86C7C1001 1002#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF86C801003 1004#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF86C841005 1006#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF86C881007 1008#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF86C8C1009 1010#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF86C901011 1012#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF86C941013 1014#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF86C981015 1016#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF86C9C1017 1018#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF86CA01019 1020#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF86CA41021 1022#define mmTPC6_CFG_QM_TENSOR_12_PADDING_VALUE 0xF86CA81023 1024#define mmTPC6_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF86CAC1025 1026#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF86CB01027 1028#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF86CB41029 1030#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF86CB81031 1032#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF86CBC1033 1034#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF86CC01035 1036#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF86CC41037 1038#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF86CC81039 1040#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF86CCC1041 1042#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF86CD01043 1044#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF86CD41045 1046#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF86CD81047 1048#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF86CDC1049 1050#define mmTPC6_CFG_QM_TENSOR_13_PADDING_VALUE 0xF86CE01051 1052#define mmTPC6_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF86CE41053 1054#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF86CE81055 1056#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF86CEC1057 1058#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF86CF01059 1060#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF86CF41061 1062#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF86CF81063 1064#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF86CFC1065 1066#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF86D001067 1068#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF86D041069 1070#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF86D081071 1072#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF86D0C1073 1074#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF86D101075 1076#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF86D141077 1078#define mmTPC6_CFG_QM_TENSOR_14_PADDING_VALUE 0xF86D181079 1080#define mmTPC6_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF86D1C1081 1082#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF86D201083 1084#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF86D241085 1086#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF86D281087 1088#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF86D2C1089 1090#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF86D301091 1092#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF86D341093 1094#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF86D381095 1096#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF86D3C1097 1098#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF86D401099 1100#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF86D441101 1102#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF86D481103 1104#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF86D4C1105 1106#define mmTPC6_CFG_QM_TENSOR_15_PADDING_VALUE 0xF86D501107 1108#define mmTPC6_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF86D541109 1110#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF86D581111 1112#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF86D5C1113 1114#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF86D601115 1116#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF86D641117 1118#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF86D681119 1120#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF86D6C1121 1122#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF86D701123 1124#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF86D741125 1126#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF86D781127 1128#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF86D7C1129 1130#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D801131 1132#define mmTPC6_CFG_QM_SYNC_OBJECT_ADDR 0xF86D841133 1134#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86D881135 1136#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86D8C1137 1138#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86D901139 1140#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86D941141 1142#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86D981143 1144#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86D9C1145 1146#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86DA01147 1148#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86DA41149 1150#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86DA81151 1152#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86DAC1153 1154#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86DB01155 1156#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86DB41157 1158#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86DB81159 1160#define mmTPC6_CFG_QM_KERNEL_ID 0xF86DBC1161 1162#define mmTPC6_CFG_QM_SRF_0 0xF86DC01163 1164#define mmTPC6_CFG_QM_SRF_1 0xF86DC41165 1166#define mmTPC6_CFG_QM_SRF_2 0xF86DC81167 1168#define mmTPC6_CFG_QM_SRF_3 0xF86DCC1169 1170#define mmTPC6_CFG_QM_SRF_4 0xF86DD01171 1172#define mmTPC6_CFG_QM_SRF_5 0xF86DD41173 1174#define mmTPC6_CFG_QM_SRF_6 0xF86DD81175 1176#define mmTPC6_CFG_QM_SRF_7 0xF86DDC1177 1178#define mmTPC6_CFG_QM_SRF_8 0xF86DE01179 1180#define mmTPC6_CFG_QM_SRF_9 0xF86DE41181 1182#define mmTPC6_CFG_QM_SRF_10 0xF86DE81183 1184#define mmTPC6_CFG_QM_SRF_11 0xF86DEC1185 1186#define mmTPC6_CFG_QM_SRF_12 0xF86DF01187 1188#define mmTPC6_CFG_QM_SRF_13 0xF86DF41189 1190#define mmTPC6_CFG_QM_SRF_14 0xF86DF81191 1192#define mmTPC6_CFG_QM_SRF_15 0xF86DFC1193 1194#define mmTPC6_CFG_QM_SRF_16 0xF86E001195 1196#define mmTPC6_CFG_QM_SRF_17 0xF86E041197 1198#define mmTPC6_CFG_QM_SRF_18 0xF86E081199 1200#define mmTPC6_CFG_QM_SRF_19 0xF86E0C1201 1202#define mmTPC6_CFG_QM_SRF_20 0xF86E101203 1204#define mmTPC6_CFG_QM_SRF_21 0xF86E141205 1206#define mmTPC6_CFG_QM_SRF_22 0xF86E181207 1208#define mmTPC6_CFG_QM_SRF_23 0xF86E1C1209 1210#define mmTPC6_CFG_QM_SRF_24 0xF86E201211 1212#define mmTPC6_CFG_QM_SRF_25 0xF86E241213 1214#define mmTPC6_CFG_QM_SRF_26 0xF86E281215 1216#define mmTPC6_CFG_QM_SRF_27 0xF86E2C1217 1218#define mmTPC6_CFG_QM_SRF_28 0xF86E301219 1220#define mmTPC6_CFG_QM_SRF_29 0xF86E341221 1222#define mmTPC6_CFG_QM_SRF_30 0xF86E381223 1224#define mmTPC6_CFG_QM_SRF_31 0xF86E3C1225 1226#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */1227