105 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_CPU_PLL_REGS_H_14#define ASIC_REG_CPU_PLL_REGS_H_15 16/*17 *****************************************18 * CPU_PLL (Prototype: PLL)19 *****************************************20 */21 22#define mmCPU_PLL_NR 0x4A210023 24#define mmCPU_PLL_NF 0x4A210425 26#define mmCPU_PLL_OD 0x4A210827 28#define mmCPU_PLL_NB 0x4A210C29 30#define mmCPU_PLL_CFG 0x4A211031 32#define mmCPU_PLL_LOSE_MASK 0x4A212033 34#define mmCPU_PLL_LOCK_INTR 0x4A212835 36#define mmCPU_PLL_LOCK_BYPASS 0x4A212C37 38#define mmCPU_PLL_DATA_CHNG 0x4A213039 40#define mmCPU_PLL_RST 0x4A213441 42#define mmCPU_PLL_SLIP_WD_CNTR 0x4A215043 44#define mmCPU_PLL_DIV_FACTOR_0 0x4A220045 46#define mmCPU_PLL_DIV_FACTOR_1 0x4A220447 48#define mmCPU_PLL_DIV_FACTOR_2 0x4A220849 50#define mmCPU_PLL_DIV_FACTOR_3 0x4A220C51 52#define mmCPU_PLL_DIV_FACTOR_CMD_0 0x4A222053 54#define mmCPU_PLL_DIV_FACTOR_CMD_1 0x4A222455 56#define mmCPU_PLL_DIV_FACTOR_CMD_2 0x4A222857 58#define mmCPU_PLL_DIV_FACTOR_CMD_3 0x4A222C59 60#define mmCPU_PLL_DIV_SEL_0 0x4A228061 62#define mmCPU_PLL_DIV_SEL_1 0x4A228463 64#define mmCPU_PLL_DIV_SEL_2 0x4A228865 66#define mmCPU_PLL_DIV_SEL_3 0x4A228C67 68#define mmCPU_PLL_DIV_EN_0 0x4A22A069 70#define mmCPU_PLL_DIV_EN_1 0x4A22A471 72#define mmCPU_PLL_DIV_EN_2 0x4A22A873 74#define mmCPU_PLL_DIV_EN_3 0x4A22AC75 76#define mmCPU_PLL_DIV_FACTOR_BUSY_0 0x4A22C077 78#define mmCPU_PLL_DIV_FACTOR_BUSY_1 0x4A22C479 80#define mmCPU_PLL_DIV_FACTOR_BUSY_2 0x4A22C881 82#define mmCPU_PLL_DIV_FACTOR_BUSY_3 0x4A22CC83 84#define mmCPU_PLL_CLK_GATER 0x4A230085 86#define mmCPU_PLL_CLK_RLX_0 0x4A231087 88#define mmCPU_PLL_CLK_RLX_1 0x4A231489 90#define mmCPU_PLL_CLK_RLX_2 0x4A231891 92#define mmCPU_PLL_CLK_RLX_3 0x4A231C93 94#define mmCPU_PLL_REF_CNTR_PERIOD 0x4A240095 96#define mmCPU_PLL_REF_LOW_THRESHOLD 0x4A241097 98#define mmCPU_PLL_REF_HIGH_THRESHOLD 0x4A242099 100#define mmCPU_PLL_PLL_NOT_STABLE 0x4A2430101 102#define mmCPU_PLL_FREQ_CALC_EN 0x4A2440103 104#endif /* ASIC_REG_CPU_PLL_REGS_H_ */105