.. cpu_ca53_cfg_masks.h cpu_ca53_cfg_regs.h cpu_if_regs.h cpu_pll_regs.h dma_ch_0_masks.h dma_ch_0_regs.h dma_ch_1_regs.h dma_ch_2_regs.h dma_ch_3_regs.h dma_ch_4_regs.h dma_macro_masks.h dma_macro_regs.h dma_nrtr_masks.h dma_nrtr_regs.h dma_qm_0_masks.h dma_qm_0_regs.h dma_qm_1_regs.h dma_qm_2_regs.h dma_qm_3_regs.h dma_qm_4_regs.h goya_blocks.h goya_masks.h goya_regs.h ic_pll_regs.h mc_pll_regs.h mme_cmdq_masks.h mme_cmdq_regs.h mme_masks.h mme_qm_masks.h mme_qm_regs.h mme_regs.h mme1_rtr_masks.h mme1_rtr_regs.h mme2_rtr_regs.h mme3_rtr_regs.h mme4_rtr_regs.h mme5_rtr_regs.h mme6_rtr_regs.h mmu_masks.h mmu_regs.h pci_nrtr_masks.h pci_nrtr_regs.h pcie_aux_regs.h pcie_wrap_regs.h psoc_emmc_pll_regs.h psoc_etr_regs.h psoc_global_conf_masks.h psoc_global_conf_regs.h psoc_mme_pll_regs.h psoc_pci_pll_regs.h psoc_spi_regs.h psoc_timestamp_regs.h sram_y0_x0_rtr_regs.h sram_y0_x1_rtr_regs.h sram_y0_x2_rtr_regs.h sram_y0_x3_rtr_regs.h sram_y0_x4_rtr_regs.h stlb_masks.h stlb_regs.h tpc_pll_regs.h tpc0_cfg_masks.h tpc0_cfg_regs.h tpc0_cmdq_masks.h tpc0_cmdq_regs.h tpc0_eml_cfg_masks.h tpc0_eml_cfg_regs.h tpc0_nrtr_masks.h tpc0_nrtr_regs.h tpc0_qm_masks.h tpc0_qm_regs.h tpc1_cfg_regs.h tpc1_cmdq_regs.h tpc1_qm_regs.h tpc1_rtr_regs.h tpc2_cfg_regs.h tpc2_cmdq_regs.h tpc2_qm_regs.h tpc2_rtr_regs.h tpc3_cfg_regs.h tpc3_cmdq_regs.h tpc3_qm_regs.h tpc3_rtr_regs.h tpc4_cfg_regs.h tpc4_cmdq_regs.h tpc4_qm_regs.h tpc4_rtr_regs.h tpc5_cfg_regs.h tpc5_cmdq_regs.h tpc5_qm_regs.h tpc5_rtr_regs.h tpc6_cfg_regs.h tpc6_cmdq_regs.h tpc6_qm_regs.h tpc6_rtr_regs.h tpc7_cfg_regs.h tpc7_cmdq_regs.h tpc7_nrtr_regs.h tpc7_qm_regs.h