105 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA_MACRO_MASKS_H_14#define ASIC_REG_DMA_MACRO_MASKS_H_15 16/*17 *****************************************18 * DMA_MACRO (Prototype: DMA_MACRO)19 *****************************************20 */21 22/* DMA_MACRO_LBW_RANGE_HIT_BLOCK */23#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT 024#define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK 0xFFFF25 26/* DMA_MACRO_LBW_RANGE_MASK */27#define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT 028#define DMA_MACRO_LBW_RANGE_MASK_R_MASK 0x3FFFFFF29 30/* DMA_MACRO_LBW_RANGE_BASE */31#define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT 032#define DMA_MACRO_LBW_RANGE_BASE_R_MASK 0x3FFFFFF33 34/* DMA_MACRO_HBW_RANGE_HIT_BLOCK */35#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT 036#define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK 0xFF37 38/* DMA_MACRO_HBW_RANGE_MASK_49_32 */39#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT 040#define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK 0x3FFFF41 42/* DMA_MACRO_HBW_RANGE_MASK_31_0 */43#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT 044#define DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK 0xFFFFFFFF45 46/* DMA_MACRO_HBW_RANGE_BASE_49_32 */47#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT 048#define DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK 0x3FFFF49 50/* DMA_MACRO_HBW_RANGE_BASE_31_0 */51#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT 052#define DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK 0xFFFFFFFF53 54/* DMA_MACRO_WRITE_EN */55#define DMA_MACRO_WRITE_EN_R_SHIFT 056#define DMA_MACRO_WRITE_EN_R_MASK 0x157 58/* DMA_MACRO_WRITE_CREDIT */59#define DMA_MACRO_WRITE_CREDIT_R_SHIFT 060#define DMA_MACRO_WRITE_CREDIT_R_MASK 0x3FF61 62/* DMA_MACRO_READ_EN */63#define DMA_MACRO_READ_EN_R_SHIFT 064#define DMA_MACRO_READ_EN_R_MASK 0x165 66/* DMA_MACRO_READ_CREDIT */67#define DMA_MACRO_READ_CREDIT_R_SHIFT 068#define DMA_MACRO_READ_CREDIT_R_MASK 0x3FF69 70/* DMA_MACRO_SRAM_BUSY */71 72/* DMA_MACRO_RAZWI_LBW_WT_VLD */73#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT 074#define DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK 0x175 76/* DMA_MACRO_RAZWI_LBW_WT_ID */77#define DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT 078#define DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK 0x7FFF79 80/* DMA_MACRO_RAZWI_LBW_RD_VLD */81#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT 082#define DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK 0x183 84/* DMA_MACRO_RAZWI_LBW_RD_ID */85#define DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT 086#define DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK 0x7FFF87 88/* DMA_MACRO_RAZWI_HBW_WT_VLD */89#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT 090#define DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK 0x191 92/* DMA_MACRO_RAZWI_HBW_WT_ID */93#define DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT 094#define DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK 0x1FFFFFFF95 96/* DMA_MACRO_RAZWI_HBW_RD_VLD */97#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT 098#define DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK 0x199 100/* DMA_MACRO_RAZWI_HBW_RD_ID */101#define DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT 0102#define DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK 0x1FFFFFFF103 104#endif /* ASIC_REG_DMA_MACRO_MASKS_H_ */105