227 lines · c
1/* SPDX-License-Identifier: GPL-2.02 *3 * Copyright 2016-2018 HabanaLabs, Ltd.4 * All Rights Reserved.5 *6 */7 8/************************************9 ** This is an auto-generated file **10 ** DO NOT EDIT BELOW **11 ************************************/12 13#ifndef ASIC_REG_DMA_NRTR_REGS_H_14#define ASIC_REG_DMA_NRTR_REGS_H_15 16/*17 *****************************************18 * DMA_NRTR (Prototype: IF_NRTR)19 *****************************************20 */21 22#define mmDMA_NRTR_HBW_MAX_CRED 0x1C010023 24#define mmDMA_NRTR_LBW_MAX_CRED 0x1C012025 26#define mmDMA_NRTR_DBG_E_ARB 0x1C030027 28#define mmDMA_NRTR_DBG_W_ARB 0x1C030429 30#define mmDMA_NRTR_DBG_N_ARB 0x1C030831 32#define mmDMA_NRTR_DBG_S_ARB 0x1C030C33 34#define mmDMA_NRTR_DBG_L_ARB 0x1C031035 36#define mmDMA_NRTR_DBG_E_ARB_MAX 0x1C032037 38#define mmDMA_NRTR_DBG_W_ARB_MAX 0x1C032439 40#define mmDMA_NRTR_DBG_N_ARB_MAX 0x1C032841 42#define mmDMA_NRTR_DBG_S_ARB_MAX 0x1C032C43 44#define mmDMA_NRTR_DBG_L_ARB_MAX 0x1C033045 46#define mmDMA_NRTR_SPLIT_COEF_0 0x1C040047 48#define mmDMA_NRTR_SPLIT_COEF_1 0x1C040449 50#define mmDMA_NRTR_SPLIT_COEF_2 0x1C040851 52#define mmDMA_NRTR_SPLIT_COEF_3 0x1C040C53 54#define mmDMA_NRTR_SPLIT_COEF_4 0x1C041055 56#define mmDMA_NRTR_SPLIT_COEF_5 0x1C041457 58#define mmDMA_NRTR_SPLIT_COEF_6 0x1C041859 60#define mmDMA_NRTR_SPLIT_COEF_7 0x1C041C61 62#define mmDMA_NRTR_SPLIT_COEF_8 0x1C042063 64#define mmDMA_NRTR_SPLIT_COEF_9 0x1C042465 66#define mmDMA_NRTR_SPLIT_CFG 0x1C044067 68#define mmDMA_NRTR_SPLIT_RD_SAT 0x1C044469 70#define mmDMA_NRTR_SPLIT_RD_RST_TOKEN 0x1C044871 72#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_0 0x1C044C73 74#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_1 0x1C045075 76#define mmDMA_NRTR_SPLIT_WR_SAT 0x1C045477 78#define mmDMA_NRTR_WPLIT_WR_TST_TOLEN 0x1C045879 80#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_0 0x1C045C81 82#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_1 0x1C046083 84#define mmDMA_NRTR_HBW_RANGE_HIT 0x1C047085 86#define mmDMA_NRTR_HBW_RANGE_MASK_L_0 0x1C048087 88#define mmDMA_NRTR_HBW_RANGE_MASK_L_1 0x1C048489 90#define mmDMA_NRTR_HBW_RANGE_MASK_L_2 0x1C048891 92#define mmDMA_NRTR_HBW_RANGE_MASK_L_3 0x1C048C93 94#define mmDMA_NRTR_HBW_RANGE_MASK_L_4 0x1C049095 96#define mmDMA_NRTR_HBW_RANGE_MASK_L_5 0x1C049497 98#define mmDMA_NRTR_HBW_RANGE_MASK_L_6 0x1C049899 100#define mmDMA_NRTR_HBW_RANGE_MASK_L_7 0x1C049C101 102#define mmDMA_NRTR_HBW_RANGE_MASK_H_0 0x1C04A0103 104#define mmDMA_NRTR_HBW_RANGE_MASK_H_1 0x1C04A4105 106#define mmDMA_NRTR_HBW_RANGE_MASK_H_2 0x1C04A8107 108#define mmDMA_NRTR_HBW_RANGE_MASK_H_3 0x1C04AC109 110#define mmDMA_NRTR_HBW_RANGE_MASK_H_4 0x1C04B0111 112#define mmDMA_NRTR_HBW_RANGE_MASK_H_5 0x1C04B4113 114#define mmDMA_NRTR_HBW_RANGE_MASK_H_6 0x1C04B8115 116#define mmDMA_NRTR_HBW_RANGE_MASK_H_7 0x1C04BC117 118#define mmDMA_NRTR_HBW_RANGE_BASE_L_0 0x1C04C0119 120#define mmDMA_NRTR_HBW_RANGE_BASE_L_1 0x1C04C4121 122#define mmDMA_NRTR_HBW_RANGE_BASE_L_2 0x1C04C8123 124#define mmDMA_NRTR_HBW_RANGE_BASE_L_3 0x1C04CC125 126#define mmDMA_NRTR_HBW_RANGE_BASE_L_4 0x1C04D0127 128#define mmDMA_NRTR_HBW_RANGE_BASE_L_5 0x1C04D4129 130#define mmDMA_NRTR_HBW_RANGE_BASE_L_6 0x1C04D8131 132#define mmDMA_NRTR_HBW_RANGE_BASE_L_7 0x1C04DC133 134#define mmDMA_NRTR_HBW_RANGE_BASE_H_0 0x1C04E0135 136#define mmDMA_NRTR_HBW_RANGE_BASE_H_1 0x1C04E4137 138#define mmDMA_NRTR_HBW_RANGE_BASE_H_2 0x1C04E8139 140#define mmDMA_NRTR_HBW_RANGE_BASE_H_3 0x1C04EC141 142#define mmDMA_NRTR_HBW_RANGE_BASE_H_4 0x1C04F0143 144#define mmDMA_NRTR_HBW_RANGE_BASE_H_5 0x1C04F4145 146#define mmDMA_NRTR_HBW_RANGE_BASE_H_6 0x1C04F8147 148#define mmDMA_NRTR_HBW_RANGE_BASE_H_7 0x1C04FC149 150#define mmDMA_NRTR_LBW_RANGE_HIT 0x1C0500151 152#define mmDMA_NRTR_LBW_RANGE_MASK_0 0x1C0510153 154#define mmDMA_NRTR_LBW_RANGE_MASK_1 0x1C0514155 156#define mmDMA_NRTR_LBW_RANGE_MASK_2 0x1C0518157 158#define mmDMA_NRTR_LBW_RANGE_MASK_3 0x1C051C159 160#define mmDMA_NRTR_LBW_RANGE_MASK_4 0x1C0520161 162#define mmDMA_NRTR_LBW_RANGE_MASK_5 0x1C0524163 164#define mmDMA_NRTR_LBW_RANGE_MASK_6 0x1C0528165 166#define mmDMA_NRTR_LBW_RANGE_MASK_7 0x1C052C167 168#define mmDMA_NRTR_LBW_RANGE_MASK_8 0x1C0530169 170#define mmDMA_NRTR_LBW_RANGE_MASK_9 0x1C0534171 172#define mmDMA_NRTR_LBW_RANGE_MASK_10 0x1C0538173 174#define mmDMA_NRTR_LBW_RANGE_MASK_11 0x1C053C175 176#define mmDMA_NRTR_LBW_RANGE_MASK_12 0x1C0540177 178#define mmDMA_NRTR_LBW_RANGE_MASK_13 0x1C0544179 180#define mmDMA_NRTR_LBW_RANGE_MASK_14 0x1C0548181 182#define mmDMA_NRTR_LBW_RANGE_MASK_15 0x1C054C183 184#define mmDMA_NRTR_LBW_RANGE_BASE_0 0x1C0550185 186#define mmDMA_NRTR_LBW_RANGE_BASE_1 0x1C0554187 188#define mmDMA_NRTR_LBW_RANGE_BASE_2 0x1C0558189 190#define mmDMA_NRTR_LBW_RANGE_BASE_3 0x1C055C191 192#define mmDMA_NRTR_LBW_RANGE_BASE_4 0x1C0560193 194#define mmDMA_NRTR_LBW_RANGE_BASE_5 0x1C0564195 196#define mmDMA_NRTR_LBW_RANGE_BASE_6 0x1C0568197 198#define mmDMA_NRTR_LBW_RANGE_BASE_7 0x1C056C199 200#define mmDMA_NRTR_LBW_RANGE_BASE_8 0x1C0570201 202#define mmDMA_NRTR_LBW_RANGE_BASE_9 0x1C0574203 204#define mmDMA_NRTR_LBW_RANGE_BASE_10 0x1C0578205 206#define mmDMA_NRTR_LBW_RANGE_BASE_11 0x1C057C207 208#define mmDMA_NRTR_LBW_RANGE_BASE_12 0x1C0580209 210#define mmDMA_NRTR_LBW_RANGE_BASE_13 0x1C0584211 212#define mmDMA_NRTR_LBW_RANGE_BASE_14 0x1C0588213 214#define mmDMA_NRTR_LBW_RANGE_BASE_15 0x1C058C215 216#define mmDMA_NRTR_RGLTR 0x1C0590217 218#define mmDMA_NRTR_RGLTR_WR_RESULT 0x1C0594219 220#define mmDMA_NRTR_RGLTR_RD_RESULT 0x1C0598221 222#define mmDMA_NRTR_SCRAMB_EN 0x1C0600223 224#define mmDMA_NRTR_NON_LIN_SCRAMB 0x1C0604225 226#endif /* ASIC_REG_DMA_NRTR_REGS_H_ */227